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drm/i915: Make i915 events part of uapi
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718dcedd
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1/*
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#ifndef _UAPI_I915_DRM_H_
28#define _UAPI_I915_DRM_H_
29
30#include <drm/drm.h>
31
32/* Please note that modifications to all structs defined here are
33 * subject to backwards-compatibility constraints.
34 */
35
cce723ed
BW
36/**
37 * DOC: uevents generated by i915 on it's device node
38 *
39 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
40 * event from the gpu l3 cache. Additional information supplied is ROW,
41 * BANK, SUBBANK of the affected cacheline. Userspace should keep track of
42 * these events and if a specific cache-line seems to have a persistent
43 * error remap it with the l3 remapping tool supplied in intel-gpu-tools.
44 * The value supplied with the event is always 1.
45 *
46 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
47 * hangcheck. The error detection event is a good indicator of when things
48 * began to go badly. The value supplied with the event is a 1 upon error
49 * detection, and a 0 upon reset completion, signifying no more error
50 * exists. NOTE: Disabling hangcheck or reset via module parameter will
51 * cause the related events to not be seen.
52 *
53 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
54 * the GPU. The value supplied with the event is always 1. NOTE: Disable
55 * reset via module parameter will cause this event to not be seen.
56 */
57#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
58#define I915_ERROR_UEVENT "ERROR"
59#define I915_RESET_UEVENT "RESET"
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60
61/* Each region is a minimum of 16k, and there are at most 255 of them.
62 */
63#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
64 * of chars for next/prev indices */
65#define I915_LOG_MIN_TEX_REGION_SIZE 14
66
67typedef struct _drm_i915_init {
68 enum {
69 I915_INIT_DMA = 0x01,
70 I915_CLEANUP_DMA = 0x02,
71 I915_RESUME_DMA = 0x03
72 } func;
73 unsigned int mmio_offset;
74 int sarea_priv_offset;
75 unsigned int ring_start;
76 unsigned int ring_end;
77 unsigned int ring_size;
78 unsigned int front_offset;
79 unsigned int back_offset;
80 unsigned int depth_offset;
81 unsigned int w;
82 unsigned int h;
83 unsigned int pitch;
84 unsigned int pitch_bits;
85 unsigned int back_pitch;
86 unsigned int depth_pitch;
87 unsigned int cpp;
88 unsigned int chipset;
89} drm_i915_init_t;
90
91typedef struct _drm_i915_sarea {
92 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
93 int last_upload; /* last time texture was uploaded */
94 int last_enqueue; /* last time a buffer was enqueued */
95 int last_dispatch; /* age of the most recently dispatched buffer */
96 int ctxOwner; /* last context to upload state */
97 int texAge;
98 int pf_enabled; /* is pageflipping allowed? */
99 int pf_active;
100 int pf_current_page; /* which buffer is being displayed? */
101 int perf_boxes; /* performance boxes to be displayed */
102 int width, height; /* screen size in pixels */
103
104 drm_handle_t front_handle;
105 int front_offset;
106 int front_size;
107
108 drm_handle_t back_handle;
109 int back_offset;
110 int back_size;
111
112 drm_handle_t depth_handle;
113 int depth_offset;
114 int depth_size;
115
116 drm_handle_t tex_handle;
117 int tex_offset;
118 int tex_size;
119 int log_tex_granularity;
120 int pitch;
121 int rotation; /* 0, 90, 180 or 270 */
122 int rotated_offset;
123 int rotated_size;
124 int rotated_pitch;
125 int virtualX, virtualY;
126
127 unsigned int front_tiled;
128 unsigned int back_tiled;
129 unsigned int depth_tiled;
130 unsigned int rotated_tiled;
131 unsigned int rotated2_tiled;
132
133 int pipeA_x;
134 int pipeA_y;
135 int pipeA_w;
136 int pipeA_h;
137 int pipeB_x;
138 int pipeB_y;
139 int pipeB_w;
140 int pipeB_h;
141
142 /* fill out some space for old userspace triple buffer */
143 drm_handle_t unused_handle;
144 __u32 unused1, unused2, unused3;
145
146 /* buffer object handles for static buffers. May change
147 * over the lifetime of the client.
148 */
149 __u32 front_bo_handle;
150 __u32 back_bo_handle;
151 __u32 unused_bo_handle;
152 __u32 depth_bo_handle;
153
154} drm_i915_sarea_t;
155
156/* due to userspace building against these headers we need some compat here */
157#define planeA_x pipeA_x
158#define planeA_y pipeA_y
159#define planeA_w pipeA_w
160#define planeA_h pipeA_h
161#define planeB_x pipeB_x
162#define planeB_y pipeB_y
163#define planeB_w pipeB_w
164#define planeB_h pipeB_h
165
166/* Flags for perf_boxes
167 */
168#define I915_BOX_RING_EMPTY 0x1
169#define I915_BOX_FLIP 0x2
170#define I915_BOX_WAIT 0x4
171#define I915_BOX_TEXTURE_LOAD 0x8
172#define I915_BOX_LOST_CONTEXT 0x10
173
174/* I915 specific ioctls
175 * The device specific ioctl range is 0x40 to 0x79.
176 */
177#define DRM_I915_INIT 0x00
178#define DRM_I915_FLUSH 0x01
179#define DRM_I915_FLIP 0x02
180#define DRM_I915_BATCHBUFFER 0x03
181#define DRM_I915_IRQ_EMIT 0x04
182#define DRM_I915_IRQ_WAIT 0x05
183#define DRM_I915_GETPARAM 0x06
184#define DRM_I915_SETPARAM 0x07
185#define DRM_I915_ALLOC 0x08
186#define DRM_I915_FREE 0x09
187#define DRM_I915_INIT_HEAP 0x0a
188#define DRM_I915_CMDBUFFER 0x0b
189#define DRM_I915_DESTROY_HEAP 0x0c
190#define DRM_I915_SET_VBLANK_PIPE 0x0d
191#define DRM_I915_GET_VBLANK_PIPE 0x0e
192#define DRM_I915_VBLANK_SWAP 0x0f
193#define DRM_I915_HWS_ADDR 0x11
194#define DRM_I915_GEM_INIT 0x13
195#define DRM_I915_GEM_EXECBUFFER 0x14
196#define DRM_I915_GEM_PIN 0x15
197#define DRM_I915_GEM_UNPIN 0x16
198#define DRM_I915_GEM_BUSY 0x17
199#define DRM_I915_GEM_THROTTLE 0x18
200#define DRM_I915_GEM_ENTERVT 0x19
201#define DRM_I915_GEM_LEAVEVT 0x1a
202#define DRM_I915_GEM_CREATE 0x1b
203#define DRM_I915_GEM_PREAD 0x1c
204#define DRM_I915_GEM_PWRITE 0x1d
205#define DRM_I915_GEM_MMAP 0x1e
206#define DRM_I915_GEM_SET_DOMAIN 0x1f
207#define DRM_I915_GEM_SW_FINISH 0x20
208#define DRM_I915_GEM_SET_TILING 0x21
209#define DRM_I915_GEM_GET_TILING 0x22
210#define DRM_I915_GEM_GET_APERTURE 0x23
211#define DRM_I915_GEM_MMAP_GTT 0x24
212#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
213#define DRM_I915_GEM_MADVISE 0x26
214#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
215#define DRM_I915_OVERLAY_ATTRS 0x28
216#define DRM_I915_GEM_EXECBUFFER2 0x29
217#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
218#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
219#define DRM_I915_GEM_WAIT 0x2c
220#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
221#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
222#define DRM_I915_GEM_SET_CACHING 0x2f
223#define DRM_I915_GEM_GET_CACHING 0x30
224#define DRM_I915_REG_READ 0x31
225
226#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
227#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
228#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
229#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
230#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
231#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
232#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
233#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
234#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
235#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
236#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
237#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
238#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
239#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
240#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
241#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
242#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
243#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
244#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
245#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
246#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
247#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
248#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
249#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
250#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
251#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
252#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
253#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
254#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
255#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
256#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
257#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
258#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
259#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
260#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
261#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
262#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
263#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
264#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
265#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
266#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
267#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
268#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
269#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
270#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
271#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
272#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
273#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
274
275/* Allow drivers to submit batchbuffers directly to hardware, relying
276 * on the security mechanisms provided by hardware.
277 */
278typedef struct drm_i915_batchbuffer {
279 int start; /* agp offset */
280 int used; /* nr bytes in use */
281 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
282 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
283 int num_cliprects; /* mulitpass with multiple cliprects? */
284 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
285} drm_i915_batchbuffer_t;
286
287/* As above, but pass a pointer to userspace buffer which can be
288 * validated by the kernel prior to sending to hardware.
289 */
290typedef struct _drm_i915_cmdbuffer {
291 char __user *buf; /* pointer to userspace command buffer */
292 int sz; /* nr bytes in buf */
293 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
294 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
295 int num_cliprects; /* mulitpass with multiple cliprects? */
296 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
297} drm_i915_cmdbuffer_t;
298
299/* Userspace can request & wait on irq's:
300 */
301typedef struct drm_i915_irq_emit {
302 int __user *irq_seq;
303} drm_i915_irq_emit_t;
304
305typedef struct drm_i915_irq_wait {
306 int irq_seq;
307} drm_i915_irq_wait_t;
308
309/* Ioctl to query kernel params:
310 */
311#define I915_PARAM_IRQ_ACTIVE 1
312#define I915_PARAM_ALLOW_BATCHBUFFER 2
313#define I915_PARAM_LAST_DISPATCH 3
314#define I915_PARAM_CHIPSET_ID 4
315#define I915_PARAM_HAS_GEM 5
316#define I915_PARAM_NUM_FENCES_AVAIL 6
317#define I915_PARAM_HAS_OVERLAY 7
318#define I915_PARAM_HAS_PAGEFLIPPING 8
319#define I915_PARAM_HAS_EXECBUF2 9
320#define I915_PARAM_HAS_BSD 10
321#define I915_PARAM_HAS_BLT 11
322#define I915_PARAM_HAS_RELAXED_FENCING 12
323#define I915_PARAM_HAS_COHERENT_RINGS 13
324#define I915_PARAM_HAS_EXEC_CONSTANTS 14
325#define I915_PARAM_HAS_RELAXED_DELTA 15
326#define I915_PARAM_HAS_GEN7_SOL_RESET 16
327#define I915_PARAM_HAS_LLC 17
328#define I915_PARAM_HAS_ALIASING_PPGTT 18
329#define I915_PARAM_HAS_WAIT_TIMEOUT 19
330#define I915_PARAM_HAS_SEMAPHORES 20
331#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
a1f2cc73 332#define I915_PARAM_HAS_VEBOX 22
c2fb7916 333#define I915_PARAM_HAS_SECURE_BATCHES 23
b45305fc 334#define I915_PARAM_HAS_PINNED_BATCHES 24
ed5982e6 335#define I915_PARAM_HAS_EXEC_NO_RELOC 25
eef90ccb 336#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
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337
338typedef struct drm_i915_getparam {
339 int param;
340 int __user *value;
341} drm_i915_getparam_t;
342
343/* Ioctl to set kernel params:
344 */
345#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
346#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
347#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
348#define I915_SETPARAM_NUM_USED_FENCES 4
349
350typedef struct drm_i915_setparam {
351 int param;
352 int value;
353} drm_i915_setparam_t;
354
355/* A memory manager for regions of shared memory:
356 */
357#define I915_MEM_REGION_AGP 1
358
359typedef struct drm_i915_mem_alloc {
360 int region;
361 int alignment;
362 int size;
363 int __user *region_offset; /* offset from start of fb or agp */
364} drm_i915_mem_alloc_t;
365
366typedef struct drm_i915_mem_free {
367 int region;
368 int region_offset;
369} drm_i915_mem_free_t;
370
371typedef struct drm_i915_mem_init_heap {
372 int region;
373 int size;
374 int start;
375} drm_i915_mem_init_heap_t;
376
377/* Allow memory manager to be torn down and re-initialized (eg on
378 * rotate):
379 */
380typedef struct drm_i915_mem_destroy_heap {
381 int region;
382} drm_i915_mem_destroy_heap_t;
383
384/* Allow X server to configure which pipes to monitor for vblank signals
385 */
386#define DRM_I915_VBLANK_PIPE_A 1
387#define DRM_I915_VBLANK_PIPE_B 2
388
389typedef struct drm_i915_vblank_pipe {
390 int pipe;
391} drm_i915_vblank_pipe_t;
392
393/* Schedule buffer swap at given vertical blank:
394 */
395typedef struct drm_i915_vblank_swap {
396 drm_drawable_t drawable;
397 enum drm_vblank_seq_type seqtype;
398 unsigned int sequence;
399} drm_i915_vblank_swap_t;
400
401typedef struct drm_i915_hws_addr {
402 __u64 addr;
403} drm_i915_hws_addr_t;
404
405struct drm_i915_gem_init {
406 /**
407 * Beginning offset in the GTT to be managed by the DRM memory
408 * manager.
409 */
410 __u64 gtt_start;
411 /**
412 * Ending offset in the GTT to be managed by the DRM memory
413 * manager.
414 */
415 __u64 gtt_end;
416};
417
418struct drm_i915_gem_create {
419 /**
420 * Requested size for the object.
421 *
422 * The (page-aligned) allocated size for the object will be returned.
423 */
424 __u64 size;
425 /**
426 * Returned handle for the object.
427 *
428 * Object handles are nonzero.
429 */
430 __u32 handle;
431 __u32 pad;
432};
433
434struct drm_i915_gem_pread {
435 /** Handle for the object being read. */
436 __u32 handle;
437 __u32 pad;
438 /** Offset into the object to read from */
439 __u64 offset;
440 /** Length of data to read */
441 __u64 size;
442 /**
443 * Pointer to write the data into.
444 *
445 * This is a fixed-size type for 32/64 compatibility.
446 */
447 __u64 data_ptr;
448};
449
450struct drm_i915_gem_pwrite {
451 /** Handle for the object being written to. */
452 __u32 handle;
453 __u32 pad;
454 /** Offset into the object to write to */
455 __u64 offset;
456 /** Length of data to write */
457 __u64 size;
458 /**
459 * Pointer to read the data from.
460 *
461 * This is a fixed-size type for 32/64 compatibility.
462 */
463 __u64 data_ptr;
464};
465
466struct drm_i915_gem_mmap {
467 /** Handle for the object being mapped. */
468 __u32 handle;
469 __u32 pad;
470 /** Offset in the object to map. */
471 __u64 offset;
472 /**
473 * Length of data to map.
474 *
475 * The value will be page-aligned.
476 */
477 __u64 size;
478 /**
479 * Returned pointer the data was mapped at.
480 *
481 * This is a fixed-size type for 32/64 compatibility.
482 */
483 __u64 addr_ptr;
484};
485
486struct drm_i915_gem_mmap_gtt {
487 /** Handle for the object being mapped. */
488 __u32 handle;
489 __u32 pad;
490 /**
491 * Fake offset to use for subsequent mmap call
492 *
493 * This is a fixed-size type for 32/64 compatibility.
494 */
495 __u64 offset;
496};
497
498struct drm_i915_gem_set_domain {
499 /** Handle for the object */
500 __u32 handle;
501
502 /** New read domains */
503 __u32 read_domains;
504
505 /** New write domain */
506 __u32 write_domain;
507};
508
509struct drm_i915_gem_sw_finish {
510 /** Handle for the object */
511 __u32 handle;
512};
513
514struct drm_i915_gem_relocation_entry {
515 /**
516 * Handle of the buffer being pointed to by this relocation entry.
517 *
518 * It's appealing to make this be an index into the mm_validate_entry
519 * list to refer to the buffer, but this allows the driver to create
520 * a relocation list for state buffers and not re-write it per
521 * exec using the buffer.
522 */
523 __u32 target_handle;
524
525 /**
526 * Value to be added to the offset of the target buffer to make up
527 * the relocation entry.
528 */
529 __u32 delta;
530
531 /** Offset in the buffer the relocation entry will be written into */
532 __u64 offset;
533
534 /**
535 * Offset value of the target buffer that the relocation entry was last
536 * written as.
537 *
538 * If the buffer has the same offset as last time, we can skip syncing
539 * and writing the relocation. This value is written back out by
540 * the execbuffer ioctl when the relocation is written.
541 */
542 __u64 presumed_offset;
543
544 /**
545 * Target memory domains read by this operation.
546 */
547 __u32 read_domains;
548
549 /**
550 * Target memory domains written by this operation.
551 *
552 * Note that only one domain may be written by the whole
553 * execbuffer operation, so that where there are conflicts,
554 * the application will get -EINVAL back.
555 */
556 __u32 write_domain;
557};
558
559/** @{
560 * Intel memory domains
561 *
562 * Most of these just align with the various caches in
563 * the system and are used to flush and invalidate as
564 * objects end up cached in different domains.
565 */
566/** CPU cache */
567#define I915_GEM_DOMAIN_CPU 0x00000001
568/** Render cache, used by 2D and 3D drawing */
569#define I915_GEM_DOMAIN_RENDER 0x00000002
570/** Sampler cache, used by texture engine */
571#define I915_GEM_DOMAIN_SAMPLER 0x00000004
572/** Command queue, used to load batch buffers */
573#define I915_GEM_DOMAIN_COMMAND 0x00000008
574/** Instruction cache, used by shader programs */
575#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
576/** Vertex address cache */
577#define I915_GEM_DOMAIN_VERTEX 0x00000020
578/** GTT domain - aperture and scanout */
579#define I915_GEM_DOMAIN_GTT 0x00000040
580/** @} */
581
582struct drm_i915_gem_exec_object {
583 /**
584 * User's handle for a buffer to be bound into the GTT for this
585 * operation.
586 */
587 __u32 handle;
588
589 /** Number of relocations to be performed on this buffer */
590 __u32 relocation_count;
591 /**
592 * Pointer to array of struct drm_i915_gem_relocation_entry containing
593 * the relocations to be performed in this buffer.
594 */
595 __u64 relocs_ptr;
596
597 /** Required alignment in graphics aperture */
598 __u64 alignment;
599
600 /**
601 * Returned value of the updated offset of the object, for future
602 * presumed_offset writes.
603 */
604 __u64 offset;
605};
606
607struct drm_i915_gem_execbuffer {
608 /**
609 * List of buffers to be validated with their relocations to be
610 * performend on them.
611 *
612 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
613 *
614 * These buffers must be listed in an order such that all relocations
615 * a buffer is performing refer to buffers that have already appeared
616 * in the validate list.
617 */
618 __u64 buffers_ptr;
619 __u32 buffer_count;
620
621 /** Offset in the batchbuffer to start execution from. */
622 __u32 batch_start_offset;
623 /** Bytes used in batchbuffer from batch_start_offset */
624 __u32 batch_len;
625 __u32 DR1;
626 __u32 DR4;
627 __u32 num_cliprects;
628 /** This is a struct drm_clip_rect *cliprects */
629 __u64 cliprects_ptr;
630};
631
632struct drm_i915_gem_exec_object2 {
633 /**
634 * User's handle for a buffer to be bound into the GTT for this
635 * operation.
636 */
637 __u32 handle;
638
639 /** Number of relocations to be performed on this buffer */
640 __u32 relocation_count;
641 /**
642 * Pointer to array of struct drm_i915_gem_relocation_entry containing
643 * the relocations to be performed in this buffer.
644 */
645 __u64 relocs_ptr;
646
647 /** Required alignment in graphics aperture */
648 __u64 alignment;
649
650 /**
651 * Returned value of the updated offset of the object, for future
652 * presumed_offset writes.
653 */
654 __u64 offset;
655
656#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
ed5982e6
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657#define EXEC_OBJECT_NEEDS_GTT (1<<1)
658#define EXEC_OBJECT_WRITE (1<<2)
659#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1)
718dcedd 660 __u64 flags;
ed5982e6 661
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662 __u64 rsvd1;
663 __u64 rsvd2;
664};
665
666struct drm_i915_gem_execbuffer2 {
667 /**
668 * List of gem_exec_object2 structs
669 */
670 __u64 buffers_ptr;
671 __u32 buffer_count;
672
673 /** Offset in the batchbuffer to start execution from. */
674 __u32 batch_start_offset;
675 /** Bytes used in batchbuffer from batch_start_offset */
676 __u32 batch_len;
677 __u32 DR1;
678 __u32 DR4;
679 __u32 num_cliprects;
680 /** This is a struct drm_clip_rect *cliprects */
681 __u64 cliprects_ptr;
682#define I915_EXEC_RING_MASK (7<<0)
683#define I915_EXEC_DEFAULT (0<<0)
684#define I915_EXEC_RENDER (1<<0)
685#define I915_EXEC_BSD (2<<0)
686#define I915_EXEC_BLT (3<<0)
82f91b6e 687#define I915_EXEC_VEBOX (4<<0)
718dcedd
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688
689/* Used for switching the constants addressing mode on gen4+ RENDER ring.
690 * Gen6+ only supports relative addressing to dynamic state (default) and
691 * absolute addressing.
692 *
693 * These flags are ignored for the BSD and BLT rings.
694 */
695#define I915_EXEC_CONSTANTS_MASK (3<<6)
696#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
697#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
698#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
699 __u64 flags;
700 __u64 rsvd1; /* now used for context info */
701 __u64 rsvd2;
702};
703
704/** Resets the SO write offset registers for transform feedback on gen7. */
705#define I915_EXEC_GEN7_SOL_RESET (1<<8)
706
c2fb7916
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707/** Request a privileged ("secure") batch buffer. Note only available for
708 * DRM_ROOT_ONLY | DRM_MASTER processes.
709 */
710#define I915_EXEC_SECURE (1<<9)
711
b45305fc
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712/** Inform the kernel that the batch is and will always be pinned. This
713 * negates the requirement for a workaround to be performed to avoid
714 * an incoherent CS (such as can be found on 830/845). If this flag is
715 * not passed, the kernel will endeavour to make sure the batch is
716 * coherent with the CS before execution. If this flag is passed,
717 * userspace assumes the responsibility for ensuring the same.
718 */
719#define I915_EXEC_IS_PINNED (1<<10)
720
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721/** Provide a hint to the kernel that the command stream and auxilliary
722 * state buffers already holds the correct presumed addresses and so the
723 * relocation process may be skipped if no buffers need to be moved in
724 * preparation for the execbuffer.
725 */
726#define I915_EXEC_NO_RELOC (1<<11)
727
eef90ccb
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728/** Use the reloc.handle as an index into the exec object array rather
729 * than as the per-file handle.
730 */
731#define I915_EXEC_HANDLE_LUT (1<<12)
732
733#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1)
ed5982e6 734
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735#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
736#define i915_execbuffer2_set_context_id(eb2, context) \
737 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
738#define i915_execbuffer2_get_context_id(eb2) \
739 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
740
741struct drm_i915_gem_pin {
742 /** Handle of the buffer to be pinned. */
743 __u32 handle;
744 __u32 pad;
745
746 /** alignment required within the aperture */
747 __u64 alignment;
748
749 /** Returned GTT offset of the buffer. */
750 __u64 offset;
751};
752
753struct drm_i915_gem_unpin {
754 /** Handle of the buffer to be unpinned. */
755 __u32 handle;
756 __u32 pad;
757};
758
759struct drm_i915_gem_busy {
760 /** Handle of the buffer to check for busy */
761 __u32 handle;
762
763 /** Return busy status (1 if busy, 0 if idle).
764 * The high word is used to indicate on which rings the object
765 * currently resides:
766 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
767 */
768 __u32 busy;
769};
770
771#define I915_CACHING_NONE 0
772#define I915_CACHING_CACHED 1
773
774struct drm_i915_gem_caching {
775 /**
776 * Handle of the buffer to set/get the caching level of. */
777 __u32 handle;
778
779 /**
780 * Cacheing level to apply or return value
781 *
782 * bits0-15 are for generic caching control (i.e. the above defined
783 * values). bits16-31 are reserved for platform-specific variations
784 * (e.g. l3$ caching on gen7). */
785 __u32 caching;
786};
787
788#define I915_TILING_NONE 0
789#define I915_TILING_X 1
790#define I915_TILING_Y 2
791
792#define I915_BIT_6_SWIZZLE_NONE 0
793#define I915_BIT_6_SWIZZLE_9 1
794#define I915_BIT_6_SWIZZLE_9_10 2
795#define I915_BIT_6_SWIZZLE_9_11 3
796#define I915_BIT_6_SWIZZLE_9_10_11 4
797/* Not seen by userland */
798#define I915_BIT_6_SWIZZLE_UNKNOWN 5
799/* Seen by userland. */
800#define I915_BIT_6_SWIZZLE_9_17 6
801#define I915_BIT_6_SWIZZLE_9_10_17 7
802
803struct drm_i915_gem_set_tiling {
804 /** Handle of the buffer to have its tiling state updated */
805 __u32 handle;
806
807 /**
808 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
809 * I915_TILING_Y).
810 *
811 * This value is to be set on request, and will be updated by the
812 * kernel on successful return with the actual chosen tiling layout.
813 *
814 * The tiling mode may be demoted to I915_TILING_NONE when the system
815 * has bit 6 swizzling that can't be managed correctly by GEM.
816 *
817 * Buffer contents become undefined when changing tiling_mode.
818 */
819 __u32 tiling_mode;
820
821 /**
822 * Stride in bytes for the object when in I915_TILING_X or
823 * I915_TILING_Y.
824 */
825 __u32 stride;
826
827 /**
828 * Returned address bit 6 swizzling required for CPU access through
829 * mmap mapping.
830 */
831 __u32 swizzle_mode;
832};
833
834struct drm_i915_gem_get_tiling {
835 /** Handle of the buffer to get tiling state for. */
836 __u32 handle;
837
838 /**
839 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
840 * I915_TILING_Y).
841 */
842 __u32 tiling_mode;
843
844 /**
845 * Returned address bit 6 swizzling required for CPU access through
846 * mmap mapping.
847 */
848 __u32 swizzle_mode;
849};
850
851struct drm_i915_gem_get_aperture {
852 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
853 __u64 aper_size;
854
855 /**
856 * Available space in the aperture used by i915_gem_execbuffer, in
857 * bytes
858 */
859 __u64 aper_available_size;
860};
861
862struct drm_i915_get_pipe_from_crtc_id {
863 /** ID of CRTC being requested **/
864 __u32 crtc_id;
865
866 /** pipe of requested CRTC **/
867 __u32 pipe;
868};
869
870#define I915_MADV_WILLNEED 0
871#define I915_MADV_DONTNEED 1
872#define __I915_MADV_PURGED 2 /* internal state */
873
874struct drm_i915_gem_madvise {
875 /** Handle of the buffer to change the backing store advice */
876 __u32 handle;
877
878 /* Advice: either the buffer will be needed again in the near future,
879 * or wont be and could be discarded under memory pressure.
880 */
881 __u32 madv;
882
883 /** Whether the backing store still exists. */
884 __u32 retained;
885};
886
887/* flags */
888#define I915_OVERLAY_TYPE_MASK 0xff
889#define I915_OVERLAY_YUV_PLANAR 0x01
890#define I915_OVERLAY_YUV_PACKED 0x02
891#define I915_OVERLAY_RGB 0x03
892
893#define I915_OVERLAY_DEPTH_MASK 0xff00
894#define I915_OVERLAY_RGB24 0x1000
895#define I915_OVERLAY_RGB16 0x2000
896#define I915_OVERLAY_RGB15 0x3000
897#define I915_OVERLAY_YUV422 0x0100
898#define I915_OVERLAY_YUV411 0x0200
899#define I915_OVERLAY_YUV420 0x0300
900#define I915_OVERLAY_YUV410 0x0400
901
902#define I915_OVERLAY_SWAP_MASK 0xff0000
903#define I915_OVERLAY_NO_SWAP 0x000000
904#define I915_OVERLAY_UV_SWAP 0x010000
905#define I915_OVERLAY_Y_SWAP 0x020000
906#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
907
908#define I915_OVERLAY_FLAGS_MASK 0xff000000
909#define I915_OVERLAY_ENABLE 0x01000000
910
911struct drm_intel_overlay_put_image {
912 /* various flags and src format description */
913 __u32 flags;
914 /* source picture description */
915 __u32 bo_handle;
916 /* stride values and offsets are in bytes, buffer relative */
917 __u16 stride_Y; /* stride for packed formats */
918 __u16 stride_UV;
919 __u32 offset_Y; /* offset for packet formats */
920 __u32 offset_U;
921 __u32 offset_V;
922 /* in pixels */
923 __u16 src_width;
924 __u16 src_height;
925 /* to compensate the scaling factors for partially covered surfaces */
926 __u16 src_scan_width;
927 __u16 src_scan_height;
928 /* output crtc description */
929 __u32 crtc_id;
930 __u16 dst_x;
931 __u16 dst_y;
932 __u16 dst_width;
933 __u16 dst_height;
934};
935
936/* flags */
937#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
938#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
939struct drm_intel_overlay_attrs {
940 __u32 flags;
941 __u32 color_key;
942 __s32 brightness;
943 __u32 contrast;
944 __u32 saturation;
945 __u32 gamma0;
946 __u32 gamma1;
947 __u32 gamma2;
948 __u32 gamma3;
949 __u32 gamma4;
950 __u32 gamma5;
951};
952
953/*
954 * Intel sprite handling
955 *
956 * Color keying works with a min/mask/max tuple. Both source and destination
957 * color keying is allowed.
958 *
959 * Source keying:
960 * Sprite pixels within the min & max values, masked against the color channels
961 * specified in the mask field, will be transparent. All other pixels will
962 * be displayed on top of the primary plane. For RGB surfaces, only the min
963 * and mask fields will be used; ranged compares are not allowed.
964 *
965 * Destination keying:
966 * Primary plane pixels that match the min value, masked against the color
967 * channels specified in the mask field, will be replaced by corresponding
968 * pixels from the sprite plane.
969 *
970 * Note that source & destination keying are exclusive; only one can be
971 * active on a given plane.
972 */
973
974#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
975#define I915_SET_COLORKEY_DESTINATION (1<<1)
976#define I915_SET_COLORKEY_SOURCE (1<<2)
977struct drm_intel_sprite_colorkey {
978 __u32 plane_id;
979 __u32 min_value;
980 __u32 channel_mask;
981 __u32 max_value;
982 __u32 flags;
983};
984
985struct drm_i915_gem_wait {
986 /** Handle of BO we shall wait on */
987 __u32 bo_handle;
988 __u32 flags;
989 /** Number of nanoseconds to wait, Returns time remaining. */
990 __s64 timeout_ns;
991};
992
993struct drm_i915_gem_context_create {
994 /* output: id of new context*/
995 __u32 ctx_id;
996 __u32 pad;
997};
998
999struct drm_i915_gem_context_destroy {
1000 __u32 ctx_id;
1001 __u32 pad;
1002};
1003
1004struct drm_i915_reg_read {
1005 __u64 offset;
1006 __u64 val; /* Return value */
1007};
1008#endif /* _UAPI_I915_DRM_H_ */