[mirror_ubuntu-artful-kernel.git] / include / uapi / drm / msm_drm.h

/*
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __MSM_DRM_H__
#define __MSM_DRM_H__

#include "drm.h"

#if defined(__cplusplus)
extern "C" {
#endif

/* Please note that modifications to all structs defined here are
 * subject to backwards-compatibility constraints:
 *  1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
 *     user/kernel compatibility
 *  2) Keep fields aligned to their size
 *  3) Because of how drm_ioctl() works, we can add new fields at
 *     the end of an ioctl if some care is taken: drm_ioctl() will
 *     zero out the new fields at the tail of the ioctl, so a zero
 *     value should have a backwards compatible meaning.  And for
 *     output params, userspace won't see the newly added output
 *     fields.. so that has to be somehow ok.
 */

#define MSM_PIPE_NONE        0x00
#define MSM_PIPE_2D0         0x01
#define MSM_PIPE_2D1         0x02
#define MSM_PIPE_3D0         0x10

/* The pipe-id just uses the lower bits, so can be OR'd with flags in
 * the upper 16 bits (which could be extended further, if needed, maybe
 * we extend/overload the pipe-id some day to deal with multiple rings,
 * but even then I don't think we need the full lower 16 bits).
 */
#define MSM_PIPE_ID_MASK     0xffff
#define MSM_PIPE_ID(x)       ((x) & MSM_PIPE_ID_MASK)
#define MSM_PIPE_FLAGS(x)    ((x) & ~MSM_PIPE_ID_MASK)

/* timeouts are specified in clock-monotonic absolute times (to simplify
 * restarting interrupted ioctls).  The following struct is logically the
 * same as 'struct timespec' but 32/64b ABI safe.
 */
struct drm_msm_timespec {
	__s64 tv_sec;          /* seconds */
	__s64 tv_nsec;         /* nanoseconds */
};

#define MSM_PARAM_GPU_ID     0x01
#define MSM_PARAM_GMEM_SIZE  0x02
#define MSM_PARAM_CHIP_ID    0x03
#define MSM_PARAM_MAX_FREQ   0x04
#define MSM_PARAM_TIMESTAMP  0x05

struct drm_msm_param {
	__u32 pipe;           /* in, MSM_PIPE_x */
	__u32 param;          /* in, MSM_PARAM_x */
	__u64 value;          /* out (get_param) or in (set_param) */
};

/*
 * GEM buffers:
 */

#define MSM_BO_SCANOUT       0x00000001     /* scanout capable */
#define MSM_BO_GPU_READONLY  0x00000002
#define MSM_BO_CACHE_MASK    0x000f0000
/* cache modes */
#define MSM_BO_CACHED        0x00010000
#define MSM_BO_WC            0x00020000
#define MSM_BO_UNCACHED      0x00040000

#define MSM_BO_FLAGS         (MSM_BO_SCANOUT | \
                              MSM_BO_GPU_READONLY | \
                              MSM_BO_CACHED | \
                              MSM_BO_WC | \
                              MSM_BO_UNCACHED)

struct drm_msm_gem_new {
	__u64 size;           /* in */
	__u32 flags;          /* in, mask of MSM_BO_x */
	__u32 handle;         /* out */
};

struct drm_msm_gem_info {
	__u32 handle;         /* in */
	__u32 pad;
	__u64 offset;         /* out, offset to pass to mmap() */
};

#define MSM_PREP_READ        0x01
#define MSM_PREP_WRITE       0x02
#define MSM_PREP_NOSYNC      0x04

#define MSM_PREP_FLAGS       (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)

struct drm_msm_gem_cpu_prep {
	__u32 handle;         /* in */
	__u32 op;             /* in, mask of MSM_PREP_x */
	struct drm_msm_timespec timeout;   /* in */
};

struct drm_msm_gem_cpu_fini {
	__u32 handle;         /* in */
};

/*
 * Cmdstream Submission:
 */

/* The value written into the cmdstream is logically:
 *
 *   ((relocbuf->gpuaddr + reloc_offset) << shift) | or
 *
 * When we have GPU's w/ >32bit ptrs, it should be possible to deal
 * with this by emit'ing two reloc entries with appropriate shift
 * values.  Or a new MSM_SUBMIT_CMD_x type would also be an option.
 *
 * NOTE that reloc's must be sorted by order of increasing submit_offset,
 * otherwise EINVAL.
 */
struct drm_msm_gem_submit_reloc {
	__u32 submit_offset;  /* in, offset from submit_bo */
	__u32 or;             /* in, value OR'd with result */
	__s32 shift;          /* in, amount of left shift (can be negative) */
	__u32 reloc_idx;      /* in, index of reloc_bo buffer */
	__u64 reloc_offset;   /* in, offset from start of reloc_bo */
};

/* submit-types:
 *   BUF - this cmd buffer is executed normally.
 *   IB_TARGET_BUF - this cmd buffer is an IB target.  Reloc's are
 *      processed normally, but the kernel does not setup an IB to
 *      this buffer in the first-level ringbuffer
 *   CTX_RESTORE_BUF - only executed if there has been a GPU context
 *      switch since the last SUBMIT ioctl
 */
#define MSM_SUBMIT_CMD_BUF             0x0001
#define MSM_SUBMIT_CMD_IB_TARGET_BUF   0x0002
#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
struct drm_msm_gem_submit_cmd {
	__u32 type;           /* in, one of MSM_SUBMIT_CMD_x */
	__u32 submit_idx;     /* in, index of submit_bo cmdstream buffer */
	__u32 submit_offset;  /* in, offset into submit_bo */
	__u32 size;           /* in, cmdstream size */
	__u32 pad;
	__u32 nr_relocs;      /* in, number of submit_reloc's */
	__u64 __user relocs;  /* in, ptr to array of submit_reloc's */
};

/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
 * cmdstream buffer(s) themselves or reloc entries) has one (and only
 * one) entry in the submit->bos[] table.
 *
 * As a optimization, the current buffer (gpu virtual address) can be
 * passed back through the 'presumed' field.  If on a subsequent reloc,
 * userspace passes back a 'presumed' address that is still valid,
 * then patching the cmdstream for this entry is skipped.  This can
 * avoid kernel needing to map/access the cmdstream bo in the common
 * case.
 */
#define MSM_SUBMIT_BO_READ             0x0001
#define MSM_SUBMIT_BO_WRITE            0x0002

#define MSM_SUBMIT_BO_FLAGS            (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)

struct drm_msm_gem_submit_bo {
	__u32 flags;          /* in, mask of MSM_SUBMIT_BO_x */
	__u32 handle;         /* in, GEM handle */
	__u64 presumed;       /* in/out, presumed buffer address */
};

/* Valid submit ioctl flags: */
/* to start, nothing.. */
#define MSM_SUBMIT_FLAGS 0

/* Each cmdstream submit consists of a table of buffers involved, and
 * one or more cmdstream buffers.  This allows for conditional execution
 * (context-restore), and IB buffers needed for per tile/bin draw cmds.
 */
struct drm_msm_gem_submit {
	__u32 flags;          /* MSM_PIPE_x | MSM_SUBMIT_x */
	__u32 fence;          /* out */
	__u32 nr_bos;         /* in, number of submit_bo's */
	__u32 nr_cmds;        /* in, number of submit_cmd's */
	__u64 __user bos;     /* in, ptr to array of submit_bo's */
	__u64 __user cmds;    /* in, ptr to array of submit_cmd's */
};

/* The normal way to synchronize with the GPU is just to CPU_PREP on
 * a buffer if you need to access it from the CPU (other cmdstream
 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
 * handle the required synchronization under the hood).  This ioctl
 * mainly just exists as a way to implement the gallium pipe_fence
 * APIs without requiring a dummy bo to synchronize on.
 */
struct drm_msm_wait_fence {
	__u32 fence;          /* in */
	__u32 pad;
	struct drm_msm_timespec timeout;   /* in */
};

/* madvise provides a way to tell the kernel in case a buffers contents
 * can be discarded under memory pressure, which is useful for userspace
 * bo cache where we want to optimistically hold on to buffer allocate
 * and potential mmap, but allow the pages to be discarded under memory
 * pressure.
 *
 * Typical usage would involve madvise(DONTNEED) when buffer enters BO
 * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
 * In the WILLNEED case, 'retained' indicates to userspace whether the
 * backing pages still exist.
 */
#define MSM_MADV_WILLNEED 0       /* backing pages are needed, status returned in 'retained' */
#define MSM_MADV_DONTNEED 1       /* backing pages not needed */
#define __MSM_MADV_PURGED 2       /* internal state */

struct drm_msm_gem_madvise {
	__u32 handle;         /* in, GEM handle */
	__u32 madv;           /* in, MSM_MADV_x */
	__u32 retained;       /* out, whether backing store still exists */
};

#define DRM_MSM_GET_PARAM              0x00
/* placeholder:
#define DRM_MSM_SET_PARAM              0x01
 */
#define DRM_MSM_GEM_NEW                0x02
#define DRM_MSM_GEM_INFO               0x03
#define DRM_MSM_GEM_CPU_PREP           0x04
#define DRM_MSM_GEM_CPU_FINI           0x05
#define DRM_MSM_GEM_SUBMIT             0x06
#define DRM_MSM_WAIT_FENCE             0x07
#define DRM_MSM_GEM_MADVISE            0x08
#define DRM_MSM_NUM_IOCTLS             0x09

#define DRM_IOCTL_MSM_GET_PARAM        DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
#define DRM_IOCTL_MSM_GEM_NEW          DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
#define DRM_IOCTL_MSM_GEM_INFO         DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
#define DRM_IOCTL_MSM_GEM_CPU_PREP     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
#define DRM_IOCTL_MSM_GEM_CPU_FINI     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
#define DRM_IOCTL_MSM_GEM_SUBMIT       DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
#define DRM_IOCTL_MSM_WAIT_FENCE       DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
#define DRM_IOCTL_MSM_GEM_MADVISE      DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)

#if defined(__cplusplus)
}
#endif

#endif /* __MSM_DRM_H__ */
Commit	Line	Data
7198e6b0 RC	1	/*
	2	* Copyright (C) 2013 Red Hat
	3	* Author: Rob Clark <robdclark@gmail.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published by
	7	* the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#ifndef __MSM_DRM_H__
	19	#define __MSM_DRM_H__
	20
06577d04	21	#include "drm.h"
7198e6b0	22
a62424e2 EV	23	#if defined(__cplusplus)
	24	extern "C" {
	25	#endif
	26
7198e6b0 RC	27	/* Please note that modifications to all structs defined here are
7198e6b0 RC	28	* subject to backwards-compatibility constraints:
7f8fc886	29	* 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
7198e6b0 RC	30	* user/kernel compatibility
	31	* 2) Keep fields aligned to their size
	32	* 3) Because of how drm_ioctl() works, we can add new fields at
	33	* the end of an ioctl if some care is taken: drm_ioctl() will
	34	* zero out the new fields at the tail of the ioctl, so a zero
	35	* value should have a backwards compatible meaning. And for
	36	* output params, userspace won't see the newly added output
	37	* fields.. so that has to be somehow ok.
	38	*/
	39
	40	#define MSM_PIPE_NONE 0x00
	41	#define MSM_PIPE_2D0 0x01
	42	#define MSM_PIPE_2D1 0x02
	43	#define MSM_PIPE_3D0 0x10
	44
d9c181e2 RC	45	/* The pipe-id just uses the lower bits, so can be OR'd with flags in
	46	* the upper 16 bits (which could be extended further, if needed, maybe
	47	* we extend/overload the pipe-id some day to deal with multiple rings,
	48	* but even then I don't think we need the full lower 16 bits).
	49	*/
	50	#define MSM_PIPE_ID_MASK 0xffff
	51	#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
	52	#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
	53
7198e6b0 RC	54	/* timeouts are specified in clock-monotonic absolute times (to simplify
	55	* restarting interrupted ioctls). The following struct is logically the
	56	* same as 'struct timespec' but 32/64b ABI safe.
	57	*/
	58	struct drm_msm_timespec {
7f8fc886 MR	59	__s64 tv_sec; /* seconds */
7f8fc886 MR	60	__s64 tv_nsec; /* nanoseconds */
7198e6b0 RC	61	};
	62
	63	#define MSM_PARAM_GPU_ID 0x01
	64	#define MSM_PARAM_GMEM_SIZE 0x02
4e1cbaa3	65	#define MSM_PARAM_CHIP_ID 0x03
4102a9e5	66	#define MSM_PARAM_MAX_FREQ 0x04
6c77d1ab	67	#define MSM_PARAM_TIMESTAMP 0x05
7198e6b0 RC	68
7198e6b0 RC	69	struct drm_msm_param {
7f8fc886 MR	70	__u32 pipe; /* in, MSM_PIPE_x */
	71	__u32 param; /* in, MSM_PARAM_x */
	72	__u64 value; /* out (get_param) or in (set_param) */
7198e6b0 RC	73	};
	74
	75	/*
	76	* GEM buffers:
	77	*/
	78
	79	#define MSM_BO_SCANOUT 0x00000001 /* scanout capable */
	80	#define MSM_BO_GPU_READONLY 0x00000002
	81	#define MSM_BO_CACHE_MASK 0x000f0000
	82	/* cache modes */
	83	#define MSM_BO_CACHED 0x00010000
	84	#define MSM_BO_WC 0x00020000
	85	#define MSM_BO_UNCACHED 0x00040000
	86
93ddb0d3 RC	87	#define MSM_BO_FLAGS (MSM_BO_SCANOUT \| \
	88	MSM_BO_GPU_READONLY \| \
	89	MSM_BO_CACHED \| \
	90	MSM_BO_WC \| \
	91	MSM_BO_UNCACHED)
	92
7198e6b0	93	struct drm_msm_gem_new {
7f8fc886 MR	94	__u64 size; /* in */
	95	__u32 flags; /* in, mask of MSM_BO_x */
	96	__u32 handle; /* out */
7198e6b0 RC	97	};
	98
	99	struct drm_msm_gem_info {
7f8fc886 MR	100	__u32 handle; /* in */
	101	__u32 pad;
	102	__u64 offset; /* out, offset to pass to mmap() */
7198e6b0 RC	103	};
	104
	105	#define MSM_PREP_READ 0x01
	106	#define MSM_PREP_WRITE 0x02
	107	#define MSM_PREP_NOSYNC 0x04
	108
93ddb0d3 RC	109	#define MSM_PREP_FLAGS (MSM_PREP_READ \| MSM_PREP_WRITE \| MSM_PREP_NOSYNC)
93ddb0d3 RC	110
7198e6b0	111	struct drm_msm_gem_cpu_prep {
7f8fc886 MR	112	__u32 handle; /* in */
7f8fc886 MR	113	__u32 op; /* in, mask of MSM_PREP_x */
7198e6b0 RC	114	struct drm_msm_timespec timeout; /* in */
	115	};
	116
	117	struct drm_msm_gem_cpu_fini {
7f8fc886	118	__u32 handle; /* in */
7198e6b0 RC	119	};
	120
	121	/*
	122	* Cmdstream Submission:
	123	*/
	124
	125	/* The value written into the cmdstream is logically:
	126	*
	127	* ((relocbuf->gpuaddr + reloc_offset) << shift) \| or
	128	*
	129	* When we have GPU's w/ >32bit ptrs, it should be possible to deal
	130	* with this by emit'ing two reloc entries with appropriate shift
	131	* values. Or a new MSM_SUBMIT_CMD_x type would also be an option.
	132	*
	133	* NOTE that reloc's must be sorted by order of increasing submit_offset,
	134	* otherwise EINVAL.
	135	*/
	136	struct drm_msm_gem_submit_reloc {
7f8fc886 MR	137	__u32 submit_offset; /* in, offset from submit_bo */
7f8fc886 MR	138	__u32 or; /* in, value OR'd with result */
8979a059	139	__s32 shift; /* in, amount of left shift (can be negative) */
7f8fc886 MR	140	__u32 reloc_idx; /* in, index of reloc_bo buffer */
7f8fc886 MR	141	__u64 reloc_offset; /* in, offset from start of reloc_bo */
7198e6b0 RC	142	};
	143
	144	/* submit-types:
	145	* BUF - this cmd buffer is executed normally.
	146	* IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are
	147	* processed normally, but the kernel does not setup an IB to
	148	* this buffer in the first-level ringbuffer
	149	* CTX_RESTORE_BUF - only executed if there has been a GPU context
	150	* switch since the last SUBMIT ioctl
	151	*/
	152	#define MSM_SUBMIT_CMD_BUF 0x0001
	153	#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
	154	#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
	155	struct drm_msm_gem_submit_cmd {
7f8fc886 MR	156	__u32 type; /* in, one of MSM_SUBMIT_CMD_x */
	157	__u32 submit_idx; /* in, index of submit_bo cmdstream buffer */
	158	__u32 submit_offset; /* in, offset into submit_bo */
	159	__u32 size; /* in, cmdstream size */
	160	__u32 pad;
	161	__u32 nr_relocs; /* in, number of submit_reloc's */
	162	__u64 __user relocs; /* in, ptr to array of submit_reloc's */
7198e6b0 RC	163	};
	164
	165	/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
	166	* cmdstream buffer(s) themselves or reloc entries) has one (and only
	167	* one) entry in the submit->bos[] table.
	168	*
	169	* As a optimization, the current buffer (gpu virtual address) can be
	170	* passed back through the 'presumed' field. If on a subsequent reloc,
	171	* userspace passes back a 'presumed' address that is still valid,
	172	* then patching the cmdstream for this entry is skipped. This can
	173	* avoid kernel needing to map/access the cmdstream bo in the common
	174	* case.
	175	*/
	176	#define MSM_SUBMIT_BO_READ 0x0001
	177	#define MSM_SUBMIT_BO_WRITE 0x0002
93ddb0d3 RC	178
	179	#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ \| MSM_SUBMIT_BO_WRITE)
	180
7198e6b0	181	struct drm_msm_gem_submit_bo {
7f8fc886 MR	182	__u32 flags; /* in, mask of MSM_SUBMIT_BO_x */
	183	__u32 handle; /* in, GEM handle */
	184	__u64 presumed; /* in/out, presumed buffer address */
7198e6b0 RC	185	};
7198e6b0 RC	186
d9c181e2 RC	187	/* Valid submit ioctl flags: */
	188	/* to start, nothing.. */
	189	#define MSM_SUBMIT_FLAGS 0
	190
7198e6b0 RC	191	/* Each cmdstream submit consists of a table of buffers involved, and
	192	* one or more cmdstream buffers. This allows for conditional execution
	193	* (context-restore), and IB buffers needed for per tile/bin draw cmds.
	194	*/
	195	struct drm_msm_gem_submit {
d9c181e2	196	__u32 flags; /* MSM_PIPE_x \| MSM_SUBMIT_x */
7f8fc886 MR	197	__u32 fence; /* out */
	198	__u32 nr_bos; /* in, number of submit_bo's */
	199	__u32 nr_cmds; /* in, number of submit_cmd's */
	200	__u64 __user bos; /* in, ptr to array of submit_bo's */
	201	__u64 __user cmds; /* in, ptr to array of submit_cmd's */
7198e6b0 RC	202	};
	203
	204	/* The normal way to synchronize with the GPU is just to CPU_PREP on
	205	* a buffer if you need to access it from the CPU (other cmdstream
	206	* submission from same or other contexts, PAGE_FLIP ioctl, etc, all
	207	* handle the required synchronization under the hood). This ioctl
	208	* mainly just exists as a way to implement the gallium pipe_fence
	209	* APIs without requiring a dummy bo to synchronize on.
	210	*/
	211	struct drm_msm_wait_fence {
7f8fc886 MR	212	__u32 fence; /* in */
7f8fc886 MR	213	__u32 pad;
7198e6b0 RC	214	struct drm_msm_timespec timeout; /* in */
	215	};
	216
4cd33c48 RC	217	/* madvise provides a way to tell the kernel in case a buffers contents
	218	* can be discarded under memory pressure, which is useful for userspace
	219	* bo cache where we want to optimistically hold on to buffer allocate
	220	* and potential mmap, but allow the pages to be discarded under memory
	221	* pressure.
	222	*
	223	* Typical usage would involve madvise(DONTNEED) when buffer enters BO
	224	* cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
	225	* In the WILLNEED case, 'retained' indicates to userspace whether the
	226	* backing pages still exist.
	227	*/
	228	#define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */
	229	#define MSM_MADV_DONTNEED 1 /* backing pages not needed */
	230	#define __MSM_MADV_PURGED 2 /* internal state */
	231
	232	struct drm_msm_gem_madvise {
	233	__u32 handle; /* in, GEM handle */
	234	__u32 madv; /* in, MSM_MADV_x */
	235	__u32 retained; /* out, whether backing store still exists */
	236	};
	237
7198e6b0 RC	238	#define DRM_MSM_GET_PARAM 0x00
	239	/* placeholder:
	240	#define DRM_MSM_SET_PARAM 0x01
	241	*/
	242	#define DRM_MSM_GEM_NEW 0x02
	243	#define DRM_MSM_GEM_INFO 0x03
	244	#define DRM_MSM_GEM_CPU_PREP 0x04
	245	#define DRM_MSM_GEM_CPU_FINI 0x05
	246	#define DRM_MSM_GEM_SUBMIT 0x06
	247	#define DRM_MSM_WAIT_FENCE 0x07
4cd33c48 RC	248	#define DRM_MSM_GEM_MADVISE 0x08
4cd33c48 RC	249	#define DRM_MSM_NUM_IOCTLS 0x09
7198e6b0 RC	250
	251	#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
	252	#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
	253	#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
	254	#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
	255	#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
	256	#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
	257	#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
4cd33c48	258	#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
7198e6b0	259
a62424e2 EV	260	#if defined(__cplusplus)
	261	}
	262	#endif
	263
7198e6b0	264	#endif /* __MSM_DRM_H__ */