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d43f81cb TB |
1 | /* |
2 | * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. | |
3 | * | |
248141db TR |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
d43f81cb | 10 | * |
248141db TR |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. | |
d43f81cb | 13 | * |
248141db TR |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
d43f81cb TB |
21 | */ |
22 | ||
23 | #ifndef _UAPI_TEGRA_DRM_H_ | |
24 | #define _UAPI_TEGRA_DRM_H_ | |
25 | ||
678205a6 | 26 | #include "drm.h" |
a191e48d | 27 | |
7aa8ceeb EV |
28 | #if defined(__cplusplus) |
29 | extern "C" { | |
30 | #endif | |
31 | ||
db7fbdfd TR |
32 | #define DRM_TEGRA_GEM_CREATE_TILED (1 << 0) |
33 | #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1) | |
773af77f | 34 | |
d43f81cb TB |
35 | struct drm_tegra_gem_create { |
36 | __u64 size; | |
37 | __u32 flags; | |
38 | __u32 handle; | |
39 | }; | |
40 | ||
41 | struct drm_tegra_gem_mmap { | |
42 | __u32 handle; | |
bdf76507 SP |
43 | __u32 pad; |
44 | __u64 offset; | |
d43f81cb TB |
45 | }; |
46 | ||
47 | struct drm_tegra_syncpt_read { | |
48 | __u32 id; | |
49 | __u32 value; | |
50 | }; | |
51 | ||
52 | struct drm_tegra_syncpt_incr { | |
53 | __u32 id; | |
54 | __u32 pad; | |
55 | }; | |
56 | ||
57 | struct drm_tegra_syncpt_wait { | |
58 | __u32 id; | |
59 | __u32 thresh; | |
60 | __u32 timeout; | |
61 | __u32 value; | |
62 | }; | |
63 | ||
64 | #define DRM_TEGRA_NO_TIMEOUT (0xffffffff) | |
65 | ||
66 | struct drm_tegra_open_channel { | |
67 | __u32 client; | |
68 | __u32 pad; | |
69 | __u64 context; | |
70 | }; | |
71 | ||
72 | struct drm_tegra_close_channel { | |
73 | __u64 context; | |
74 | }; | |
75 | ||
76 | struct drm_tegra_get_syncpt { | |
77 | __u64 context; | |
78 | __u32 index; | |
79 | __u32 id; | |
80 | }; | |
81 | ||
c54a169b AM |
82 | struct drm_tegra_get_syncpt_base { |
83 | __u64 context; | |
84 | __u32 syncpt; | |
85 | __u32 id; | |
86 | }; | |
87 | ||
d43f81cb TB |
88 | struct drm_tegra_syncpt { |
89 | __u32 id; | |
90 | __u32 incrs; | |
91 | }; | |
92 | ||
93 | struct drm_tegra_cmdbuf { | |
94 | __u32 handle; | |
95 | __u32 offset; | |
96 | __u32 words; | |
97 | __u32 pad; | |
98 | }; | |
99 | ||
100 | struct drm_tegra_reloc { | |
101 | struct { | |
102 | __u32 handle; | |
103 | __u32 offset; | |
104 | } cmdbuf; | |
105 | struct { | |
106 | __u32 handle; | |
107 | __u32 offset; | |
108 | } target; | |
109 | __u32 shift; | |
110 | __u32 pad; | |
111 | }; | |
112 | ||
113 | struct drm_tegra_waitchk { | |
114 | __u32 handle; | |
115 | __u32 offset; | |
116 | __u32 syncpt; | |
117 | __u32 thresh; | |
118 | }; | |
119 | ||
120 | struct drm_tegra_submit { | |
121 | __u64 context; | |
122 | __u32 num_syncpts; | |
123 | __u32 num_cmdbufs; | |
124 | __u32 num_relocs; | |
125 | __u32 num_waitchks; | |
126 | __u32 waitchk_mask; | |
127 | __u32 timeout; | |
d43f81cb TB |
128 | __u64 syncpts; |
129 | __u64 cmdbufs; | |
130 | __u64 relocs; | |
131 | __u64 waitchks; | |
132 | __u32 fence; /* Return value */ | |
133 | ||
134 | __u32 reserved[5]; /* future expansion */ | |
135 | }; | |
136 | ||
7678d71f TR |
137 | #define DRM_TEGRA_GEM_TILING_MODE_PITCH 0 |
138 | #define DRM_TEGRA_GEM_TILING_MODE_TILED 1 | |
139 | #define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2 | |
140 | ||
141 | struct drm_tegra_gem_set_tiling { | |
142 | /* input */ | |
143 | __u32 handle; | |
144 | __u32 mode; | |
145 | __u32 value; | |
146 | __u32 pad; | |
147 | }; | |
148 | ||
149 | struct drm_tegra_gem_get_tiling { | |
150 | /* input */ | |
151 | __u32 handle; | |
152 | /* output */ | |
153 | __u32 mode; | |
154 | __u32 value; | |
155 | __u32 pad; | |
156 | }; | |
157 | ||
7b129087 TR |
158 | #define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0) |
159 | #define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP) | |
160 | ||
161 | struct drm_tegra_gem_set_flags { | |
162 | /* input */ | |
163 | __u32 handle; | |
164 | /* output */ | |
165 | __u32 flags; | |
166 | }; | |
167 | ||
168 | struct drm_tegra_gem_get_flags { | |
169 | /* input */ | |
170 | __u32 handle; | |
171 | /* output */ | |
172 | __u32 flags; | |
173 | }; | |
174 | ||
c54a169b AM |
175 | #define DRM_TEGRA_GEM_CREATE 0x00 |
176 | #define DRM_TEGRA_GEM_MMAP 0x01 | |
177 | #define DRM_TEGRA_SYNCPT_READ 0x02 | |
178 | #define DRM_TEGRA_SYNCPT_INCR 0x03 | |
179 | #define DRM_TEGRA_SYNCPT_WAIT 0x04 | |
180 | #define DRM_TEGRA_OPEN_CHANNEL 0x05 | |
181 | #define DRM_TEGRA_CLOSE_CHANNEL 0x06 | |
182 | #define DRM_TEGRA_GET_SYNCPT 0x07 | |
183 | #define DRM_TEGRA_SUBMIT 0x08 | |
184 | #define DRM_TEGRA_GET_SYNCPT_BASE 0x09 | |
7678d71f TR |
185 | #define DRM_TEGRA_GEM_SET_TILING 0x0a |
186 | #define DRM_TEGRA_GEM_GET_TILING 0x0b | |
7b129087 TR |
187 | #define DRM_TEGRA_GEM_SET_FLAGS 0x0c |
188 | #define DRM_TEGRA_GEM_GET_FLAGS 0x0d | |
d43f81cb TB |
189 | |
190 | #define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create) | |
191 | #define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap) | |
192 | #define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read) | |
193 | #define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr) | |
194 | #define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait) | |
195 | #define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel) | |
196 | #define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel) | |
197 | #define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt) | |
198 | #define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit) | |
c54a169b | 199 | #define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base) |
7678d71f TR |
200 | #define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling) |
201 | #define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling) | |
7b129087 TR |
202 | #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags) |
203 | #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags) | |
d43f81cb | 204 | |
7aa8ceeb EV |
205 | #if defined(__cplusplus) |
206 | } | |
207 | #endif | |
208 | ||
d43f81cb | 209 | #endif |