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drm/tegra: Add support for tiled buffer objects
[mirror_ubuntu-bionic-kernel.git] / include / uapi / drm / tegra_drm.h
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1/*
2 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _UAPI_TEGRA_DRM_H_
18#define _UAPI_TEGRA_DRM_H_
19
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20#include <drm/drm.h>
21
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22#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
23
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24struct drm_tegra_gem_create {
25 __u64 size;
26 __u32 flags;
27 __u32 handle;
28};
29
30struct drm_tegra_gem_mmap {
31 __u32 handle;
32 __u32 offset;
33};
34
35struct drm_tegra_syncpt_read {
36 __u32 id;
37 __u32 value;
38};
39
40struct drm_tegra_syncpt_incr {
41 __u32 id;
42 __u32 pad;
43};
44
45struct drm_tegra_syncpt_wait {
46 __u32 id;
47 __u32 thresh;
48 __u32 timeout;
49 __u32 value;
50};
51
52#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
53
54struct drm_tegra_open_channel {
55 __u32 client;
56 __u32 pad;
57 __u64 context;
58};
59
60struct drm_tegra_close_channel {
61 __u64 context;
62};
63
64struct drm_tegra_get_syncpt {
65 __u64 context;
66 __u32 index;
67 __u32 id;
68};
69
70struct drm_tegra_syncpt {
71 __u32 id;
72 __u32 incrs;
73};
74
75struct drm_tegra_cmdbuf {
76 __u32 handle;
77 __u32 offset;
78 __u32 words;
79 __u32 pad;
80};
81
82struct drm_tegra_reloc {
83 struct {
84 __u32 handle;
85 __u32 offset;
86 } cmdbuf;
87 struct {
88 __u32 handle;
89 __u32 offset;
90 } target;
91 __u32 shift;
92 __u32 pad;
93};
94
95struct drm_tegra_waitchk {
96 __u32 handle;
97 __u32 offset;
98 __u32 syncpt;
99 __u32 thresh;
100};
101
102struct drm_tegra_submit {
103 __u64 context;
104 __u32 num_syncpts;
105 __u32 num_cmdbufs;
106 __u32 num_relocs;
107 __u32 num_waitchks;
108 __u32 waitchk_mask;
109 __u32 timeout;
110 __u32 pad;
111 __u64 syncpts;
112 __u64 cmdbufs;
113 __u64 relocs;
114 __u64 waitchks;
115 __u32 fence; /* Return value */
116
117 __u32 reserved[5]; /* future expansion */
118};
119
120#define DRM_TEGRA_GEM_CREATE 0x00
121#define DRM_TEGRA_GEM_MMAP 0x01
122#define DRM_TEGRA_SYNCPT_READ 0x02
123#define DRM_TEGRA_SYNCPT_INCR 0x03
124#define DRM_TEGRA_SYNCPT_WAIT 0x04
125#define DRM_TEGRA_OPEN_CHANNEL 0x05
126#define DRM_TEGRA_CLOSE_CHANNEL 0x06
127#define DRM_TEGRA_GET_SYNCPT 0x07
128#define DRM_TEGRA_SUBMIT 0x08
129
130#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
131#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
132#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
133#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
134#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
135#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
136#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
137#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
138#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
139
140#endif