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d5bc60f6 EA |
1 | /* |
2 | * Copyright © 2014-2015 Broadcom | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #ifndef _UAPI_VC4_DRM_H_ | |
25 | #define _UAPI_VC4_DRM_H_ | |
26 | ||
27 | #include "drm.h" | |
28 | ||
6a982350 EV |
29 | #if defined(__cplusplus) |
30 | extern "C" { | |
31 | #endif | |
32 | ||
d5b1a78a EA |
33 | #define DRM_VC4_SUBMIT_CL 0x00 |
34 | #define DRM_VC4_WAIT_SEQNO 0x01 | |
35 | #define DRM_VC4_WAIT_BO 0x02 | |
d5bc60f6 EA |
36 | #define DRM_VC4_CREATE_BO 0x03 |
37 | #define DRM_VC4_MMAP_BO 0x04 | |
463873d5 | 38 | #define DRM_VC4_CREATE_SHADER_BO 0x05 |
21461365 | 39 | #define DRM_VC4_GET_HANG_STATE 0x06 |
af713795 | 40 | #define DRM_VC4_GET_PARAM 0x07 |
83753117 EA |
41 | #define DRM_VC4_SET_TILING 0x08 |
42 | #define DRM_VC4_GET_TILING 0x09 | |
f3099462 | 43 | #define DRM_VC4_LABEL_BO 0x0a |
b9f19259 | 44 | #define DRM_VC4_GEM_MADVISE 0x0b |
d5bc60f6 | 45 | |
d5b1a78a EA |
46 | #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) |
47 | #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) | |
48 | #define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) | |
d5bc60f6 EA |
49 | #define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) |
50 | #define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) | |
463873d5 | 51 | #define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) |
21461365 | 52 | #define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) |
af713795 | 53 | #define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) |
83753117 EA |
54 | #define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling) |
55 | #define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) | |
f3099462 | 56 | #define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo) |
b9f19259 | 57 | #define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise) |
d5bc60f6 | 58 | |
d5b1a78a EA |
59 | struct drm_vc4_submit_rcl_surface { |
60 | __u32 hindex; /* Handle index, or ~0 if not present. */ | |
61 | __u32 offset; /* Offset to start of buffer. */ | |
62 | /* | |
63 | * Bits for either render config (color_write) or load/store packet. | |
64 | * Bits should all be 0 for MSAA load/stores. | |
65 | */ | |
66 | __u16 bits; | |
67 | ||
68 | #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) | |
69 | __u16 flags; | |
70 | }; | |
71 | ||
72 | /** | |
73 | * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D | |
74 | * engine. | |
75 | * | |
76 | * Drivers typically use GPU BOs to store batchbuffers / command lists and | |
77 | * their associated state. However, because the VC4 lacks an MMU, we have to | |
78 | * do validation of memory accesses by the GPU commands. If we were to store | |
79 | * our commands in BOs, we'd need to do uncached readback from them to do the | |
80 | * validation process, which is too expensive. Instead, userspace accumulates | |
81 | * commands and associated state in plain memory, then the kernel copies the | |
82 | * data to its own address space, and then validates and stores it in a GPU | |
83 | * BO. | |
84 | */ | |
85 | struct drm_vc4_submit_cl { | |
86 | /* Pointer to the binner command list. | |
87 | * | |
88 | * This is the first set of commands executed, which runs the | |
89 | * coordinate shader to determine where primitives land on the screen, | |
90 | * then writes out the state updates and draw calls necessary per tile | |
91 | * to the tile allocation BO. | |
92 | */ | |
93 | __u64 bin_cl; | |
94 | ||
95 | /* Pointer to the shader records. | |
96 | * | |
97 | * Shader records are the structures read by the hardware that contain | |
98 | * pointers to uniforms, shaders, and vertex attributes. The | |
99 | * reference to the shader record has enough information to determine | |
100 | * how many pointers are necessary (fixed number for shaders/uniforms, | |
101 | * and an attribute count), so those BO indices into bo_handles are | |
102 | * just stored as __u32s before each shader record passed in. | |
103 | */ | |
104 | __u64 shader_rec; | |
105 | ||
106 | /* Pointer to uniform data and texture handles for the textures | |
107 | * referenced by the shader. | |
108 | * | |
109 | * For each shader state record, there is a set of uniform data in the | |
110 | * order referenced by the record (FS, VS, then CS). Each set of | |
111 | * uniform data has a __u32 index into bo_handles per texture | |
112 | * sample operation, in the order the QPU_W_TMUn_S writes appear in | |
113 | * the program. Following the texture BO handle indices is the actual | |
114 | * uniform data. | |
115 | * | |
116 | * The individual uniform state blocks don't have sizes passed in, | |
117 | * because the kernel has to determine the sizes anyway during shader | |
118 | * code validation. | |
119 | */ | |
120 | __u64 uniforms; | |
121 | __u64 bo_handles; | |
122 | ||
123 | /* Size in bytes of the binner command list. */ | |
124 | __u32 bin_cl_size; | |
125 | /* Size in bytes of the set of shader records. */ | |
126 | __u32 shader_rec_size; | |
127 | /* Number of shader records. | |
128 | * | |
129 | * This could just be computed from the contents of shader_records and | |
130 | * the address bits of references to them from the bin CL, but it | |
131 | * keeps the kernel from having to resize some allocations it makes. | |
132 | */ | |
133 | __u32 shader_rec_count; | |
134 | /* Size in bytes of the uniform state. */ | |
135 | __u32 uniforms_size; | |
136 | ||
137 | /* Number of BO handles passed in (size is that times 4). */ | |
138 | __u32 bo_handle_count; | |
139 | ||
140 | /* RCL setup: */ | |
141 | __u16 width; | |
142 | __u16 height; | |
143 | __u8 min_x_tile; | |
144 | __u8 min_y_tile; | |
145 | __u8 max_x_tile; | |
146 | __u8 max_y_tile; | |
147 | struct drm_vc4_submit_rcl_surface color_read; | |
148 | struct drm_vc4_submit_rcl_surface color_write; | |
149 | struct drm_vc4_submit_rcl_surface zs_read; | |
150 | struct drm_vc4_submit_rcl_surface zs_write; | |
151 | struct drm_vc4_submit_rcl_surface msaa_color_write; | |
152 | struct drm_vc4_submit_rcl_surface msaa_zs_write; | |
153 | __u32 clear_color[2]; | |
154 | __u32 clear_z; | |
155 | __u8 clear_s; | |
156 | ||
157 | __u32 pad:24; | |
158 | ||
159 | #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) | |
3be8eddd EA |
160 | /* By default, the kernel gets to choose the order that the tiles are |
161 | * rendered in. If this is set, then the tiles will be rendered in a | |
162 | * raster order, with the right-to-left vs left-to-right and | |
163 | * top-to-bottom vs bottom-to-top dictated by | |
164 | * VC4_SUBMIT_CL_RCL_ORDER_INCREASING_*. This allows overlapping | |
165 | * blits to be implemented using the 3D engine. | |
166 | */ | |
167 | #define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1) | |
168 | #define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2) | |
169 | #define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3) | |
d5b1a78a EA |
170 | __u32 flags; |
171 | ||
172 | /* Returned value of the seqno of this render job (for the | |
173 | * wait ioctl). | |
174 | */ | |
175 | __u64 seqno; | |
176 | }; | |
177 | ||
178 | /** | |
179 | * struct drm_vc4_wait_seqno - ioctl argument for waiting for | |
180 | * DRM_VC4_SUBMIT_CL completion using its returned seqno. | |
181 | * | |
182 | * timeout_ns is the timeout in nanoseconds, where "0" means "don't | |
183 | * block, just return the status." | |
184 | */ | |
185 | struct drm_vc4_wait_seqno { | |
186 | __u64 seqno; | |
187 | __u64 timeout_ns; | |
188 | }; | |
189 | ||
190 | /** | |
191 | * struct drm_vc4_wait_bo - ioctl argument for waiting for | |
192 | * completion of the last DRM_VC4_SUBMIT_CL on a BO. | |
193 | * | |
194 | * This is useful for cases where multiple processes might be | |
195 | * rendering to a BO and you want to wait for all rendering to be | |
196 | * completed. | |
197 | */ | |
198 | struct drm_vc4_wait_bo { | |
199 | __u32 handle; | |
200 | __u32 pad; | |
201 | __u64 timeout_ns; | |
202 | }; | |
203 | ||
d5bc60f6 EA |
204 | /** |
205 | * struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs. | |
206 | * | |
207 | * There are currently no values for the flags argument, but it may be | |
208 | * used in a future extension. | |
209 | */ | |
210 | struct drm_vc4_create_bo { | |
211 | __u32 size; | |
212 | __u32 flags; | |
213 | /** Returned GEM handle for the BO. */ | |
214 | __u32 handle; | |
215 | __u32 pad; | |
216 | }; | |
217 | ||
218 | /** | |
219 | * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs. | |
220 | * | |
221 | * This doesn't actually perform an mmap. Instead, it returns the | |
222 | * offset you need to use in an mmap on the DRM device node. This | |
223 | * means that tools like valgrind end up knowing about the mapped | |
224 | * memory. | |
225 | * | |
226 | * There are currently no values for the flags argument, but it may be | |
227 | * used in a future extension. | |
228 | */ | |
229 | struct drm_vc4_mmap_bo { | |
230 | /** Handle for the object being mapped. */ | |
231 | __u32 handle; | |
232 | __u32 flags; | |
233 | /** offset into the drm node to use for subsequent mmap call. */ | |
234 | __u64 offset; | |
235 | }; | |
236 | ||
463873d5 EA |
237 | /** |
238 | * struct drm_vc4_create_shader_bo - ioctl argument for creating VC4 | |
239 | * shader BOs. | |
240 | * | |
241 | * Since allowing a shader to be overwritten while it's also being | |
242 | * executed from would allow privlege escalation, shaders must be | |
243 | * created using this ioctl, and they can't be mmapped later. | |
244 | */ | |
245 | struct drm_vc4_create_shader_bo { | |
246 | /* Size of the data argument. */ | |
247 | __u32 size; | |
248 | /* Flags, currently must be 0. */ | |
249 | __u32 flags; | |
250 | ||
251 | /* Pointer to the data. */ | |
252 | __u64 data; | |
253 | ||
254 | /** Returned GEM handle for the BO. */ | |
255 | __u32 handle; | |
256 | /* Pad, must be 0. */ | |
257 | __u32 pad; | |
258 | }; | |
259 | ||
21461365 EA |
260 | struct drm_vc4_get_hang_state_bo { |
261 | __u32 handle; | |
262 | __u32 paddr; | |
263 | __u32 size; | |
264 | __u32 pad; | |
265 | }; | |
266 | ||
267 | /** | |
268 | * struct drm_vc4_hang_state - ioctl argument for collecting state | |
269 | * from a GPU hang for analysis. | |
270 | */ | |
271 | struct drm_vc4_get_hang_state { | |
272 | /** Pointer to array of struct drm_vc4_get_hang_state_bo. */ | |
273 | __u64 bo; | |
274 | /** | |
275 | * On input, the size of the bo array. Output is the number | |
276 | * of bos to be returned. | |
277 | */ | |
278 | __u32 bo_count; | |
279 | ||
280 | __u32 start_bin, start_render; | |
281 | ||
282 | __u32 ct0ca, ct0ea; | |
283 | __u32 ct1ca, ct1ea; | |
284 | __u32 ct0cs, ct1cs; | |
285 | __u32 ct0ra0, ct1ra0; | |
286 | ||
287 | __u32 bpca, bpcs; | |
288 | __u32 bpoa, bpos; | |
289 | ||
290 | __u32 vpmbase; | |
291 | ||
292 | __u32 dbge; | |
293 | __u32 fdbgo; | |
294 | __u32 fdbgb; | |
295 | __u32 fdbgr; | |
296 | __u32 fdbgs; | |
297 | __u32 errstat; | |
298 | ||
299 | /* Pad that we may save more registers into in the future. */ | |
300 | __u32 pad[16]; | |
301 | }; | |
302 | ||
af713795 EA |
303 | #define DRM_VC4_PARAM_V3D_IDENT0 0 |
304 | #define DRM_VC4_PARAM_V3D_IDENT1 1 | |
305 | #define DRM_VC4_PARAM_V3D_IDENT2 2 | |
7363cee5 | 306 | #define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3 |
7154d76f | 307 | #define DRM_VC4_PARAM_SUPPORTS_ETC1 4 |
c778cc5d | 308 | #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 |
3be8eddd | 309 | #define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6 |
b9f19259 | 310 | #define DRM_VC4_PARAM_SUPPORTS_MADVISE 7 |
af713795 EA |
311 | |
312 | struct drm_vc4_get_param { | |
313 | __u32 param; | |
314 | __u32 pad; | |
315 | __u64 value; | |
316 | }; | |
317 | ||
83753117 EA |
318 | struct drm_vc4_get_tiling { |
319 | __u32 handle; | |
320 | __u32 flags; | |
321 | __u64 modifier; | |
322 | }; | |
323 | ||
324 | struct drm_vc4_set_tiling { | |
325 | __u32 handle; | |
326 | __u32 flags; | |
327 | __u64 modifier; | |
328 | }; | |
329 | ||
f3099462 EA |
330 | /** |
331 | * struct drm_vc4_label_bo - Attach a name to a BO for debug purposes. | |
332 | */ | |
333 | struct drm_vc4_label_bo { | |
334 | __u32 handle; | |
335 | __u32 len; | |
336 | __u64 name; | |
337 | }; | |
338 | ||
b9f19259 BB |
339 | /* |
340 | * States prefixed with '__' are internal states and cannot be passed to the | |
341 | * DRM_IOCTL_VC4_GEM_MADVISE ioctl. | |
342 | */ | |
343 | #define VC4_MADV_WILLNEED 0 | |
344 | #define VC4_MADV_DONTNEED 1 | |
345 | #define __VC4_MADV_PURGED 2 | |
346 | #define __VC4_MADV_NOTSUPP 3 | |
347 | ||
348 | struct drm_vc4_gem_madvise { | |
349 | __u32 handle; | |
350 | __u32 madv; | |
351 | __u32 retained; | |
352 | __u32 pad; | |
353 | }; | |
354 | ||
6a982350 EV |
355 | #if defined(__cplusplus) |
356 | } | |
357 | #endif | |
358 | ||
d5bc60f6 | 359 | #endif /* _UAPI_VC4_DRM_H_ */ |