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62fb7a5e GH |
1 | /* |
2 | * Copyright 2013 Red Hat | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | #ifndef VIRTGPU_DRM_H | |
25 | #define VIRTGPU_DRM_H | |
26 | ||
6e82e9c8 | 27 | #include "drm.h" |
62fb7a5e | 28 | |
38180815 EV |
29 | #if defined(__cplusplus) |
30 | extern "C" { | |
31 | #endif | |
32 | ||
62fb7a5e GH |
33 | /* Please note that modifications to all structs defined here are |
34 | * subject to backwards-compatibility constraints. | |
35 | * | |
29e08b05 | 36 | * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel |
62fb7a5e GH |
37 | * compatibility Keep fields aligned to their size |
38 | */ | |
39 | ||
40 | #define DRM_VIRTGPU_MAP 0x01 | |
41 | #define DRM_VIRTGPU_EXECBUFFER 0x02 | |
42 | #define DRM_VIRTGPU_GETPARAM 0x03 | |
43 | #define DRM_VIRTGPU_RESOURCE_CREATE 0x04 | |
44 | #define DRM_VIRTGPU_RESOURCE_INFO 0x05 | |
45 | #define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06 | |
46 | #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07 | |
47 | #define DRM_VIRTGPU_WAIT 0x08 | |
48 | #define DRM_VIRTGPU_GET_CAPS 0x09 | |
49 | ||
50 | struct drm_virtgpu_map { | |
29e08b05 GL |
51 | __u64 offset; /* use for mmap system call */ |
52 | __u32 handle; | |
53 | __u32 pad; | |
62fb7a5e GH |
54 | }; |
55 | ||
56 | struct drm_virtgpu_execbuffer { | |
29e08b05 GL |
57 | __u32 flags; /* for future use */ |
58 | __u32 size; | |
59 | __u64 command; /* void* */ | |
60 | __u64 bo_handles; | |
61 | __u32 num_bo_handles; | |
62 | __u32 pad; | |
62fb7a5e GH |
63 | }; |
64 | ||
65 | #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */ | |
66 | ||
67 | struct drm_virtgpu_getparam { | |
29e08b05 GL |
68 | __u64 param; |
69 | __u64 value; | |
62fb7a5e GH |
70 | }; |
71 | ||
72 | /* NO_BO flags? NO resource flag? */ | |
73 | /* resource flag for y_0_top */ | |
74 | struct drm_virtgpu_resource_create { | |
29e08b05 GL |
75 | __u32 target; |
76 | __u32 format; | |
77 | __u32 bind; | |
78 | __u32 width; | |
79 | __u32 height; | |
80 | __u32 depth; | |
81 | __u32 array_size; | |
82 | __u32 last_level; | |
83 | __u32 nr_samples; | |
84 | __u32 flags; | |
85 | __u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */ | |
86 | __u32 res_handle; /* returned by kernel */ | |
87 | __u32 size; /* validate transfer in the host */ | |
88 | __u32 stride; /* validate transfer in the host */ | |
62fb7a5e GH |
89 | }; |
90 | ||
91 | struct drm_virtgpu_resource_info { | |
29e08b05 GL |
92 | __u32 bo_handle; |
93 | __u32 res_handle; | |
94 | __u32 size; | |
95 | __u32 stride; | |
62fb7a5e GH |
96 | }; |
97 | ||
98 | struct drm_virtgpu_3d_box { | |
29e08b05 GL |
99 | __u32 x; |
100 | __u32 y; | |
101 | __u32 z; | |
102 | __u32 w; | |
103 | __u32 h; | |
104 | __u32 d; | |
62fb7a5e GH |
105 | }; |
106 | ||
107 | struct drm_virtgpu_3d_transfer_to_host { | |
29e08b05 | 108 | __u32 bo_handle; |
62fb7a5e | 109 | struct drm_virtgpu_3d_box box; |
29e08b05 GL |
110 | __u32 level; |
111 | __u32 offset; | |
62fb7a5e GH |
112 | }; |
113 | ||
114 | struct drm_virtgpu_3d_transfer_from_host { | |
29e08b05 | 115 | __u32 bo_handle; |
62fb7a5e | 116 | struct drm_virtgpu_3d_box box; |
29e08b05 GL |
117 | __u32 level; |
118 | __u32 offset; | |
62fb7a5e GH |
119 | }; |
120 | ||
121 | #define VIRTGPU_WAIT_NOWAIT 1 /* like it */ | |
122 | struct drm_virtgpu_3d_wait { | |
29e08b05 GL |
123 | __u32 handle; /* 0 is an invalid handle */ |
124 | __u32 flags; | |
62fb7a5e GH |
125 | }; |
126 | ||
127 | struct drm_virtgpu_get_caps { | |
29e08b05 GL |
128 | __u32 cap_set_id; |
129 | __u32 cap_set_ver; | |
130 | __u64 addr; | |
131 | __u32 size; | |
132 | __u32 pad; | |
62fb7a5e GH |
133 | }; |
134 | ||
135 | #define DRM_IOCTL_VIRTGPU_MAP \ | |
136 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map) | |
137 | ||
138 | #define DRM_IOCTL_VIRTGPU_EXECBUFFER \ | |
139 | DRM_IOW(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\ | |
140 | struct drm_virtgpu_execbuffer) | |
141 | ||
142 | #define DRM_IOCTL_VIRTGPU_GETPARAM \ | |
143 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\ | |
144 | struct drm_virtgpu_getparam) | |
145 | ||
146 | #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \ | |
147 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \ | |
148 | struct drm_virtgpu_resource_create) | |
149 | ||
150 | #define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \ | |
151 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \ | |
152 | struct drm_virtgpu_resource_info) | |
153 | ||
154 | #define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \ | |
155 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \ | |
156 | struct drm_virtgpu_3d_transfer_from_host) | |
157 | ||
158 | #define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \ | |
159 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \ | |
160 | struct drm_virtgpu_3d_transfer_to_host) | |
161 | ||
162 | #define DRM_IOCTL_VIRTGPU_WAIT \ | |
163 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \ | |
164 | struct drm_virtgpu_3d_wait) | |
165 | ||
166 | #define DRM_IOCTL_VIRTGPU_GET_CAPS \ | |
167 | DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \ | |
168 | struct drm_virtgpu_get_caps) | |
169 | ||
38180815 EV |
170 | #if defined(__cplusplus) |
171 | } | |
172 | #endif | |
173 | ||
62fb7a5e | 174 | #endif |