[mirror_ubuntu-zesty-kernel.git] / include / uapi / linux / ndctl.h

/*
 * Copyright (c) 2014-2015, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU Lesser General Public License,
 * version 2.1, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT ANY
 * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
 * FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public License for
 * more details.
 */
#ifndef __NDCTL_H__
#define __NDCTL_H__

#include <linux/types.h>

struct nd_cmd_smart {
	__u32 status;
	__u8 data[128];
} __packed;

struct nd_cmd_smart_threshold {
	__u32 status;
	__u8 data[8];
} __packed;

struct nd_cmd_dimm_flags {
	__u32 status;
	__u32 flags;
} __packed;

struct nd_cmd_get_config_size {
	__u32 status;
	__u32 config_size;
	__u32 max_xfer;
} __packed;

struct nd_cmd_get_config_data_hdr {
	__u32 in_offset;
	__u32 in_length;
	__u32 status;
	__u8 out_buf[0];
} __packed;

struct nd_cmd_set_config_hdr {
	__u32 in_offset;
	__u32 in_length;
	__u8 in_buf[0];
} __packed;

struct nd_cmd_vendor_hdr {
	__u32 opcode;
	__u32 in_length;
	__u8 in_buf[0];
} __packed;

struct nd_cmd_vendor_tail {
	__u32 status;
	__u32 out_length;
	__u8 out_buf[0];
} __packed;

struct nd_cmd_ars_cap {
	__u64 address;
	__u64 length;
	__u32 status;
	__u32 max_ars_out;
} __packed;

struct nd_cmd_ars_start {
	__u64 address;
	__u64 length;
	__u16 type;
	__u8 reserved[6];
	__u32 status;
} __packed;

struct nd_cmd_ars_status {
	__u32 status;
	__u32 out_length;
	__u64 address;
	__u64 length;
	__u16 type;
	__u32 num_records;
	struct nd_ars_record {
		__u32 handle;
		__u32 flags;
		__u64 err_address;
		__u64 mask;
	} __packed records[0];
} __packed;

enum {
	ND_CMD_IMPLEMENTED = 0,

	/* bus commands */
	ND_CMD_ARS_CAP = 1,
	ND_CMD_ARS_START = 2,
	ND_CMD_ARS_STATUS = 3,

	/* per-dimm commands */
	ND_CMD_SMART = 1,
	ND_CMD_SMART_THRESHOLD = 2,
	ND_CMD_DIMM_FLAGS = 3,
	ND_CMD_GET_CONFIG_SIZE = 4,
	ND_CMD_GET_CONFIG_DATA = 5,
	ND_CMD_SET_CONFIG_DATA = 6,
	ND_CMD_VENDOR_EFFECT_LOG_SIZE = 7,
	ND_CMD_VENDOR_EFFECT_LOG = 8,
	ND_CMD_VENDOR = 9,
};

static inline const char *nvdimm_bus_cmd_name(unsigned cmd)
{
	static const char * const names[] = {
		[ND_CMD_ARS_CAP] = "ars_cap",
		[ND_CMD_ARS_START] = "ars_start",
		[ND_CMD_ARS_STATUS] = "ars_status",
	};

	if (cmd < ARRAY_SIZE(names) && names[cmd])
		return names[cmd];
	return "unknown";
}

static inline const char *nvdimm_cmd_name(unsigned cmd)
{
	static const char * const names[] = {
		[ND_CMD_SMART] = "smart",
		[ND_CMD_SMART_THRESHOLD] = "smart_thresh",
		[ND_CMD_DIMM_FLAGS] = "flags",
		[ND_CMD_GET_CONFIG_SIZE] = "get_size",
		[ND_CMD_GET_CONFIG_DATA] = "get_data",
		[ND_CMD_SET_CONFIG_DATA] = "set_data",
		[ND_CMD_VENDOR_EFFECT_LOG_SIZE] = "effect_size",
		[ND_CMD_VENDOR_EFFECT_LOG] = "effect_log",
		[ND_CMD_VENDOR] = "vendor",
	};

	if (cmd < ARRAY_SIZE(names) && names[cmd])
		return names[cmd];
	return "unknown";
}

#define ND_IOCTL 'N'

#define ND_IOCTL_SMART			_IOWR(ND_IOCTL, ND_CMD_SMART,\
					struct nd_cmd_smart)

#define ND_IOCTL_SMART_THRESHOLD	_IOWR(ND_IOCTL, ND_CMD_SMART_THRESHOLD,\
					struct nd_cmd_smart_threshold)

#define ND_IOCTL_DIMM_FLAGS		_IOWR(ND_IOCTL, ND_CMD_DIMM_FLAGS,\
					struct nd_cmd_dimm_flags)

#define ND_IOCTL_GET_CONFIG_SIZE	_IOWR(ND_IOCTL, ND_CMD_GET_CONFIG_SIZE,\
					struct nd_cmd_get_config_size)

#define ND_IOCTL_GET_CONFIG_DATA	_IOWR(ND_IOCTL, ND_CMD_GET_CONFIG_DATA,\
					struct nd_cmd_get_config_data_hdr)

#define ND_IOCTL_SET_CONFIG_DATA	_IOWR(ND_IOCTL, ND_CMD_SET_CONFIG_DATA,\
					struct nd_cmd_set_config_hdr)

#define ND_IOCTL_VENDOR			_IOWR(ND_IOCTL, ND_CMD_VENDOR,\
					struct nd_cmd_vendor_hdr)

#define ND_IOCTL_ARS_CAP		_IOWR(ND_IOCTL, ND_CMD_ARS_CAP,\
					struct nd_cmd_ars_cap)

#define ND_IOCTL_ARS_START		_IOWR(ND_IOCTL, ND_CMD_ARS_START,\
					struct nd_cmd_ars_start)

#define ND_IOCTL_ARS_STATUS		_IOWR(ND_IOCTL, ND_CMD_ARS_STATUS,\
					struct nd_cmd_ars_status)

#define ND_DEVICE_DIMM 1            /* nd_dimm: container for "config data" */
#define ND_DEVICE_REGION_PMEM 2     /* nd_region: (parent of PMEM namespaces) */
#define ND_DEVICE_REGION_BLK 3      /* nd_region: (parent of BLK namespaces) */
#define ND_DEVICE_NAMESPACE_IO 4    /* legacy persistent memory */
#define ND_DEVICE_NAMESPACE_PMEM 5  /* PMEM namespace (may alias with BLK) */
#define ND_DEVICE_NAMESPACE_BLK 6   /* BLK namespace (may alias with PMEM) */

enum nd_driver_flags {
	ND_DRIVER_DIMM            = 1 << ND_DEVICE_DIMM,
	ND_DRIVER_REGION_PMEM     = 1 << ND_DEVICE_REGION_PMEM,
	ND_DRIVER_REGION_BLK      = 1 << ND_DEVICE_REGION_BLK,
	ND_DRIVER_NAMESPACE_IO    = 1 << ND_DEVICE_NAMESPACE_IO,
	ND_DRIVER_NAMESPACE_PMEM  = 1 << ND_DEVICE_NAMESPACE_PMEM,
	ND_DRIVER_NAMESPACE_BLK   = 1 << ND_DEVICE_NAMESPACE_BLK,
};
#endif /* __NDCTL_H__ */
Commit	Line	Data
62232e45 DW	1	/*
	2	* Copyright (c) 2014-2015, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU Lesser General Public License,
	6	* version 2.1, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT ANY
	9	* WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
	10	* FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for
	11	* more details.
	12	*/
	13	#ifndef __NDCTL_H__
	14	#define __NDCTL_H__
	15
	16	#include <linux/types.h>
	17
	18	struct nd_cmd_smart {
	19	__u32 status;
	20	__u8 data[128];
	21	} __packed;
	22
	23	struct nd_cmd_smart_threshold {
	24	__u32 status;
	25	__u8 data[8];
	26	} __packed;
	27
	28	struct nd_cmd_dimm_flags {
	29	__u32 status;
	30	__u32 flags;
	31	} __packed;
	32
	33	struct nd_cmd_get_config_size {
	34	__u32 status;
	35	__u32 config_size;
	36	__u32 max_xfer;
	37	} __packed;
	38
	39	struct nd_cmd_get_config_data_hdr {
	40	__u32 in_offset;
	41	__u32 in_length;
	42	__u32 status;
	43	__u8 out_buf[0];
	44	} __packed;
	45
	46	struct nd_cmd_set_config_hdr {
	47	__u32 in_offset;
	48	__u32 in_length;
	49	__u8 in_buf[0];
	50	} __packed;
	51
	52	struct nd_cmd_vendor_hdr {
	53	__u32 opcode;
	54	__u32 in_length;
	55	__u8 in_buf[0];
	56	} __packed;
	57
	58	struct nd_cmd_vendor_tail {
	59	__u32 status;
	60	__u32 out_length;
	61	__u8 out_buf[0];
	62	} __packed;
	63
	64	struct nd_cmd_ars_cap {
65	__u64 address;
66	__u64 length;
67	__u32 status;
68	__u32 max_ars_out;
69	} __packed;
70
71	struct nd_cmd_ars_start {
72	__u64 address;
73	__u64 length;
74	__u16 type;
75	__u8 reserved[6];
76	__u32 status;
77	} __packed;
78
79	struct nd_cmd_ars_status {
80	__u32 status;
81	__u32 out_length;
82	__u64 address;
83	__u64 length;
84	__u16 type;
85	__u32 num_records;
86	struct nd_ars_record {
87	__u32 handle;
88	__u32 flags;
89	__u64 err_address;
90	__u64 mask;
91	} __packed records[0];
92	} __packed;
93
94	enum {
95	ND_CMD_IMPLEMENTED = 0,
96
97	/* bus commands */
98	ND_CMD_ARS_CAP = 1,
99	ND_CMD_ARS_START = 2,
100	ND_CMD_ARS_STATUS = 3,
101
102	/* per-dimm commands */
103	ND_CMD_SMART = 1,
104	ND_CMD_SMART_THRESHOLD = 2,
105	ND_CMD_DIMM_FLAGS = 3,
106	ND_CMD_GET_CONFIG_SIZE = 4,
107	ND_CMD_GET_CONFIG_DATA = 5,
108	ND_CMD_SET_CONFIG_DATA = 6,
109	ND_CMD_VENDOR_EFFECT_LOG_SIZE = 7,
110	ND_CMD_VENDOR_EFFECT_LOG = 8,
111	ND_CMD_VENDOR = 9,
112	};
113
114	static inline const char *nvdimm_bus_cmd_name(unsigned cmd)
115	{
116	static const char * const names[] = {
117	[ND_CMD_ARS_CAP] = "ars_cap",
118	[ND_CMD_ARS_START] = "ars_start",
119	[ND_CMD_ARS_STATUS] = "ars_status",
120	};
121
122	if (cmd < ARRAY_SIZE(names) && names[cmd])
123	return names[cmd];
124	return "unknown";
125	}
126
127	static inline const char *nvdimm_cmd_name(unsigned cmd)
128	{
129	static const char * const names[] = {
130	[ND_CMD_SMART] = "smart",
131	[ND_CMD_SMART_THRESHOLD] = "smart_thresh",
132	[ND_CMD_DIMM_FLAGS] = "flags",
133	[ND_CMD_GET_CONFIG_SIZE] = "get_size",
134	[ND_CMD_GET_CONFIG_DATA] = "get_data",
135	[ND_CMD_SET_CONFIG_DATA] = "set_data",
136	[ND_CMD_VENDOR_EFFECT_LOG_SIZE] = "effect_size",
137	[ND_CMD_VENDOR_EFFECT_LOG] = "effect_log",
138	[ND_CMD_VENDOR] = "vendor",
139	};
140
141	if (cmd < ARRAY_SIZE(names) && names[cmd])
142	return names[cmd];
143	return "unknown";
144	}
145
146	#define ND_IOCTL 'N'
147
148	#define ND_IOCTL_SMART _IOWR(ND_IOCTL, ND_CMD_SMART,\
149	struct nd_cmd_smart)
150
151	#define ND_IOCTL_SMART_THRESHOLD _IOWR(ND_IOCTL, ND_CMD_SMART_THRESHOLD,\
152	struct nd_cmd_smart_threshold)
153
154	#define ND_IOCTL_DIMM_FLAGS _IOWR(ND_IOCTL, ND_CMD_DIMM_FLAGS,\
155	struct nd_cmd_dimm_flags)
156
157	#define ND_IOCTL_GET_CONFIG_SIZE _IOWR(ND_IOCTL, ND_CMD_GET_CONFIG_SIZE,\
158	struct nd_cmd_get_config_size)
159
160	#define ND_IOCTL_GET_CONFIG_DATA _IOWR(ND_IOCTL, ND_CMD_GET_CONFIG_DATA,\
161	struct nd_cmd_get_config_data_hdr)
162
163	#define ND_IOCTL_SET_CONFIG_DATA _IOWR(ND_IOCTL, ND_CMD_SET_CONFIG_DATA,\
164	struct nd_cmd_set_config_hdr)
165
166	#define ND_IOCTL_VENDOR _IOWR(ND_IOCTL, ND_CMD_VENDOR,\
167	struct nd_cmd_vendor_hdr)
168
169	#define ND_IOCTL_ARS_CAP _IOWR(ND_IOCTL, ND_CMD_ARS_CAP,\
170	struct nd_cmd_ars_cap)
171
172	#define ND_IOCTL_ARS_START _IOWR(ND_IOCTL, ND_CMD_ARS_START,\
173	struct nd_cmd_ars_start)
174
175	#define ND_IOCTL_ARS_STATUS _IOWR(ND_IOCTL, ND_CMD_ARS_STATUS,\
176	struct nd_cmd_ars_status)
177
4d88a97a	178	#define ND_DEVICE_DIMM 1 /* nd_dimm: container for "config data" */
3d88002e DW	179	#define ND_DEVICE_REGION_PMEM 2 /* nd_region: (parent of PMEM namespaces) */
	180	#define ND_DEVICE_REGION_BLK 3 /* nd_region: (parent of BLK namespaces) */
	181	#define ND_DEVICE_NAMESPACE_IO 4 /* legacy persistent memory */
	182	#define ND_DEVICE_NAMESPACE_PMEM 5 /* PMEM namespace (may alias with BLK) */
	183	#define ND_DEVICE_NAMESPACE_BLK 6 /* BLK namespace (may alias with PMEM) */
4d88a97a DW	184
	185	enum nd_driver_flags {
	186	ND_DRIVER_DIMM = 1 << ND_DEVICE_DIMM,
3d88002e DW	187	ND_DRIVER_REGION_PMEM = 1 << ND_DEVICE_REGION_PMEM,
	188	ND_DRIVER_REGION_BLK = 1 << ND_DEVICE_REGION_BLK,
	189	ND_DRIVER_NAMESPACE_IO = 1 << ND_DEVICE_NAMESPACE_IO,
	190	ND_DRIVER_NAMESPACE_PMEM = 1 << ND_DEVICE_NAMESPACE_PMEM,
	191	ND_DRIVER_NAMESPACE_BLK = 1 << ND_DEVICE_NAMESPACE_BLK,
4d88a97a	192	};
62232e45	193	#endif /* __NDCTL_H__ */