projects / mirror_ubuntu-kernels.git / blame
| Commit | Line | Data |
|---|---|---|
| 6f52b16c | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 4352dfd5 GKH |
2 | /* |
| 3 | * pci_regs.h | |
| 4 | * | |
| 5 | * PCI standard defines | |
| 6 | * Copyright 1994, Drew Eckhardt | |
| 7 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> | |
| 8 | * | |
| 9 | * For more information, please consult the following manuals (look at | |
| 10 | * http://www.pcisig.com/ for how to get them): | |
| 11 | * | |
| 12 | * PCI BIOS Specification | |
| 13 | * PCI Local Bus Specification | |
| 14 | * PCI to PCI Bridge Specification | |
| 15 | * PCI System Design Guide | |
| e78d0169 | 16 | * |
| f7625980 BH |
17 | * For HyperTransport information, please consult the following manuals |
| 18 | * from http://www.hypertransport.org | |
| e78d0169 | 19 | * |
| f7625980 | 20 | * The HyperTransport I/O Link Specification |
| 4352dfd5 GKH |
21 | */ |
| 22 | ||
| 23 | #ifndef LINUX_PCI_REGS_H | |
| 24 | #define LINUX_PCI_REGS_H | |
| 25 | ||
| cc10385b WSH |
26 | /* |
| 27 | * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of | |
| 28 | * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of | |
| 29 | * configuration space. | |
| 30 | */ | |
| 31 | #define PCI_CFG_SPACE_SIZE 256 | |
| 32 | #define PCI_CFG_SPACE_EXP_SIZE 4096 | |
| 33 | ||
| 4352dfd5 GKH |
34 | /* |
| 35 | * Under PCI, each device has 256 bytes of configuration address space, | |
| 36 | * of which the first 64 bytes are standardized as follows: | |
| 37 | */ | |
| a0dee2ed | 38 | #define PCI_STD_HEADER_SIZEOF 64 |
| 4352dfd5 GKH |
39 | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
| 40 | #define PCI_DEVICE_ID 0x02 /* 16 bits */ | |
| 41 | #define PCI_COMMAND 0x04 /* 16 bits */ | |
| 42 | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ | |
| 43 | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ | |
| 44 | #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ | |
| 45 | #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ | |
| 46 | #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ | |
| 47 | #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ | |
| 48 | #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ | |
| f7625980 | 49 | #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ |
| 4352dfd5 GKH |
50 | #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ |
| 51 | #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ | |
| 52 | #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ | |
| 53 | ||
| 54 | #define PCI_STATUS 0x06 /* 16 bits */ | |
| d6112f8d | 55 | #define PCI_STATUS_IMM_READY 0x01 /* Immediate Readiness */ |
| ccb86a69 | 56 | #define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */ |
| 4352dfd5 | 57 | #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ |
| f7625980 | 58 | #define PCI_STATUS_66MHZ 0x20 /* Support 66 MHz PCI 2.1 bus */ |
| 4352dfd5 GKH |
59 | #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ |
| 60 | #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ | |
| 61 | #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ | |
| 62 | #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ | |
| 63 | #define PCI_STATUS_DEVSEL_FAST 0x000 | |
| 64 | #define PCI_STATUS_DEVSEL_MEDIUM 0x200 | |
| 65 | #define PCI_STATUS_DEVSEL_SLOW 0x400 | |
| 66 | #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ | |
| 67 | #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ | |
| 68 | #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ | |
| 69 | #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ | |
| 70 | #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ | |
| 71 | ||
| 72 | #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ | |
| 73 | #define PCI_REVISION_ID 0x08 /* Revision ID */ | |
| 74 | #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ | |
| 75 | #define PCI_CLASS_DEVICE 0x0a /* Device class */ | |
| 76 | ||
| 77 | #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ | |
| 78 | #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ | |
| 79 | #define PCI_HEADER_TYPE 0x0e /* 8 bits */ | |
| 80 | #define PCI_HEADER_TYPE_NORMAL 0 | |
| 81 | #define PCI_HEADER_TYPE_BRIDGE 1 | |
| 82 | #define PCI_HEADER_TYPE_CARDBUS 2 | |
| 83 | ||
| 84 | #define PCI_BIST 0x0f /* 8 bits */ | |
| 85 | #define PCI_BIST_CODE_MASK 0x0f /* Return result */ | |
| 86 | #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ | |
| 87 | #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ | |
| 88 | ||
| 89 | /* | |
| 90 | * Base addresses specify locations in memory or I/O space. | |
| 91 | * Decoded size can be determined by writing a value of | |
| 92 | * 0xffffffff to the register, and reading it back. Only | |
| 93 | * 1 bits are decoded. | |
| 94 | */ | |
| 95 | #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ | |
| 96 | #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ | |
| 97 | #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ | |
| 98 | #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ | |
| 99 | #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ | |
| 100 | #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ | |
| 101 | #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ | |
| 102 | #define PCI_BASE_ADDRESS_SPACE_IO 0x01 | |
| 103 | #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 | |
| 104 | #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 | |
| 105 | #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ | |
| 106 | #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ | |
| 107 | #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ | |
| 108 | #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ | |
| 109 | #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) | |
| 110 | #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) | |
| 111 | /* bit 1 is reserved if address_space = 1 */ | |
| 112 | ||
| 113 | /* Header type 0 (normal devices) */ | |
| 114 | #define PCI_CARDBUS_CIS 0x28 | |
| 115 | #define PCI_SUBSYSTEM_VENDOR_ID 0x2c | |
| 116 | #define PCI_SUBSYSTEM_ID 0x2e | |
| 117 | #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ | |
| 118 | #define PCI_ROM_ADDRESS_ENABLE 0x01 | |
| 76dc5268 | 119 | #define PCI_ROM_ADDRESS_MASK (~0x7ffU) |
| 4352dfd5 GKH |
120 | |
| 121 | #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ | |
| 122 | ||
| 123 | /* 0x35-0x3b are reserved */ | |
| 124 | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ | |
| 125 | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ | |
| 126 | #define PCI_MIN_GNT 0x3e /* 8 bits */ | |
| 127 | #define PCI_MAX_LAT 0x3f /* 8 bits */ | |
| 128 | ||
| 129 | /* Header type 1 (PCI-to-PCI bridges) */ | |
| 130 | #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ | |
| 131 | #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ | |
| 132 | #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ | |
| 133 | #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ | |
| 134 | #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ | |
| 135 | #define PCI_IO_LIMIT 0x1d | |
| 136 | #define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */ | |
| 137 | #define PCI_IO_RANGE_TYPE_16 0x00 | |
| 138 | #define PCI_IO_RANGE_TYPE_32 0x01 | |
| 2b28ae19 BH |
139 | #define PCI_IO_RANGE_MASK (~0x0fUL) /* Standard 4K I/O windows */ |
| 140 | #define PCI_IO_1K_RANGE_MASK (~0x03UL) /* Intel 1K I/O windows */ | |
| 4352dfd5 GKH |
141 | #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ |
| 142 | #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ | |
| 143 | #define PCI_MEMORY_LIMIT 0x22 | |
| 144 | #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL | |
| 145 | #define PCI_MEMORY_RANGE_MASK (~0x0fUL) | |
| 146 | #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ | |
| 147 | #define PCI_PREF_MEMORY_LIMIT 0x26 | |
| 148 | #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL | |
| 149 | #define PCI_PREF_RANGE_TYPE_32 0x00 | |
| 150 | #define PCI_PREF_RANGE_TYPE_64 0x01 | |
| 151 | #define PCI_PREF_RANGE_MASK (~0x0fUL) | |
| 152 | #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ | |
| 153 | #define PCI_PREF_LIMIT_UPPER32 0x2c | |
| 154 | #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ | |
| 155 | #define PCI_IO_LIMIT_UPPER16 0x32 | |
| 156 | /* 0x34 same as for htype 0 */ | |
| 157 | /* 0x35-0x3b is reserved */ | |
| 158 | #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ | |
| 159 | /* 0x3c-0x3d are same as for htype 0 */ | |
| 160 | #define PCI_BRIDGE_CONTROL 0x3e | |
| 161 | #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ | |
| 162 | #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ | |
| 11949255 | 163 | #define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */ |
| 4352dfd5 GKH |
164 | #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ |
| 165 | #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ | |
| 166 | #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ | |
| 167 | #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ | |
| 168 | ||
| 169 | /* Header type 2 (CardBus bridges) */ | |
| 170 | #define PCI_CB_CAPABILITY_LIST 0x14 | |
| 171 | /* 0x15 reserved */ | |
| 172 | #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ | |
| 173 | #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ | |
| 174 | #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ | |
| 175 | #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ | |
| 176 | #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ | |
| 177 | #define PCI_CB_MEMORY_BASE_0 0x1c | |
| 178 | #define PCI_CB_MEMORY_LIMIT_0 0x20 | |
| 179 | #define PCI_CB_MEMORY_BASE_1 0x24 | |
| 180 | #define PCI_CB_MEMORY_LIMIT_1 0x28 | |
| 181 | #define PCI_CB_IO_BASE_0 0x2c | |
| 182 | #define PCI_CB_IO_BASE_0_HI 0x2e | |
| 183 | #define PCI_CB_IO_LIMIT_0 0x30 | |
| 184 | #define PCI_CB_IO_LIMIT_0_HI 0x32 | |
| 185 | #define PCI_CB_IO_BASE_1 0x34 | |
| 186 | #define PCI_CB_IO_BASE_1_HI 0x36 | |
| 187 | #define PCI_CB_IO_LIMIT_1 0x38 | |
| 188 | #define PCI_CB_IO_LIMIT_1_HI 0x3a | |
| 189 | #define PCI_CB_IO_RANGE_MASK (~0x03UL) | |
| 190 | /* 0x3c-0x3d are same as for htype 0 */ | |
| 191 | #define PCI_CB_BRIDGE_CONTROL 0x3e | |
| 192 | #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ | |
| 193 | #define PCI_CB_BRIDGE_CTL_SERR 0x02 | |
| 194 | #define PCI_CB_BRIDGE_CTL_ISA 0x04 | |
| 195 | #define PCI_CB_BRIDGE_CTL_VGA 0x08 | |
| 196 | #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 | |
| 197 | #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ | |
| 198 | #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ | |
| 199 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ | |
| 200 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 | |
| 201 | #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 | |
| 202 | #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 | |
| 203 | #define PCI_CB_SUBSYSTEM_ID 0x42 | |
| 204 | #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ | |
| 205 | /* 0x48-0x7f reserved */ | |
| 206 | ||
| 207 | /* Capability lists */ | |
| 208 | ||
| 209 | #define PCI_CAP_LIST_ID 0 /* Capability ID */ | |
| 210 | #define PCI_CAP_ID_PM 0x01 /* Power Management */ | |
| 211 | #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ | |
| 212 | #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ | |
| 213 | #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ | |
| 214 | #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ | |
| 215 | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ | |
| 216 | #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ | |
| 46ff3463 | 217 | #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ |
| f7625980 | 218 | #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */ |
| 9f672153 AC |
219 | #define PCI_CAP_ID_DBG 0x0A /* Debug port */ |
| 220 | #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ | |
| f7625980 | 221 | #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ |
| 9f672153 AC |
222 | #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ |
| 223 | #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ | |
| a0dee2ed | 224 | #define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */ |
| f7625980 | 225 | #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
| 4352dfd5 | 226 | #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
| a0dee2ed | 227 | #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */ |
| f7b7baae | 228 | #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ |
| f80b0ba9 SS |
229 | #define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */ |
| 230 | #define PCI_CAP_ID_MAX PCI_CAP_ID_EA | |
| 4352dfd5 GKH |
231 | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
| 232 | #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ | |
| 233 | #define PCI_CAP_SIZEOF 4 | |
| 234 | ||
| 235 | /* Power Management Registers */ | |
| 236 | ||
| 237 | #define PCI_PM_PMC 2 /* PM Capabilities Register */ | |
| 238 | #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ | |
| 239 | #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ | |
| 240 | #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ | |
| 241 | #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ | |
| 25985edc | 242 | #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxiliary power support mask */ |
| 4352dfd5 GKH |
243 | #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ |
| 244 | #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ | |
| 245 | #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ | |
| 246 | #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */ | |
| 247 | #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ | |
| 248 | #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */ | |
| 249 | #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ | |
| 250 | #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ | |
| 251 | #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ | |
| 337001b6 | 252 | #define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */ |
| 4352dfd5 GKH |
253 | #define PCI_PM_CTRL 4 /* PM control and status register */ |
| 254 | #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ | |
| 998dd7c7 | 255 | #define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */ |
| 4352dfd5 GKH |
256 | #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ |
| 257 | #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ | |
| 258 | #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ | |
| 259 | #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ | |
| 260 | #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ | |
| 261 | #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ | |
| 262 | #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ | |
| 263 | #define PCI_PM_DATA_REGISTER 7 /* (??) */ | |
| 264 | #define PCI_PM_SIZEOF 8 | |
| 265 | ||
| 266 | /* AGP registers */ | |
| 267 | ||
| 268 | #define PCI_AGP_VERSION 2 /* BCD version number */ | |
| 269 | #define PCI_AGP_RFU 3 /* Rest of capability flags */ | |
| 270 | #define PCI_AGP_STATUS 4 /* Status register */ | |
| 271 | #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ | |
| 272 | #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ | |
| 273 | #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ | |
| 274 | #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ | |
| 275 | #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ | |
| 276 | #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ | |
| 277 | #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ | |
| 278 | #define PCI_AGP_COMMAND 8 /* Control register */ | |
| 279 | #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ | |
| 280 | #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ | |
| 281 | #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ | |
| f7625980 BH |
282 | #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ |
| 283 | #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ | |
| 4352dfd5 GKH |
284 | #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ |
| 285 | #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ | |
| 286 | #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ | |
| 287 | #define PCI_AGP_SIZEOF 12 | |
| 288 | ||
| 289 | /* Vital Product Data */ | |
| 290 | ||
| 291 | #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */ | |
| 292 | #define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */ | |
| 293 | #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ | |
| 294 | #define PCI_VPD_DATA 4 /* 32-bits of data returned here */ | |
| a0dee2ed | 295 | #define PCI_CAP_VPD_SIZEOF 8 |
| 4352dfd5 GKH |
296 | |
| 297 | /* Slot Identification */ | |
| 298 | ||
| 299 | #define PCI_SID_ESR 2 /* Expansion Slot Register */ | |
| 300 | #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ | |
| 301 | #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ | |
| 302 | #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ | |
| 303 | ||
| 304 | /* Message Signalled Interrupts registers */ | |
| 305 | ||
| 24bc69da BH |
306 | #define PCI_MSI_FLAGS 2 /* Message Control */ |
| 307 | #define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */ | |
| 308 | #define PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available */ | |
| 309 | #define PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured */ | |
| 310 | #define PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */ | |
| 311 | #define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */ | |
| 4352dfd5 GKH |
312 | #define PCI_MSI_RFU 3 /* Rest of capability flags */ |
| 313 | #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ | |
| 314 | #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ | |
| 315 | #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ | |
| 67b5db65 | 316 | #define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */ |
| a0dee2ed | 317 | #define PCI_MSI_PENDING_32 16 /* Pending intrs for 32-bit devices */ |
| 4352dfd5 | 318 | #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ |
| 67b5db65 | 319 | #define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ |
| a0dee2ed | 320 | #define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */ |
| 4352dfd5 | 321 | |
| db500419 | 322 | /* MSI-X registers */ |
| 24bc69da BH |
323 | #define PCI_MSIX_FLAGS 2 /* Message Control */ |
| 324 | #define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */ | |
| 325 | #define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */ | |
| 326 | #define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */ | |
| 327 | #define PCI_MSIX_TABLE 4 /* Table offset */ | |
| 328 | #define PCI_MSIX_TABLE_BIR 0x00000007 /* BAR index */ | |
| 329 | #define PCI_MSIX_TABLE_OFFSET 0xfffffff8 /* Offset into specified BAR */ | |
| 330 | #define PCI_MSIX_PBA 8 /* Pending Bit Array offset */ | |
| 331 | #define PCI_MSIX_PBA_BIR 0x00000007 /* BAR index */ | |
| 332 | #define PCI_MSIX_PBA_OFFSET 0xfffffff8 /* Offset into specified BAR */ | |
| c9ddbac9 | 333 | #define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR /* deprecated */ |
| a0dee2ed | 334 | #define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ |
| e65e5fb5 | 335 | |
| f7625980 | 336 | /* MSI-X Table entry format */ |
| 00aaaef9 SY |
337 | #define PCI_MSIX_ENTRY_SIZE 16 |
| 338 | #define PCI_MSIX_ENTRY_LOWER_ADDR 0 | |
| 339 | #define PCI_MSIX_ENTRY_UPPER_ADDR 4 | |
| 340 | #define PCI_MSIX_ENTRY_DATA 8 | |
| 341 | #define PCI_MSIX_ENTRY_VECTOR_CTRL 12 | |
| 8d805286 | 342 | #define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 |
| 00aaaef9 | 343 | |
| 4352dfd5 GKH |
344 | /* CompactPCI Hotswap Register */ |
| 345 | ||
| 346 | #define PCI_CHSWP_CSR 2 /* Control and Status Register */ | |
| 347 | #define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */ | |
| 348 | #define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */ | |
| 349 | #define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */ | |
| 350 | #define PCI_CHSWP_LOO 0x08 /* LED On / Off */ | |
| 351 | #define PCI_CHSWP_PI 0x30 /* Programming Interface */ | |
| 352 | #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */ | |
| 353 | #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */ | |
| 354 | ||
| f7b7baae SY |
355 | /* PCI Advanced Feature registers */ |
| 356 | ||
| 357 | #define PCI_AF_LENGTH 2 | |
| 358 | #define PCI_AF_CAP 3 | |
| 359 | #define PCI_AF_CAP_TP 0x01 | |
| 360 | #define PCI_AF_CAP_FLR 0x02 | |
| 361 | #define PCI_AF_CTRL 4 | |
| 362 | #define PCI_AF_CTRL_FLR 0x01 | |
| 363 | #define PCI_AF_STATUS 5 | |
| 364 | #define PCI_AF_STATUS_TP 0x01 | |
| a0dee2ed | 365 | #define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */ |
| f7b7baae | 366 | |
| f80b0ba9 SS |
367 | /* PCI Enhanced Allocation registers */ |
| 368 | ||
| 369 | #define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */ | |
| 370 | #define PCI_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */ | |
| 371 | #define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */ | |
| 372 | #define PCI_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */ | |
| 373 | #define PCI_EA_ES 0x00000007 /* Entry Size */ | |
| 26635112 | 374 | #define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */ |
| f80b0ba9 SS |
375 | /* 0-5 map to BARs 0-5 respectively */ |
| 376 | #define PCI_EA_BEI_BAR0 0 | |
| 377 | #define PCI_EA_BEI_BAR5 5 | |
| 378 | #define PCI_EA_BEI_BRIDGE 6 /* Resource behind bridge */ | |
| 379 | #define PCI_EA_BEI_ENI 7 /* Equivalent Not Indicated */ | |
| 380 | #define PCI_EA_BEI_ROM 8 /* Expansion ROM */ | |
| 381 | /* 9-14 map to VF BARs 0-5 respectively */ | |
| 382 | #define PCI_EA_BEI_VF_BAR0 9 | |
| 383 | #define PCI_EA_BEI_VF_BAR5 14 | |
| 384 | #define PCI_EA_BEI_RESERVED 15 /* Reserved - Treat like ENI */ | |
| 26635112 BH |
385 | #define PCI_EA_PP 0x0000ff00 /* Primary Properties */ |
| 386 | #define PCI_EA_SP 0x00ff0000 /* Secondary Properties */ | |
| f80b0ba9 SS |
387 | #define PCI_EA_P_MEM 0x00 /* Non-Prefetch Memory */ |
| 388 | #define PCI_EA_P_MEM_PREFETCH 0x01 /* Prefetchable Memory */ | |
| 389 | #define PCI_EA_P_IO 0x02 /* I/O Space */ | |
| 390 | #define PCI_EA_P_VF_MEM_PREFETCH 0x03 /* VF Prefetchable Memory */ | |
| 391 | #define PCI_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */ | |
| 392 | #define PCI_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */ | |
| 393 | #define PCI_EA_P_BRIDGE_MEM_PREFETCH 0x06 /* Bridge Prefetchable Memory */ | |
| 394 | #define PCI_EA_P_BRIDGE_IO 0x07 /* Bridge I/O Space */ | |
| 395 | /* 0x08-0xfc reserved */ | |
| 396 | #define PCI_EA_P_MEM_RESERVED 0xfd /* Reserved Memory */ | |
| 397 | #define PCI_EA_P_IO_RESERVED 0xfe /* Reserved I/O Space */ | |
| 398 | #define PCI_EA_P_UNAVAILABLE 0xff /* Entry Unavailable */ | |
| 399 | #define PCI_EA_WRITABLE 0x40000000 /* Writable: 1 = RW, 0 = HwInit */ | |
| 400 | #define PCI_EA_ENABLE 0x80000000 /* Enable for this entry */ | |
| 401 | #define PCI_EA_BASE 4 /* Base Address Offset */ | |
| 402 | #define PCI_EA_MAX_OFFSET 8 /* MaxOffset (resource length) */ | |
| 403 | /* bit 0 is reserved */ | |
| 404 | #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */ | |
| 405 | #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ | |
| 406 | ||
| 7793eeab | 407 | /* PCI-X registers (Type 0 (non-bridge) devices) */ |
| 4352dfd5 GKH |
408 | |
| 409 | #define PCI_X_CMD 2 /* Modes & Features */ | |
| 410 | #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ | |
| 411 | #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ | |
| 9974a356 MC |
412 | #define PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */ |
| 413 | #define PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */ | |
| 414 | #define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */ | |
| 415 | #define PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */ | |
| 4352dfd5 | 416 | #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ |
| 9974a356 MC |
417 | /* Max # of outstanding split transactions */ |
| 418 | #define PCI_X_CMD_SPLIT_1 0x0000 /* Max 1 */ | |
| 419 | #define PCI_X_CMD_SPLIT_2 0x0010 /* Max 2 */ | |
| 420 | #define PCI_X_CMD_SPLIT_3 0x0020 /* Max 3 */ | |
| 421 | #define PCI_X_CMD_SPLIT_4 0x0030 /* Max 4 */ | |
| 422 | #define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */ | |
| 423 | #define PCI_X_CMD_SPLIT_12 0x0050 /* Max 12 */ | |
| 424 | #define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */ | |
| 425 | #define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */ | |
| 4352dfd5 | 426 | #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ |
| f7625980 | 427 | #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ |
| 4352dfd5 GKH |
428 | #define PCI_X_STATUS 4 /* PCI-X capabilities */ |
| 429 | #define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */ | |
| 430 | #define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */ | |
| 431 | #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */ | |
| 432 | #define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */ | |
| 433 | #define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */ | |
| 434 | #define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */ | |
| 435 | #define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */ | |
| 436 | #define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */ | |
| 437 | #define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */ | |
| 438 | #define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */ | |
| 439 | #define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */ | |
| 440 | #define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ | |
| 441 | #define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ | |
| a0dee2ed AW |
442 | #define PCI_X_ECC_CSR 8 /* ECC control and status */ |
| 443 | #define PCI_CAP_PCIX_SIZEOF_V0 8 /* size of registers for Version 0 */ | |
| 444 | #define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */ | |
| 445 | #define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */ | |
| 4352dfd5 | 446 | |
| 7793eeab BH |
447 | /* PCI-X registers (Type 1 (bridge) devices) */ |
| 448 | ||
| 449 | #define PCI_X_BRIDGE_SSTATUS 2 /* Secondary Status */ | |
| 450 | #define PCI_X_SSTATUS_64BIT 0x0001 /* Secondary AD interface is 64 bits */ | |
| 451 | #define PCI_X_SSTATUS_133MHZ 0x0002 /* 133 MHz capable */ | |
| 452 | #define PCI_X_SSTATUS_FREQ 0x03c0 /* Secondary Bus Mode and Frequency */ | |
| 453 | #define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */ | |
| 454 | #define PCI_X_SSTATUS_V1 0x1000 /* Mode 2, not Mode 1 */ | |
| 455 | #define PCI_X_SSTATUS_V2 0x2000 /* Mode 1 or Modes 1 and 2 */ | |
| 456 | #define PCI_X_SSTATUS_266MHZ 0x4000 /* 266 MHz capable */ | |
| 457 | #define PCI_X_SSTATUS_533MHZ 0x8000 /* 533 MHz capable */ | |
| 458 | #define PCI_X_BRIDGE_STATUS 4 /* Bridge Status */ | |
| 459 | ||
| bc577d2b GB |
460 | /* PCI Bridge Subsystem ID registers */ |
| 461 | ||
| f7625980 BH |
462 | #define PCI_SSVID_VENDOR_ID 4 /* PCI Bridge subsystem vendor ID */ |
| 463 | #define PCI_SSVID_DEVICE_ID 6 /* PCI Bridge subsystem device ID */ | |
| bc577d2b | 464 | |
| 4352dfd5 GKH |
465 | /* PCI Express capability registers */ |
| 466 | ||
| 467 | #define PCI_EXP_FLAGS 2 /* Capabilities register */ | |
| 468 | #define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ | |
| 469 | #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ | |
| 470 | #define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ | |
| 471 | #define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ | |
| 472 | #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ | |
| 473 | #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ | |
| 474 | #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ | |
| fbf501c3 BH |
475 | #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */ |
| 476 | #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */ | |
| d1b054da | 477 | #define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */ |
| 1830ea91 | 478 | #define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */ |
| 4352dfd5 GKH |
479 | #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ |
| 480 | #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ | |
| 481 | #define PCI_EXP_DEVCAP 4 /* Device capabilities */ | |
| c0b4b381 BH |
482 | #define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */ |
| 483 | #define PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */ | |
| 484 | #define PCI_EXP_DEVCAP_EXT_TAG 0x00000020 /* Extended tags */ | |
| 485 | #define PCI_EXP_DEVCAP_L0S 0x000001c0 /* L0s Acceptable Latency */ | |
| 486 | #define PCI_EXP_DEVCAP_L1 0x00000e00 /* L1 Acceptable Latency */ | |
| 487 | #define PCI_EXP_DEVCAP_ATN_BUT 0x00001000 /* Attention Button Present */ | |
| 488 | #define PCI_EXP_DEVCAP_ATN_IND 0x00002000 /* Attention Indicator Present */ | |
| 489 | #define PCI_EXP_DEVCAP_PWR_IND 0x00004000 /* Power Indicator Present */ | |
| 490 | #define PCI_EXP_DEVCAP_RBER 0x00008000 /* Role-Based Error Reporting */ | |
| 491 | #define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 /* Slot Power Limit Value */ | |
| 492 | #define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 /* Slot Power Limit Scale */ | |
| 8dd7f803 | 493 | #define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ |
| 4352dfd5 GKH |
494 | #define PCI_EXP_DEVCTL 8 /* Device Control */ |
| 495 | #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ | |
| 496 | #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ | |
| 497 | #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */ | |
| 498 | #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ | |
| 499 | #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ | |
| 500 | #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ | |
| 501 | #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ | |
| 502 | #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ | |
| 503 | #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ | |
| 504 | #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ | |
| 505 | #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ | |
| 5929b8a3 RM |
506 | #define PCI_EXP_DEVCTL_READRQ_128B 0x0000 /* 128 Bytes */ |
| 507 | #define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */ | |
| 508 | #define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */ | |
| 509 | #define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */ | |
| a5724fc3 HK |
510 | #define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */ |
| 511 | #define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */ | |
| 8dd7f803 | 512 | #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ |
| 4352dfd5 | 513 | #define PCI_EXP_DEVSTA 10 /* Device Status */ |
| c0b4b381 BH |
514 | #define PCI_EXP_DEVSTA_CED 0x0001 /* Correctable Error Detected */ |
| 515 | #define PCI_EXP_DEVSTA_NFED 0x0002 /* Non-Fatal Error Detected */ | |
| 516 | #define PCI_EXP_DEVSTA_FED 0x0004 /* Fatal Error Detected */ | |
| 517 | #define PCI_EXP_DEVSTA_URD 0x0008 /* Unsupported Request Detected */ | |
| 518 | #define PCI_EXP_DEVSTA_AUXPD 0x0010 /* AUX Power Detected */ | |
| 519 | #define PCI_EXP_DEVSTA_TRPND 0x0020 /* Transactions Pending */ | |
| ea5311c7 | 520 | #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1 12 /* v1 endpoints without link end here */ |
| 4352dfd5 | 521 | #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ |
| 322162a7 | 522 | #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ |
| c0b4b381 BH |
523 | #define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */ |
| 524 | #define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */ | |
| 56c1af46 | 525 | #define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ |
| 1acfb9b7 | 526 | #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ |
| 322162a7 KK |
527 | #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ |
| 528 | #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ | |
| 529 | #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ | |
| 530 | #define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */ | |
| cb93b186 | 531 | #define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* Clock Power Management */ |
| 25985edc | 532 | #define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Surprise Down Error Reporting Capable */ |
| 322162a7 KK |
533 | #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ |
| 534 | #define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */ | |
| 535 | #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ | |
| 4352dfd5 | 536 | #define PCI_EXP_LNKCTL 16 /* Link Control */ |
| 322162a7 | 537 | #define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ |
| c0b4b381 BH |
538 | #define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 /* L0s Enable */ |
| 539 | #define PCI_EXP_LNKCTL_ASPM_L1 0x0002 /* L1 Enable */ | |
| 322162a7 KK |
540 | #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ |
| 541 | #define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */ | |
| 542 | #define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */ | |
| 543 | #define PCI_EXP_LNKCTL_CCC 0x0040 /* Common Clock Configuration */ | |
| 544 | #define PCI_EXP_LNKCTL_ES 0x0080 /* Extended Synch */ | |
| c0b4b381 | 545 | #define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */ |
| 322162a7 KK |
546 | #define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */ |
| 547 | #define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */ | |
| f7625980 | 548 | #define PCI_EXP_LNKCTL_LABIE 0x0800 /* Link Autonomous Bandwidth Interrupt Enable */ |
| 4352dfd5 | 549 | #define PCI_EXP_LNKSTA 18 /* Link Status */ |
| 322162a7 | 550 | #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ |
| c0b4b381 BH |
551 | #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ |
| 552 | #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ | |
| 55fdbfe7 | 553 | #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ |
| 1acfb9b7 | 554 | #define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */ |
| f7625980 | 555 | #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ |
| 55fdbfe7 JK |
556 | #define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */ |
| 557 | #define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */ | |
| 558 | #define PCI_EXP_LNKSTA_NLW_X4 0x0040 /* Current Link Width x4 */ | |
| 559 | #define PCI_EXP_LNKSTA_NLW_X8 0x0080 /* Current Link Width x8 */ | |
| ff846f52 | 560 | #define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ |
| 322162a7 | 561 | #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ |
| 7d715a6c | 562 | #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ |
| 322162a7 KK |
563 | #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ |
| 564 | #define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ | |
| 565 | #define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */ | |
| ea5311c7 | 566 | #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints with link end here */ |
| 4352dfd5 | 567 | #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ |
| 322162a7 KK |
568 | #define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */ |
| 569 | #define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */ | |
| 570 | #define PCI_EXP_SLTCAP_MRLSP 0x00000004 /* MRL Sensor Present */ | |
| 571 | #define PCI_EXP_SLTCAP_AIP 0x00000008 /* Attention Indicator Present */ | |
| 572 | #define PCI_EXP_SLTCAP_PIP 0x00000010 /* Power Indicator Present */ | |
| 573 | #define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */ | |
| 574 | #define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */ | |
| 575 | #define PCI_EXP_SLTCAP_SPLV 0x00007f80 /* Slot Power Limit Value */ | |
| 576 | #define PCI_EXP_SLTCAP_SPLS 0x00018000 /* Slot Power Limit Scale */ | |
| 577 | #define PCI_EXP_SLTCAP_EIP 0x00020000 /* Electromechanical Interlock Present */ | |
| 578 | #define PCI_EXP_SLTCAP_NCCS 0x00040000 /* No Command Completed Support */ | |
| 579 | #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ | |
| 4352dfd5 | 580 | #define PCI_EXP_SLTCTL 24 /* Slot Control */ |
| 322162a7 KK |
581 | #define PCI_EXP_SLTCTL_ABPE 0x0001 /* Attention Button Pressed Enable */ |
| 582 | #define PCI_EXP_SLTCTL_PFDE 0x0002 /* Power Fault Detected Enable */ | |
| 583 | #define PCI_EXP_SLTCTL_MRLSCE 0x0004 /* MRL Sensor Changed Enable */ | |
| 584 | #define PCI_EXP_SLTCTL_PDCE 0x0008 /* Presence Detect Changed Enable */ | |
| 585 | #define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */ | |
| 586 | #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ | |
| 587 | #define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */ | |
| e7b4f0d7 BH |
588 | #define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 /* Attention Indicator on */ |
| 589 | #define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */ | |
| 590 | #define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 /* Attention Indicator off */ | |
| 322162a7 | 591 | #define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */ |
| e7b4f0d7 BH |
592 | #define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 /* Power Indicator on */ |
| 593 | #define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 /* Power Indicator blinking */ | |
| 594 | #define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 /* Power Indicator off */ | |
| 322162a7 | 595 | #define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */ |
| e7b4f0d7 BH |
596 | #define PCI_EXP_SLTCTL_PWR_ON 0x0000 /* Power On */ |
| 597 | #define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */ | |
| 322162a7 KK |
598 | #define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */ |
| 599 | #define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */ | |
| 4352dfd5 | 600 | #define PCI_EXP_SLTSTA 26 /* Slot Status */ |
| 322162a7 KK |
601 | #define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */ |
| 602 | #define PCI_EXP_SLTSTA_PFD 0x0002 /* Power Fault Detected */ | |
| 603 | #define PCI_EXP_SLTSTA_MRLSC 0x0004 /* MRL Sensor Changed */ | |
| 604 | #define PCI_EXP_SLTSTA_PDC 0x0008 /* Presence Detect Changed */ | |
| 605 | #define PCI_EXP_SLTSTA_CC 0x0010 /* Command Completed */ | |
| 606 | #define PCI_EXP_SLTSTA_MRLSS 0x0020 /* MRL Sensor State */ | |
| 607 | #define PCI_EXP_SLTSTA_PDS 0x0040 /* Presence Detect State */ | |
| 608 | #define PCI_EXP_SLTSTA_EIS 0x0080 /* Electromechanical Interlock Status */ | |
| 609 | #define PCI_EXP_SLTSTA_DLLSC 0x0100 /* Data Link Layer State Changed */ | |
| 4352dfd5 | 610 | #define PCI_EXP_RTCTL 28 /* Root Control */ |
| c0b4b381 BH |
611 | #define PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */ |
| 612 | #define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */ | |
| 613 | #define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */ | |
| 614 | #define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */ | |
| 615 | #define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */ | |
| 4352dfd5 | 616 | #define PCI_EXP_RTCAP 30 /* Root Capabilities */ |
| f3dbd802 | 617 | #define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ |
| 4352dfd5 | 618 | #define PCI_EXP_RTSTA 32 /* Root Status */ |
| c0b4b381 BH |
619 | #define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ |
| 620 | #define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */ | |
| c463b8cb | 621 | /* |
| 1b121c24 BH |
622 | * The Device Capabilities 2, Device Status 2, Device Control 2, |
| 623 | * Link Capabilities 2, Link Status 2, Link Control 2, | |
| 624 | * Slot Capabilities 2, Slot Status 2, and Slot Control 2 registers | |
| 625 | * are only present on devices with PCIe Capability version 2. | |
| 626 | * Use pcie_capability_read_word() and similar interfaces to use them | |
| 627 | * safely. | |
| c463b8cb | 628 | */ |
| 58c3a727 | 629 | #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ |
| fdabc3fe | 630 | #define PCI_EXP_DEVCAP2_COMP_TMOUT_DIS 0x00000010 /* Completion Timeout Disable supported */ |
| c0b4b381 | 631 | #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */ |
| 2e0cbc4d | 632 | #define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */ |
| 430a2368 JC |
633 | #define PCI_EXP_DEVCAP2_ATOMIC_COMP32 0x00000080 /* 32b AtomicOp completion */ |
| 634 | #define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completion */ | |
| 635 | #define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion */ | |
| c0b4b381 BH |
636 | #define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ |
| 637 | #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ | |
| 638 | #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ | |
| 639 | #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ | |
| 7ce3f912 | 640 | #define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */ |
| 58c3a727 | 641 | #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ |
| ad4d35f8 | 642 | #define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ |
| fdabc3fe | 643 | #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */ |
| ad4d35f8 | 644 | #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ |
| 2e0cbc4d | 645 | #define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */ |
| f92faaba | 646 | #define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */ |
| c0b4b381 BH |
647 | #define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */ |
| 648 | #define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */ | |
| 649 | #define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */ | |
| 650 | #define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 /* Enable OBFF Message type A */ | |
| 651 | #define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 /* Enable OBFF Message type B */ | |
| d2ab1fa6 | 652 | #define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ |
| bd6fb762 | 653 | #define PCI_EXP_DEVSTA2 42 /* Device Status 2 */ |
| ea5311c7 | 654 | #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints without link end here */ |
| bd6fb762 | 655 | #define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */ |
| c0b4b381 | 656 | #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */ |
| 1acfb9b7 JF |
657 | #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */ |
| 658 | #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */ | |
| 659 | #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ | |
| c0b4b381 | 660 | #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ |
| 89858517 | 661 | #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ |
| c80851f6 FL |
662 | #define PCI_EXP_LNKCTL2_TLS 0x000f |
| 663 | #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ | |
| 664 | #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ | |
| 665 | #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ | |
| 666 | #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ | |
| 8c0d3a02 | 667 | #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ |
| ea5311c7 | 668 | #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ |
| bd6fb762 | 669 | #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ |
| 89858517 | 670 | #define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ |
| bd6fb762 | 671 | #define PCI_EXP_SLTSTA2 58 /* Slot Status 2 */ |
| 4352dfd5 GKH |
672 | |
| 673 | /* Extended Capabilities (PCI-X 2.0 and Express) */ | |
| 674 | #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) | |
| 675 | #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) | |
| 676 | #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) | |
| 677 | ||
| a0dee2ed AW |
678 | #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ |
| 679 | #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ | |
| 680 | #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ | |
| 681 | #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ | |
| 682 | #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ | |
| 683 | #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ | |
| 684 | #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ | |
| 685 | #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ | |
| 686 | #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ | |
| 687 | #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ | |
| f7625980 | 688 | #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ |
| a0dee2ed AW |
689 | #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ |
| 690 | #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ | |
| 691 | #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ | |
| 692 | #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ | |
| 693 | #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ | |
| 694 | #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ | |
| 695 | #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ | |
| 696 | #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ | |
| f7625980 BH |
697 | #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ |
| 698 | #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ | |
| 699 | #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ | |
| 700 | #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ | |
| 701 | #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ | |
| 702 | #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ | |
| a0dee2ed AW |
703 | #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ |
| 704 | #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ | |
| 10126ac1 | 705 | #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ |
| 0fc1223f | 706 | #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ |
| 9bb04a0c JY |
707 | #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ |
| 708 | #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM | |
| a0dee2ed AW |
709 | |
| 710 | #define PCI_EXT_CAP_DSN_SIZEOF 12 | |
| 711 | #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 | |
| 4352dfd5 GKH |
712 | |
| 713 | /* Advanced Error Reporting */ | |
| 714 | #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ | |
| 846fc709 | 715 | #define PCI_ERR_UNC_UND 0x00000001 /* Undefined */ |
| 4352dfd5 | 716 | #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ |
| a0dee2ed | 717 | #define PCI_ERR_UNC_SURPDN 0x00000020 /* Surprise Down */ |
| 4352dfd5 GKH |
718 | #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ |
| 719 | #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ | |
| 720 | #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ | |
| 721 | #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ | |
| 722 | #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ | |
| 723 | #define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ | |
| 724 | #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ | |
| 725 | #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ | |
| 726 | #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ | |
| a0dee2ed AW |
727 | #define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */ |
| 728 | #define PCI_ERR_UNC_INTN 0x00400000 /* internal error */ | |
| 729 | #define PCI_ERR_UNC_MCBTLP 0x00800000 /* MC blocked TLP */ | |
| 730 | #define PCI_ERR_UNC_ATOMEG 0x01000000 /* Atomic egress blocked */ | |
| 731 | #define PCI_ERR_UNC_TLPPRE 0x02000000 /* TLP prefix blocked */ | |
| 4352dfd5 GKH |
732 | #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ |
| 733 | /* Same bits as above */ | |
| 734 | #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ | |
| 735 | /* Same bits as above */ | |
| 736 | #define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */ | |
| 737 | #define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */ | |
| 738 | #define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ | |
| 739 | #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ | |
| 740 | #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ | |
| 741 | #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ | |
| a0dee2ed AW |
742 | #define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */ |
| 743 | #define PCI_ERR_COR_INTERNAL 0x00004000 /* Corrected Internal */ | |
| 744 | #define PCI_ERR_COR_LOG_OVER 0x00008000 /* Header Log Overflow */ | |
| 4352dfd5 GKH |
745 | #define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ |
| 746 | /* Same bits as above */ | |
| 747 | #define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ | |
| 748 | #define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ | |
| 749 | #define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */ | |
| 750 | #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ | |
| 751 | #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ | |
| 752 | #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ | |
| 753 | #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ | |
| 754 | #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ | |
| 8fc614c0 BH |
755 | #define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */ |
| 756 | #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */ | |
| 757 | #define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */ | |
| 4352dfd5 | 758 | #define PCI_ERR_ROOT_STATUS 48 |
| 8fc614c0 BH |
759 | #define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ |
| 760 | #define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */ | |
| 761 | #define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */ | |
| 762 | #define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */ | |
| 763 | #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */ | |
| 764 | #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ | |
| 765 | #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ | |
| 7c950b9e | 766 | #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ |
| f647a44f | 767 | #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ |
| 4352dfd5 GKH |
768 | |
| 769 | /* Virtual Channel */ | |
| 274127a1 AW |
770 | #define PCI_VC_PORT_CAP1 4 |
| 771 | #define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ | |
| 772 | #define PCI_VC_CAP1_LPEVCC 0x00000070 /* low prio extended VC count */ | |
| 773 | #define PCI_VC_CAP1_ARB_SIZE 0x00000c00 | |
| 774 | #define PCI_VC_PORT_CAP2 8 | |
| 775 | #define PCI_VC_CAP2_32_PHASE 0x00000002 | |
| 776 | #define PCI_VC_CAP2_64_PHASE 0x00000004 | |
| 777 | #define PCI_VC_CAP2_128_PHASE 0x00000008 | |
| 778 | #define PCI_VC_CAP2_ARB_OFF 0xff000000 | |
| 4352dfd5 | 779 | #define PCI_VC_PORT_CTRL 12 |
| 425c1b22 | 780 | #define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 |
| 4352dfd5 | 781 | #define PCI_VC_PORT_STATUS 14 |
| 425c1b22 | 782 | #define PCI_VC_PORT_STATUS_TABLE 0x00000001 |
| 4352dfd5 | 783 | #define PCI_VC_RES_CAP 16 |
| 425c1b22 AW |
784 | #define PCI_VC_RES_CAP_32_PHASE 0x00000002 |
| 785 | #define PCI_VC_RES_CAP_64_PHASE 0x00000004 | |
| 786 | #define PCI_VC_RES_CAP_128_PHASE 0x00000008 | |
| 787 | #define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010 | |
| 788 | #define PCI_VC_RES_CAP_256_PHASE 0x00000020 | |
| 789 | #define PCI_VC_RES_CAP_ARB_OFF 0xff000000 | |
| 4352dfd5 | 790 | #define PCI_VC_RES_CTRL 20 |
| 425c1b22 AW |
791 | #define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000 |
| 792 | #define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000 | |
| 793 | #define PCI_VC_RES_CTRL_ID 0x07000000 | |
| 794 | #define PCI_VC_RES_CTRL_ENABLE 0x80000000 | |
| 4352dfd5 | 795 | #define PCI_VC_RES_STATUS 26 |
| 425c1b22 AW |
796 | #define PCI_VC_RES_STATUS_TABLE 0x00000001 |
| 797 | #define PCI_VC_RES_STATUS_NEGO 0x00000002 | |
| a0dee2ed AW |
798 | #define PCI_CAP_VC_BASE_SIZEOF 0x10 |
| 799 | #define PCI_CAP_VC_PER_VC_SIZEOF 0x0C | |
| 4352dfd5 GKH |
800 | |
| 801 | /* Power Budgeting */ | |
| 802 | #define PCI_PWR_DSR 4 /* Data Select Register */ | |
| 803 | #define PCI_PWR_DATA 8 /* Data Register */ | |
| 804 | #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ | |
| 805 | #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ | |
| 806 | #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ | |
| 807 | #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ | |
| 808 | #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ | |
| 809 | #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ | |
| 810 | #define PCI_PWR_CAP 12 /* Capability */ | |
| 811 | #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ | |
| a0dee2ed | 812 | #define PCI_EXT_CAP_PWR_SIZEOF 16 |
| 4352dfd5 | 813 | |
| defb9446 BH |
814 | /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */ |
| 815 | #define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */ | |
| 816 | #define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) | |
| 817 | #define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) | |
| 818 | #define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) | |
| 819 | ||
| 687d5fe3 | 820 | /* |
| f7625980 | 821 | * HyperTransport sub capability types |
| 687d5fe3 ME |
822 | * |
| 823 | * Unfortunately there are both 3 bit and 5 bit capability types defined | |
| 824 | * in the HT spec, catering for that is a little messy. You probably don't | |
| 825 | * want to use these directly, just use pci_find_ht_capability() and it | |
| 826 | * will do the right thing for you. | |
| 827 | */ | |
| 828 | #define HT_3BIT_CAP_MASK 0xE0 | |
| e78d0169 EB |
829 | #define HT_CAPTYPE_SLAVE 0x00 /* Slave/Primary link configuration */ |
| 830 | #define HT_CAPTYPE_HOST 0x20 /* Host/Secondary link configuration */ | |
| 687d5fe3 ME |
831 | |
| 832 | #define HT_5BIT_CAP_MASK 0xF8 | |
| e78d0169 EB |
833 | #define HT_CAPTYPE_IRQ 0x80 /* IRQ Configuration */ |
| 834 | #define HT_CAPTYPE_REMAPPING_40 0xA0 /* 40 bit address remapping */ | |
| 835 | #define HT_CAPTYPE_REMAPPING_64 0xA2 /* 64 bit address remapping */ | |
| 836 | #define HT_CAPTYPE_UNITID_CLUMP 0x90 /* Unit ID clumping */ | |
| 837 | #define HT_CAPTYPE_EXTCONF 0x98 /* Extended Configuration Space Access */ | |
| 838 | #define HT_CAPTYPE_MSI_MAPPING 0xA8 /* MSI Mapping Capability */ | |
| d010b51c ME |
839 | #define HT_MSI_FLAGS 0x02 /* Offset to flags */ |
| 840 | #define HT_MSI_FLAGS_ENABLE 0x1 /* Mapping enable */ | |
| 841 | #define HT_MSI_FLAGS_FIXED 0x2 /* Fixed mapping only */ | |
| 842 | #define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL /* Fixed addr */ | |
| 843 | #define HT_MSI_ADDR_LO 0x04 /* Offset to low addr bits */ | |
| 844 | #define HT_MSI_ADDR_LO_MASK 0xFFF00000 /* Low address bit mask */ | |
| 845 | #define HT_MSI_ADDR_HI 0x08 /* Offset to high addr bits */ | |
| e78d0169 EB |
846 | #define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */ |
| 847 | #define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */ | |
| 848 | #define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */ | |
| f7625980 BH |
849 | #define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 HyperTransport configuration */ |
| 850 | #define HT_CAPTYPE_PM 0xE0 /* HyperTransport power management configuration */ | |
| a0dee2ed AW |
851 | #define HT_CAP_SIZEOF_LONG 28 /* slave & primary */ |
| 852 | #define HT_CAP_SIZEOF_SHORT 24 /* host & secondary */ | |
| e78d0169 | 853 | |
| 58c3a727 YZ |
854 | /* Alternative Routing-ID Interpretation */ |
| 855 | #define PCI_ARI_CAP 0x04 /* ARI Capability Register */ | |
| 856 | #define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */ | |
| 857 | #define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */ | |
| 858 | #define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ | |
| 859 | #define PCI_ARI_CTRL 0x06 /* ARI Control Register */ | |
| 860 | #define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ | |
| 861 | #define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ | |
| 862 | #define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ | |
| a0dee2ed | 863 | #define PCI_EXT_CAP_ARI_SIZEOF 8 |
| e78d0169 | 864 | |
| 302b4215 YZ |
865 | /* Address Translation Service */ |
| 866 | #define PCI_ATS_CAP 0x04 /* ATS Capability Register */ | |
| 867 | #define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) /* Invalidate Queue Depth */ | |
| 868 | #define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */ | |
| 8c938ddc | 869 | #define PCI_ATS_CAP_PAGE_ALIGNED 0x0020 /* Page Aligned Request */ |
| 302b4215 YZ |
870 | #define PCI_ATS_CTRL 0x06 /* ATS Control Register */ |
| 871 | #define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */ | |
| 872 | #define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ | |
| 873 | #define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */ | |
| a0dee2ed | 874 | #define PCI_EXT_CAP_ATS_SIZEOF 8 |
| 302b4215 | 875 | |
| c320b976 | 876 | /* Page Request Interface */ |
| 91f57d5e AW |
877 | #define PCI_PRI_CTRL 0x04 /* PRI control register */ |
| 878 | #define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */ | |
| 879 | #define PCI_PRI_CTRL_RESET 0x02 /* Reset */ | |
| 880 | #define PCI_PRI_STATUS 0x06 /* PRI status register */ | |
| 881 | #define PCI_PRI_STATUS_RF 0x001 /* Response Failure */ | |
| 882 | #define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */ | |
| 883 | #define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */ | |
| e5567f5f | 884 | #define PCI_PRI_STATUS_PASID 0x8000 /* PRG Response PASID Required */ |
| 91f57d5e AW |
885 | #define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ |
| 886 | #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ | |
| a0dee2ed | 887 | #define PCI_EXT_CAP_PRI_SIZEOF 16 |
| c320b976 | 888 | |
| f7625980 | 889 | /* Process Address Space ID */ |
| 91f57d5e AW |
890 | #define PCI_PASID_CAP 0x04 /* PASID feature register */ |
| 891 | #define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ | |
| f7625980 | 892 | #define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */ |
| 91f57d5e AW |
893 | #define PCI_PASID_CTRL 0x06 /* PASID control register */ |
| 894 | #define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ | |
| 895 | #define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ | |
| f7625980 | 896 | #define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */ |
| a0dee2ed | 897 | #define PCI_EXT_CAP_PASID_SIZEOF 8 |
| 086ac11f | 898 | |
| d1b054da YZ |
899 | /* Single Root I/O Virtualization */ |
| 900 | #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ | |
| 901 | #define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */ | |
| 902 | #define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */ | |
| 903 | #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ | |
| 904 | #define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ | |
| 905 | #define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */ | |
| 906 | #define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */ | |
| 907 | #define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ | |
| 908 | #define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */ | |
| 909 | #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */ | |
| 910 | #define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */ | |
| 911 | #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ | |
| 912 | #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ | |
| 913 | #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ | |
| 914 | #define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */ | |
| 915 | #define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ | |
| 916 | #define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ | |
| 917 | #define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ | |
| 918 | #define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ | |
| 919 | #define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */ | |
| 920 | #define PCI_SRIOV_BAR 0x24 /* VF BAR0 */ | |
| 921 | #define PCI_SRIOV_NUM_BARS 6 /* Number of VF BARs */ | |
| 922 | #define PCI_SRIOV_VFM 0x3c /* VF Migration State Array Offset*/ | |
| 923 | #define PCI_SRIOV_VFM_BIR(x) ((x) & 7) /* State BIR */ | |
| 924 | #define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) /* State Offset */ | |
| 925 | #define PCI_SRIOV_VFM_UA 0x0 /* Inactive.Unavailable */ | |
| 926 | #define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */ | |
| 927 | #define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */ | |
| 928 | #define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */ | |
| a0dee2ed | 929 | #define PCI_EXT_CAP_SRIOV_SIZEOF 64 |
| d1b054da | 930 | |
| 51c2e0a7 JB |
931 | #define PCI_LTR_MAX_SNOOP_LAT 0x4 |
| 932 | #define PCI_LTR_MAX_NOSNOOP_LAT 0x6 | |
| 933 | #define PCI_LTR_VALUE_MASK 0x000003ff | |
| 934 | #define PCI_LTR_SCALE_MASK 0x00001c00 | |
| 935 | #define PCI_LTR_SCALE_SHIFT 10 | |
| a0dee2ed | 936 | #define PCI_EXT_CAP_LTR_SIZEOF 8 |
| 51c2e0a7 | 937 | |
| ae21ee65 AK |
938 | /* Access Control Service */ |
| 939 | #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ | |
| 940 | #define PCI_ACS_SV 0x01 /* Source Validation */ | |
| 941 | #define PCI_ACS_TB 0x02 /* Translation Blocking */ | |
| 942 | #define PCI_ACS_RR 0x04 /* P2P Request Redirect */ | |
| 943 | #define PCI_ACS_CR 0x08 /* P2P Completion Redirect */ | |
| 944 | #define PCI_ACS_UF 0x10 /* Upstream Forwarding */ | |
| 945 | #define PCI_ACS_EC 0x20 /* P2P Egress Control */ | |
| 946 | #define PCI_ACS_DT 0x40 /* Direct Translated P2P */ | |
| a0dee2ed | 947 | #define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */ |
| ae21ee65 AK |
948 | #define PCI_ACS_CTRL 0x06 /* ACS Control Register */ |
| 949 | #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ | |
| 950 | ||
| f7625980 | 951 | #define PCI_VSEC_HDR 4 /* extended cap - vendor-specific */ |
| a0dee2ed AW |
952 | #define PCI_VSEC_HDR_LEN_SHIFT 20 /* shift for length field */ |
| 953 | ||
| f7625980 | 954 | /* SATA capability */ |
| a0dee2ed AW |
955 | #define PCI_SATA_REGS 4 /* SATA REGs specifier */ |
| 956 | #define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */ | |
| 957 | #define PCI_SATA_REGS_INLINE 0xF /* REGS in config space */ | |
| 958 | #define PCI_SATA_SIZEOF_SHORT 8 | |
| 959 | #define PCI_SATA_SIZEOF_LONG 16 | |
| 960 | ||
| f7625980 | 961 | /* Resizable BARs */ |
| 276b738d CK |
962 | #define PCI_REBAR_CAP 4 /* capability register */ |
| 963 | #define PCI_REBAR_CAP_SIZES 0x00FFFFF0 /* supported BAR sizes */ | |
| a0dee2ed | 964 | #define PCI_REBAR_CTRL 8 /* control register */ |
| 276b738d CK |
965 | #define PCI_REBAR_CTRL_BAR_IDX 0x00000007 /* BAR index */ |
| 966 | #define PCI_REBAR_CTRL_NBAR_MASK 0x000000E0 /* # of resizable BARs */ | |
| b1277a22 | 967 | #define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # of BARs */ |
| 276b738d | 968 | #define PCI_REBAR_CTRL_BAR_SIZE 0x00001F00 /* BAR size */ |
| b1277a22 | 969 | #define PCI_REBAR_CTRL_BAR_SHIFT 8 /* shift for BAR size */ |
| a0dee2ed | 970 | |
| f7625980 | 971 | /* Dynamic Power Allocation */ |
| a0dee2ed AW |
972 | #define PCI_DPA_CAP 4 /* capability register */ |
| 973 | #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */ | |
| 974 | #define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */ | |
| 975 | ||
| 976 | /* TPH Requester */ | |
| 977 | #define PCI_TPH_CAP 4 /* capability register */ | |
| 978 | #define PCI_TPH_CAP_LOC_MASK 0x600 /* location mask */ | |
| 979 | #define PCI_TPH_LOC_NONE 0x000 /* no location */ | |
| 980 | #define PCI_TPH_LOC_CAP 0x200 /* in capability */ | |
| 981 | #define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */ | |
| 982 | #define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* st table mask */ | |
| 983 | #define PCI_TPH_CAP_ST_SHIFT 16 /* st table shift */ | |
| 984 | #define PCI_TPH_BASE_SIZEOF 12 /* size with no st table */ | |
| 985 | ||
| 26e51571 KB |
986 | /* Downstream Port Containment */ |
| 987 | #define PCI_EXP_DPC_CAP 4 /* DPC Capability */ | |
| 65d5e913 BH |
988 | #define PCI_EXP_DPC_IRQ 0x001F /* Interrupt Message Number */ |
| 989 | #define PCI_EXP_DPC_CAP_RP_EXT 0x0020 /* Root Port Extensions */ | |
| 990 | #define PCI_EXP_DPC_CAP_POISONED_TLP 0x0040 /* Poisoned TLP Egress Blocking Supported */ | |
| 991 | #define PCI_EXP_DPC_CAP_SW_TRIGGER 0x0080 /* Software Triggering Supported */ | |
| 992 | #define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0x0F00 /* RP PIO Log Size */ | |
| 26e51571 KB |
993 | #define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */ |
| 994 | ||
| 995 | #define PCI_EXP_DPC_CTL 6 /* DPC control */ | |
| 6927868e | 996 | #define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */ |
| 65d5e913 BH |
997 | #define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */ |
| 998 | #define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */ | |
| 26e51571 KB |
999 | |
| 1000 | #define PCI_EXP_DPC_STATUS 8 /* DPC Status */ | |
| 65d5e913 BH |
1001 | #define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */ |
| 1002 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006 /* Trigger Reason */ | |
| 1003 | #define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 /* Interrupt Status */ | |
| 1004 | #define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */ | |
| 1005 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */ | |
| 26e51571 KB |
1006 | |
| 1007 | #define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */ | |
| 1008 | ||
| f20c4ea4 | 1009 | #define PCI_EXP_DPC_RP_PIO_STATUS 0x0C /* RP PIO Status */ |
| 65d5e913 | 1010 | #define PCI_EXP_DPC_RP_PIO_MASK 0x10 /* RP PIO Mask */ |
| f20c4ea4 DL |
1011 | #define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14 /* RP PIO Severity */ |
| 1012 | #define PCI_EXP_DPC_RP_PIO_SYSERROR 0x18 /* RP PIO SysError */ | |
| 1013 | #define PCI_EXP_DPC_RP_PIO_EXCEPTION 0x1C /* RP PIO Exception */ | |
| 1014 | #define PCI_EXP_DPC_RP_PIO_HEADER_LOG 0x20 /* RP PIO Header Log */ | |
| 1015 | #define PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG 0x30 /* RP PIO ImpSpec Log */ | |
| 1016 | #define PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG 0x34 /* RP PIO TLP Prefix Log */ | |
| 1017 | ||
| 9bb04a0c JY |
1018 | /* Precision Time Measurement */ |
| 1019 | #define PCI_PTM_CAP 0x04 /* PTM Capability */ | |
| eec097d4 | 1020 | #define PCI_PTM_CAP_REQ 0x00000001 /* Requester capable */ |
| 9bb04a0c | 1021 | #define PCI_PTM_CAP_ROOT 0x00000004 /* Root capable */ |
| 8b2ec318 | 1022 | #define PCI_PTM_GRANULARITY_MASK 0x0000FF00 /* Clock granularity */ |
| 9bb04a0c JY |
1023 | #define PCI_PTM_CTRL 0x08 /* PTM Control */ |
| 1024 | #define PCI_PTM_CTRL_ENABLE 0x00000001 /* PTM enable */ | |
| 1025 | #define PCI_PTM_CTRL_ROOT 0x00000002 /* Root select */ | |
| 1026 | ||
| 7f88ba4a BH |
1027 | /* ASPM L1 PM Substates */ |
| 1028 | #define PCI_L1SS_CAP 0x04 /* Capabilities Register */ | |
| 1029 | #define PCI_L1SS_CAP_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Supported */ | |
| 1030 | #define PCI_L1SS_CAP_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Supported */ | |
| 1031 | #define PCI_L1SS_CAP_ASPM_L1_2 0x00000004 /* ASPM L1.2 Supported */ | |
| 1032 | #define PCI_L1SS_CAP_ASPM_L1_1 0x00000008 /* ASPM L1.1 Supported */ | |
| 1033 | #define PCI_L1SS_CAP_L1_PM_SS 0x00000010 /* L1 PM Substates Supported */ | |
| a48f3d5b BH |
1034 | #define PCI_L1SS_CAP_CM_RESTORE_TIME 0x0000ff00 /* Port Common_Mode_Restore_Time */ |
| 1035 | #define PCI_L1SS_CAP_P_PWR_ON_SCALE 0x00030000 /* Port T_POWER_ON scale */ | |
| 1036 | #define PCI_L1SS_CAP_P_PWR_ON_VALUE 0x00f80000 /* Port T_POWER_ON value */ | |
| 7f88ba4a BH |
1037 | #define PCI_L1SS_CTL1 0x08 /* Control 1 Register */ |
| 1038 | #define PCI_L1SS_CTL1_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Enable */ | |
| 1039 | #define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */ | |
| 1040 | #define PCI_L1SS_CTL1_ASPM_L1_2 0x00000004 /* ASPM L1.2 Enable */ | |
| 1041 | #define PCI_L1SS_CTL1_ASPM_L1_1 0x00000008 /* ASPM L1.1 Enable */ | |
| 1042 | #define PCI_L1SS_CTL1_L1SS_MASK 0x0000000f | |
| a48f3d5b BH |
1043 | #define PCI_L1SS_CTL1_CM_RESTORE_TIME 0x0000ff00 /* Common_Mode_Restore_Time */ |
| 1044 | #define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 /* LTR_L1.2_THRESHOLD_Value */ | |
| 1045 | #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ | |
| 7f88ba4a | 1046 | #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ |
| 0fc1223f | 1047 | |
| 4352dfd5 | 1048 | #endif /* LINUX_PCI_REGS_H */ |