]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - include/uapi/linux/v4l2-dv-timings.h
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[media] v4l2-dv-timings: add VICs and picture aspect ratio
[mirror_ubuntu-artful-kernel.git] / include / uapi / linux / v4l2-dv-timings.h
CommitLineData
f00dc304
HV		 1/*
2 * V4L2 DV timings header.
3 *
cf038120 4 * Copyright (C) 2012-2016 Hans Verkuil <hans.verkuil@cisco.com>
f00dc304
HV		 5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
f00dc304
HV		 14 */
15
16#ifndef _V4L2_DV_TIMINGS_H
17#define _V4L2_DV_TIMINGS_H
18
607ec6a5
MCC		 19#if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6))
20/* Sadly gcc versions older than 4.6 have a bug in how they initialize
21 anonymous unions where they require additional curly brackets.
22 This violates the C1x standard. This workaround adds the curly brackets
23 if needed. */
f00dc304
HV		 24#define V4L2_INIT_BT_TIMINGS(_width, args...) \
25 { .bt = { _width , ## args } }
607ec6a5
MCC		 26#else
27#define V4L2_INIT_BT_TIMINGS(_width, args...) \
28 .bt = { _width , ## args }
29#endif
f00dc304 30
cf038120 31/* CEA-861-F timings (i.e. standard HDTV timings) */
f00dc304
HV		 32
33#define V4L2_DV_BT_CEA_640X480P59_94 { \
34 .type = V4L2_DV_BT_656_1120, \
35 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
36 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \
cf038120
HV		 37 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
38 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 1) \
f00dc304
HV		 39}
40
a7b74bd8
HV		 41/* Note: these are the nominal timings, for HDMI links this format is typically
42 * double-clocked to meet the minimum pixelclock requirements. */
43#define V4L2_DV_BT_CEA_720X480I59_94 { \
44 .type = V4L2_DV_BT_656_1120, \
45 V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
46 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \
5ce65d1f 47 V4L2_DV_BT_STD_CEA861, \
cf038120
HV		 48 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
49 V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
50 { 4, 3 }, 6) \
a7b74bd8
HV		 51}
52
f00dc304
HV		 53#define V4L2_DV_BT_CEA_720X480P59_94 { \
54 .type = V4L2_DV_BT_656_1120, \
55 V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
56 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
cf038120
HV		 57 V4L2_DV_BT_STD_CEA861, \
58 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
59 V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 2) \
f00dc304
HV		 60}
61
a7b74bd8
HV		 62/* Note: these are the nominal timings, for HDMI links this format is typically
63 * double-clocked to meet the minimum pixelclock requirements. */
64#define V4L2_DV_BT_CEA_720X576I50 { \
65 .type = V4L2_DV_BT_656_1120, \
66 V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
67 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \
5ce65d1f 68 V4L2_DV_BT_STD_CEA861, \
cf038120
HV		 69 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
70 V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
71 { 4, 3 }, 21) \
a7b74bd8
HV		 72}
73
f00dc304
HV		 74#define V4L2_DV_BT_CEA_720X576P50 { \
75 .type = V4L2_DV_BT_656_1120, \
76 V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
77 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
cf038120
HV		 78 V4L2_DV_BT_STD_CEA861, \
79 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
80 V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 17) \
f00dc304
HV		 81}
82
83#define V4L2_DV_BT_CEA_1280X720P24 { \
84 .type = V4L2_DV_BT_656_1120, \
85 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
86 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
87 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
88 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
cf038120 89 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 60) \
f00dc304
HV		 90}
91
92#define V4L2_DV_BT_CEA_1280X720P25 { \
93 .type = V4L2_DV_BT_656_1120, \
94 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
95 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
96 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
cf038120
HV		 97 V4L2_DV_BT_STD_CEA861, \
98 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 61) \
f00dc304
HV		 99}
100
101#define V4L2_DV_BT_CEA_1280X720P30 { \
102 .type = V4L2_DV_BT_656_1120, \
103 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
104 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
105 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
5ce65d1f 106 V4L2_DV_BT_STD_CEA861, \
cf038120
HV		 107 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
108 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 62) \
f00dc304
HV		 109}
110
111#define V4L2_DV_BT_CEA_1280X720P50 { \
112 .type = V4L2_DV_BT_656_1120, \
113 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
114 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
115 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
cf038120
HV		 116 V4L2_DV_BT_STD_CEA861, \
117 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 19) \
f00dc304
HV		 118}
119
120#define V4L2_DV_BT_CEA_1280X720P60 { \
121 .type = V4L2_DV_BT_656_1120, \
122 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
123 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
124 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
5ce65d1f 125 V4L2_DV_BT_STD_CEA861, \
cf038120
HV		 126 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
127 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 4) \
f00dc304
HV		 128}
129
130#define V4L2_DV_BT_CEA_1920X1080P24 { \
131 .type = V4L2_DV_BT_656_1120, \
132 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
133 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
134 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
5ce65d1f 135 V4L2_DV_BT_STD_CEA861, \
cf038120
HV		 136 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
137 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 32) \
f00dc304
HV		 138}
139
140#define V4L2_DV_BT_CEA_1920X1080P25 { \
141 .type = V4L2_DV_BT_656_1120, \
142 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
143 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
144 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
cf038120
HV		 145 V4L2_DV_BT_STD_CEA861, \
146 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 33) \
f00dc304
HV		 147}
148
149#define V4L2_DV_BT_CEA_1920X1080P30 { \
150 .type = V4L2_DV_BT_656_1120, \
151 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
152 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
153 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
5ce65d1f 154 V4L2_DV_BT_STD_CEA861, \
cf038120
HV		 155 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
156 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 34) \
f00dc304
HV		 157}
158
159#define V4L2_DV_BT_CEA_1920X1080I50 { \
160 .type = V4L2_DV_BT_656_1120, \
161 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
162 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
163 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
5ce65d1f 164 V4L2_DV_BT_STD_CEA861, \
cf038120
HV		 165 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
166 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 20) \
f00dc304
HV		 167}
168
169#define V4L2_DV_BT_CEA_1920X1080P50 { \
170 .type = V4L2_DV_BT_656_1120, \
171 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
172 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
173 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
cf038120
HV		 174 V4L2_DV_BT_STD_CEA861, \
175 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 31) \
f00dc304
HV		 176}
177
178#define V4L2_DV_BT_CEA_1920X1080I60 { \
179 .type = V4L2_DV_BT_656_1120, \
180 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
181 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
182 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
183 V4L2_DV_BT_STD_CEA861, \
5ce65d1f 184 V4L2_DV_FL_CAN_REDUCE_FPS | \
cf038120
HV		 185 V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
186 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 5) \
f00dc304
HV		 187}
188
189#define V4L2_DV_BT_CEA_1920X1080P60 { \
190 .type = V4L2_DV_BT_656_1120, \
191 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
192 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
193 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
194 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
cf038120
HV		 195 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
196 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 16) \
f00dc304
HV		 197}
198
ebf9edd3
HV		 199#define V4L2_DV_BT_CEA_3840X2160P24 { \
200 .type = V4L2_DV_BT_656_1120, \
3020ca71
HV		 201 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
202 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
ebf9edd3 203 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
5ce65d1f 204 V4L2_DV_BT_STD_CEA861, \
cf038120
HV		 205 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
206 V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
207 { 0, 0 }, 93, 3) \
ebf9edd3
HV		 208}
209
210#define V4L2_DV_BT_CEA_3840X2160P25 { \
211 .type = V4L2_DV_BT_656_1120, \
3020ca71
HV		 212 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
213 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
ebf9edd3 214 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
cf038120
HV		 215 V4L2_DV_BT_STD_CEA861, \
216 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC | \
217 V4L2_DV_FL_HAS_HDMI_VIC, { 0, 0 }, 94, 2) \
ebf9edd3
HV		 218}
219
220#define V4L2_DV_BT_CEA_3840X2160P30 { \
221 .type = V4L2_DV_BT_656_1120, \
3020ca71
HV		 222 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
223 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
ebf9edd3 224 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
5ce65d1f 225 V4L2_DV_BT_STD_CEA861, \
cf038120
HV		 226 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
227 V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
228 { 0, 0 }, 95, 1) \
ebf9edd3
HV		 229}
230
231#define V4L2_DV_BT_CEA_3840X2160P50 { \
232 .type = V4L2_DV_BT_656_1120, \
3020ca71
HV		 233 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
234 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
ebf9edd3 235 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
cf038120
HV		 236 V4L2_DV_BT_STD_CEA861, \
237 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 96) \
ebf9edd3
HV		 238}
239
240#define V4L2_DV_BT_CEA_3840X2160P60 { \
241 .type = V4L2_DV_BT_656_1120, \
3020ca71
HV		 242 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
243 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
ebf9edd3 244 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
5ce65d1f 245 V4L2_DV_BT_STD_CEA861, \
cf038120
HV		 246 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
247 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 97) \
ebf9edd3
HV		 248}
249
250#define V4L2_DV_BT_CEA_4096X2160P24 { \
251 .type = V4L2_DV_BT_656_1120, \
3020ca71
HV		 252 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
253 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
ebf9edd3 254 297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
5ce65d1f 255 V4L2_DV_BT_STD_CEA861, \
cf038120
HV		 256 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
257 V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
258 { 0, 0 }, 98, 4) \
ebf9edd3
HV		 259}
260
261#define V4L2_DV_BT_CEA_4096X2160P25 { \
262 .type = V4L2_DV_BT_656_1120, \
3020ca71
HV		 263 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
264 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
ebf9edd3 265 297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
cf038120
HV		 266 V4L2_DV_BT_STD_CEA861, \
267 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 99) \
ebf9edd3
HV		 268}
269
270#define V4L2_DV_BT_CEA_4096X2160P30 { \
271 .type = V4L2_DV_BT_656_1120, \
3020ca71
HV		 272 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
273 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
ebf9edd3 274 297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
5ce65d1f 275 V4L2_DV_BT_STD_CEA861, \
cf038120
HV		 276 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
277 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 100) \
ebf9edd3
HV		 278}
279
280#define V4L2_DV_BT_CEA_4096X2160P50 { \
281 .type = V4L2_DV_BT_656_1120, \
3020ca71
HV		 282 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
283 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
ebf9edd3 284 594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
cf038120
HV		 285 V4L2_DV_BT_STD_CEA861, \
286 V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 101) \
ebf9edd3
HV		 287}
288
289#define V4L2_DV_BT_CEA_4096X2160P60 { \
290 .type = V4L2_DV_BT_656_1120, \
3020ca71
HV		 291 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
292 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
ebf9edd3 293 594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
5ce65d1f 294 V4L2_DV_BT_STD_CEA861, \
cf038120
HV		 295 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
296 V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 102) \
ebf9edd3
HV		 297}
298
f00dc304
HV		 299
300/* VESA Discrete Monitor Timings as per version 1.0, revision 12 */
301
302#define V4L2_DV_BT_DMT_640X350P85 { \
303 .type = V4L2_DV_BT_656_1120, \
304 V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
305 31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \
306 V4L2_DV_BT_STD_DMT, 0) \
307}
308
309#define V4L2_DV_BT_DMT_640X400P85 { \
310 .type = V4L2_DV_BT_656_1120, \
311 V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
312 31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \
313 V4L2_DV_BT_STD_DMT, 0) \
314}
315
316#define V4L2_DV_BT_DMT_720X400P85 { \
317 .type = V4L2_DV_BT_656_1120, \
318 V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
319 35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \
320 V4L2_DV_BT_STD_DMT, 0) \
321}
322
323/* VGA resolutions */
324#define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94
325
326#define V4L2_DV_BT_DMT_640X480P72 { \
327 .type = V4L2_DV_BT_656_1120, \
328 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
329 31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \
330 V4L2_DV_BT_STD_DMT, 0) \
331}
332
333#define V4L2_DV_BT_DMT_640X480P75 { \
334 .type = V4L2_DV_BT_656_1120, \
335 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
336 31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \
337 V4L2_DV_BT_STD_DMT, 0) \
338}
339
340#define V4L2_DV_BT_DMT_640X480P85 { \
341 .type = V4L2_DV_BT_656_1120, \
342 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
343 36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \
344 V4L2_DV_BT_STD_DMT, 0) \
345}
346
347/* SVGA resolutions */
348#define V4L2_DV_BT_DMT_800X600P56 { \
349 .type = V4L2_DV_BT_656_1120, \
350 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
351 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
352 36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \
353 V4L2_DV_BT_STD_DMT, 0) \
354}
355
356#define V4L2_DV_BT_DMT_800X600P60 { \
357 .type = V4L2_DV_BT_656_1120, \
358 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
359 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
360 40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \
361 V4L2_DV_BT_STD_DMT, 0) \
362}
363
364#define V4L2_DV_BT_DMT_800X600P72 { \
365 .type = V4L2_DV_BT_656_1120, \
366 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
367 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
368 50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \
369 V4L2_DV_BT_STD_DMT, 0) \
370}
371
372#define V4L2_DV_BT_DMT_800X600P75 { \
373 .type = V4L2_DV_BT_656_1120, \
374 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
375 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
376 49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \
377 V4L2_DV_BT_STD_DMT, 0) \
378}
379
380#define V4L2_DV_BT_DMT_800X600P85 { \
381 .type = V4L2_DV_BT_656_1120, \
382 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
383 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
384 56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \
385 V4L2_DV_BT_STD_DMT, 0) \
386}
387
388#define V4L2_DV_BT_DMT_800X600P120_RB { \
389 .type = V4L2_DV_BT_656_1120, \
390 V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \
391 73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \
392 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
393 V4L2_DV_FL_REDUCED_BLANKING) \
394}
395
396#define V4L2_DV_BT_DMT_848X480P60 { \
397 .type = V4L2_DV_BT_656_1120, \
398 V4L2_INIT_BT_TIMINGS(848, 480, 0, \
399 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
400 33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \
401 V4L2_DV_BT_STD_DMT, 0) \
402}
403
404#define V4L2_DV_BT_DMT_1024X768I43 { \
405 .type = V4L2_DV_BT_656_1120, \
406 V4L2_INIT_BT_TIMINGS(1024, 768, 1, \
407 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
408 44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \
409 V4L2_DV_BT_STD_DMT, 0) \
410}
411
412/* XGA resolutions */
413#define V4L2_DV_BT_DMT_1024X768P60 { \
414 .type = V4L2_DV_BT_656_1120, \
415 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
416 65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \
417 V4L2_DV_BT_STD_DMT, 0) \
418}
419
420#define V4L2_DV_BT_DMT_1024X768P70 { \
421 .type = V4L2_DV_BT_656_1120, \
422 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
423 75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \
424 V4L2_DV_BT_STD_DMT, 0) \
425}
426
427#define V4L2_DV_BT_DMT_1024X768P75 { \
428 .type = V4L2_DV_BT_656_1120, \
429 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
430 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
431 78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \
432 V4L2_DV_BT_STD_DMT, 0) \
433}
434
435#define V4L2_DV_BT_DMT_1024X768P85 { \
436 .type = V4L2_DV_BT_656_1120, \
437 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
438 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
439 94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \
440 V4L2_DV_BT_STD_DMT, 0) \
441}
442
443#define V4L2_DV_BT_DMT_1024X768P120_RB { \
444 .type = V4L2_DV_BT_656_1120, \
445 V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \
446 115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \
447 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
448 V4L2_DV_FL_REDUCED_BLANKING) \
449}
450
451/* XGA+ resolution */
452#define V4L2_DV_BT_DMT_1152X864P75 { \
453 .type = V4L2_DV_BT_656_1120, \
454 V4L2_INIT_BT_TIMINGS(1152, 864, 0, \
455 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
456 108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \
457 V4L2_DV_BT_STD_DMT, 0) \
458}
459
460#define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60
461
462/* WXGA resolutions */
463#define V4L2_DV_BT_DMT_1280X768P60_RB { \
464 .type = V4L2_DV_BT_656_1120, \
465 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
466 68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \
467 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
468 V4L2_DV_FL_REDUCED_BLANKING) \
469}
470
471#define V4L2_DV_BT_DMT_1280X768P60 { \
472 .type = V4L2_DV_BT_656_1120, \
473 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
474 79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \
475 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
476}
477
478#define V4L2_DV_BT_DMT_1280X768P75 { \
479 .type = V4L2_DV_BT_656_1120, \
480 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
481 102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \
482 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
483}
484
485#define V4L2_DV_BT_DMT_1280X768P85 { \
486 .type = V4L2_DV_BT_656_1120, \
487 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
488 117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \
489 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
490}
491
492#define V4L2_DV_BT_DMT_1280X768P120_RB { \
493 .type = V4L2_DV_BT_656_1120, \
494 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
495 140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \
496 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
497 V4L2_DV_FL_REDUCED_BLANKING) \
498}
499
500#define V4L2_DV_BT_DMT_1280X800P60_RB { \
501 .type = V4L2_DV_BT_656_1120, \
502 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
503 71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \
504 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
505 V4L2_DV_FL_REDUCED_BLANKING) \
506}
507
508#define V4L2_DV_BT_DMT_1280X800P60 { \
509 .type = V4L2_DV_BT_656_1120, \
510 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
511 83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \
512 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
513}
514
515#define V4L2_DV_BT_DMT_1280X800P75 { \
516 .type = V4L2_DV_BT_656_1120, \
517 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
518 106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \
519 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
520}
521
522#define V4L2_DV_BT_DMT_1280X800P85 { \
523 .type = V4L2_DV_BT_656_1120, \
524 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
525 122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \
526 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
527}
528
529#define V4L2_DV_BT_DMT_1280X800P120_RB { \
530 .type = V4L2_DV_BT_656_1120, \
531 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
532 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \
533 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
534 V4L2_DV_FL_REDUCED_BLANKING) \
535}
536
537#define V4L2_DV_BT_DMT_1280X960P60 { \
538 .type = V4L2_DV_BT_656_1120, \
539 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
540 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
541 108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \
542 V4L2_DV_BT_STD_DMT, 0) \
543}
544
545#define V4L2_DV_BT_DMT_1280X960P85 { \
546 .type = V4L2_DV_BT_656_1120, \
547 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
548 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
549 148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \
550 V4L2_DV_BT_STD_DMT, 0) \
551}
552
553#define V4L2_DV_BT_DMT_1280X960P120_RB { \
554 .type = V4L2_DV_BT_656_1120, \
555 V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
556 175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \
557 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
558 V4L2_DV_FL_REDUCED_BLANKING) \
559}
560
561/* SXGA resolutions */
562#define V4L2_DV_BT_DMT_1280X1024P60 { \
563 .type = V4L2_DV_BT_656_1120, \
564 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
565 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
566 108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \
567 V4L2_DV_BT_STD_DMT, 0) \
568}
569
570#define V4L2_DV_BT_DMT_1280X1024P75 { \
571 .type = V4L2_DV_BT_656_1120, \
572 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
573 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
574 135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \
575 V4L2_DV_BT_STD_DMT, 0) \
576}
577
578#define V4L2_DV_BT_DMT_1280X1024P85 { \
579 .type = V4L2_DV_BT_656_1120, \
580 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
581 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
582 157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \
583 V4L2_DV_BT_STD_DMT, 0) \
584}
585
586#define V4L2_DV_BT_DMT_1280X1024P120_RB { \
587 .type = V4L2_DV_BT_656_1120, \
588 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \
589 187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \
590 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
591 V4L2_DV_FL_REDUCED_BLANKING) \
592}
593
594#define V4L2_DV_BT_DMT_1360X768P60 { \
595 .type = V4L2_DV_BT_656_1120, \
596 V4L2_INIT_BT_TIMINGS(1360, 768, 0, \
597 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
598 85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \
599 V4L2_DV_BT_STD_DMT, 0) \
600}
601
602#define V4L2_DV_BT_DMT_1360X768P120_RB { \
603 .type = V4L2_DV_BT_656_1120, \
604 V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \
605 148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \
606 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
607 V4L2_DV_FL_REDUCED_BLANKING) \
608}
609
610#define V4L2_DV_BT_DMT_1366X768P60 { \
611 .type = V4L2_DV_BT_656_1120, \
612 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
613 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
614 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \
615 V4L2_DV_BT_STD_DMT, 0) \
616}
617
618#define V4L2_DV_BT_DMT_1366X768P60_RB { \
619 .type = V4L2_DV_BT_656_1120, \
620 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
621 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
622 72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \
623 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
624}
625
626/* SXGA+ resolutions */
627#define V4L2_DV_BT_DMT_1400X1050P60_RB { \
628 .type = V4L2_DV_BT_656_1120, \
629 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
630 101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \
631 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
632 V4L2_DV_FL_REDUCED_BLANKING) \
633}
634
635#define V4L2_DV_BT_DMT_1400X1050P60 { \
636 .type = V4L2_DV_BT_656_1120, \
637 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
638 121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \
639 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
640}
641
642#define V4L2_DV_BT_DMT_1400X1050P75 { \
643 .type = V4L2_DV_BT_656_1120, \
644 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
645 156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \
646 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
647}
648
649#define V4L2_DV_BT_DMT_1400X1050P85 { \
650 .type = V4L2_DV_BT_656_1120, \
651 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
652 179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \
653 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
654}
655
656#define V4L2_DV_BT_DMT_1400X1050P120_RB { \
657 .type = V4L2_DV_BT_656_1120, \
658 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
659 208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \
660 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
661 V4L2_DV_FL_REDUCED_BLANKING) \
662}
663
664/* WXGA+ resolutions */
665#define V4L2_DV_BT_DMT_1440X900P60_RB { \
666 .type = V4L2_DV_BT_656_1120, \
667 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
668 88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \
669 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
670 V4L2_DV_FL_REDUCED_BLANKING) \
671}
672
673#define V4L2_DV_BT_DMT_1440X900P60 { \
674 .type = V4L2_DV_BT_656_1120, \
675 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
676 106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \
677 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
678}
679
680#define V4L2_DV_BT_DMT_1440X900P75 { \
681 .type = V4L2_DV_BT_656_1120, \
682 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
683 136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \
684 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
685}
686
687#define V4L2_DV_BT_DMT_1440X900P85 { \
688 .type = V4L2_DV_BT_656_1120, \
689 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
690 157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \
691 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
692}
693
694#define V4L2_DV_BT_DMT_1440X900P120_RB { \
695 .type = V4L2_DV_BT_656_1120, \
696 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
697 182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \
698 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
699 V4L2_DV_FL_REDUCED_BLANKING) \
700}
701
702#define V4L2_DV_BT_DMT_1600X900P60_RB { \
703 .type = V4L2_DV_BT_656_1120, \
704 V4L2_INIT_BT_TIMINGS(1600, 900, 0, \
705 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
706 108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \
707 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
708}
709
710/* UXGA resolutions */
711#define V4L2_DV_BT_DMT_1600X1200P60 { \
712 .type = V4L2_DV_BT_656_1120, \
713 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
714 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
715 162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
716 V4L2_DV_BT_STD_DMT, 0) \
717}
718
719#define V4L2_DV_BT_DMT_1600X1200P65 { \
720 .type = V4L2_DV_BT_656_1120, \
721 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
722 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
723 175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
724 V4L2_DV_BT_STD_DMT, 0) \
725}
726
727#define V4L2_DV_BT_DMT_1600X1200P70 { \
728 .type = V4L2_DV_BT_656_1120, \
729 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
730 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
731 189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
732 V4L2_DV_BT_STD_DMT, 0) \
733}
734
735#define V4L2_DV_BT_DMT_1600X1200P75 { \
736 .type = V4L2_DV_BT_656_1120, \
737 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
738 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
739 202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
740 V4L2_DV_BT_STD_DMT, 0) \
741}
742
743#define V4L2_DV_BT_DMT_1600X1200P85 { \
744 .type = V4L2_DV_BT_656_1120, \
745 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
746 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
747 229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
748 V4L2_DV_BT_STD_DMT, 0) \
749}
750
751#define V4L2_DV_BT_DMT_1600X1200P120_RB { \
752 .type = V4L2_DV_BT_656_1120, \
753 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
754 268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \
755 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
756 V4L2_DV_FL_REDUCED_BLANKING) \
757}
758
759/* WSXGA+ resolutions */
760#define V4L2_DV_BT_DMT_1680X1050P60_RB { \
761 .type = V4L2_DV_BT_656_1120, \
762 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
763 119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \
764 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
765 V4L2_DV_FL_REDUCED_BLANKING) \
766}
767
768#define V4L2_DV_BT_DMT_1680X1050P60 { \
769 .type = V4L2_DV_BT_656_1120, \
770 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
771 146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \
772 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
773}
774
775#define V4L2_DV_BT_DMT_1680X1050P75 { \
776 .type = V4L2_DV_BT_656_1120, \
777 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
778 187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \
779 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
780}
781
782#define V4L2_DV_BT_DMT_1680X1050P85 { \
783 .type = V4L2_DV_BT_656_1120, \
784 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
785 214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \
786 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
787}
788
789#define V4L2_DV_BT_DMT_1680X1050P120_RB { \
790 .type = V4L2_DV_BT_656_1120, \
791 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
792 245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \
793 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
794 V4L2_DV_FL_REDUCED_BLANKING) \
795}
796
797#define V4L2_DV_BT_DMT_1792X1344P60 { \
798 .type = V4L2_DV_BT_656_1120, \
799 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
800 204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \
801 V4L2_DV_BT_STD_DMT, 0) \
802}
803
804#define V4L2_DV_BT_DMT_1792X1344P75 { \
805 .type = V4L2_DV_BT_656_1120, \
806 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
807 261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \
808 V4L2_DV_BT_STD_DMT, 0) \
809}
810
811#define V4L2_DV_BT_DMT_1792X1344P120_RB { \
812 .type = V4L2_DV_BT_656_1120, \
813 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \
814 333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \
815 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
816 V4L2_DV_FL_REDUCED_BLANKING) \
817}
818
819#define V4L2_DV_BT_DMT_1856X1392P60 { \
820 .type = V4L2_DV_BT_656_1120, \
821 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
822 218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \
823 V4L2_DV_BT_STD_DMT, 0) \
824}
825
826#define V4L2_DV_BT_DMT_1856X1392P75 { \
827 .type = V4L2_DV_BT_656_1120, \
828 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
829 288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \
830 V4L2_DV_BT_STD_DMT, 0) \
831}
832
833#define V4L2_DV_BT_DMT_1856X1392P120_RB { \
834 .type = V4L2_DV_BT_656_1120, \
835 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \
836 356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \
837 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
838 V4L2_DV_FL_REDUCED_BLANKING) \
839}
840
841#define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60
842
843/* WUXGA resolutions */
844#define V4L2_DV_BT_DMT_1920X1200P60_RB { \
845 .type = V4L2_DV_BT_656_1120, \
846 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
847 154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \
848 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
849 V4L2_DV_FL_REDUCED_BLANKING) \
850}
851
852#define V4L2_DV_BT_DMT_1920X1200P60 { \
853 .type = V4L2_DV_BT_656_1120, \
854 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
855 193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \
856 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
857}
858
859#define V4L2_DV_BT_DMT_1920X1200P75 { \
860 .type = V4L2_DV_BT_656_1120, \
861 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
862 245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \
863 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
864}
865
866#define V4L2_DV_BT_DMT_1920X1200P85 { \
867 .type = V4L2_DV_BT_656_1120, \
868 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
869 281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \
870 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
871}
872
873#define V4L2_DV_BT_DMT_1920X1200P120_RB { \
874 .type = V4L2_DV_BT_656_1120, \
875 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
876 317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \
877 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
878 V4L2_DV_FL_REDUCED_BLANKING) \
879}
880
881#define V4L2_DV_BT_DMT_1920X1440P60 { \
882 .type = V4L2_DV_BT_656_1120, \
883 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
884 234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \
885 V4L2_DV_BT_STD_DMT, 0) \
886}
887
888#define V4L2_DV_BT_DMT_1920X1440P75 { \
889 .type = V4L2_DV_BT_656_1120, \
890 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
891 297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \
892 V4L2_DV_BT_STD_DMT, 0) \
893}
894
895#define V4L2_DV_BT_DMT_1920X1440P120_RB { \
896 .type = V4L2_DV_BT_656_1120, \
897 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \
898 380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \
899 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
900 V4L2_DV_FL_REDUCED_BLANKING) \
901}
902
903#define V4L2_DV_BT_DMT_2048X1152P60_RB { \
904 .type = V4L2_DV_BT_656_1120, \
905 V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \
906 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
907 162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \
908 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
909}
910
911/* WQXGA resolutions */
912#define V4L2_DV_BT_DMT_2560X1600P60_RB { \
913 .type = V4L2_DV_BT_656_1120, \
914 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
915 268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \
916 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
917 V4L2_DV_FL_REDUCED_BLANKING) \
918}
919
920#define V4L2_DV_BT_DMT_2560X1600P60 { \
921 .type = V4L2_DV_BT_656_1120, \
922 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
923 348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \
924 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
925}
926
927#define V4L2_DV_BT_DMT_2560X1600P75 { \
928 .type = V4L2_DV_BT_656_1120, \
929 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
930 443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \
931 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
932}
933
934#define V4L2_DV_BT_DMT_2560X1600P85 { \
935 .type = V4L2_DV_BT_656_1120, \
936 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
937 505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \
938 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
939}
940
941#define V4L2_DV_BT_DMT_2560X1600P120_RB { \
942 .type = V4L2_DV_BT_656_1120, \
943 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
944 552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \
945 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
946 V4L2_DV_FL_REDUCED_BLANKING) \
947}
948
a1d16e0f
HV		 949/* 4K resolutions */
950#define V4L2_DV_BT_DMT_4096X2160P60_RB { \
951 .type = V4L2_DV_BT_656_1120, \
952 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
953 556744000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
954 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
955 V4L2_DV_FL_REDUCED_BLANKING) \
956}
957
958#define V4L2_DV_BT_DMT_4096X2160P59_94_RB { \
959 .type = V4L2_DV_BT_656_1120, \
960 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
961 556188000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
962 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
963 V4L2_DV_FL_REDUCED_BLANKING) \
964}
965
7389e6ef
CAC		 966/* SDI timings definitions */
967
968/* SMPTE-125M */
969#define V4L2_DV_BT_SDI_720X487I60 { \
970 .type = V4L2_DV_BT_656_1120, \
971 V4L2_INIT_BT_TIMINGS(720, 487, 1, \
972 V4L2_DV_HSYNC_POS_POL, \
973 13500000, 16, 121, 0, 0, 19, 0, 0, 19, 0, \
974 V4L2_DV_BT_STD_SDI, \
975 V4L2_DV_FL_FIRST_FIELD_EXTRA_LINE) \
976}
977
f00dc304 978#endif
Ubuntu Artful kernel mirror