[mirror_ubuntu-focal-kernel.git] / include / uapi / rdma / mlx5-abi.h

/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
/*
 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX5_ABI_USER_H
#define MLX5_ABI_USER_H

#include <linux/types.h>
#include <linux/if_ether.h>	/* For ETH_ALEN. */

enum {
	MLX5_QP_FLAG_SIGNATURE		= 1 << 0,
	MLX5_QP_FLAG_SCATTER_CQE	= 1 << 1,
};

enum {
	MLX5_SRQ_FLAG_SIGNATURE		= 1 << 0,
};

enum {
	MLX5_WQ_FLAG_SIGNATURE		= 1 << 0,
};

/* Increment this value if any changes that break userspace ABI
 * compatibility are made.
 */
#define MLX5_IB_UVERBS_ABI_VERSION	1

/* Make sure that all structs defined in this file remain laid out so
 * that they pack the same way on 32-bit and 64-bit architectures (to
 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
 * In particular do not use pointer types -- pass pointers in __u64
 * instead.
 */

struct mlx5_ib_alloc_ucontext_req {
	__u32	total_num_bfregs;
	__u32	num_low_latency_bfregs;
};

enum mlx5_lib_caps {
	MLX5_LIB_CAP_4K_UAR	= (__u64)1 << 0,
};

struct mlx5_ib_alloc_ucontext_req_v2 {
	__u32	total_num_bfregs;
	__u32	num_low_latency_bfregs;
	__u32	flags;
	__u32	comp_mask;
	__u8	max_cqe_version;
	__u8	reserved0;
	__u16	reserved1;
	__u32	reserved2;
	__u64	lib_caps;
};

enum mlx5_ib_alloc_ucontext_resp_mask {
	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
};

enum mlx5_user_cmds_supp_uhw {
	MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
	MLX5_USER_CMDS_SUPP_UHW_CREATE_AH    = 1 << 1,
};

/* The eth_min_inline response value is set to off-by-one vs the FW
 * returned value to allow user-space to deal with older kernels.
 */
enum mlx5_user_inline_mode {
	MLX5_USER_INLINE_MODE_NA,
	MLX5_USER_INLINE_MODE_NONE,
	MLX5_USER_INLINE_MODE_L2,
	MLX5_USER_INLINE_MODE_IP,
	MLX5_USER_INLINE_MODE_TCP_UDP,
};

struct mlx5_ib_alloc_ucontext_resp {
	__u32	qp_tab_size;
	__u32	bf_reg_size;
	__u32	tot_bfregs;
	__u32	cache_line_size;
	__u16	max_sq_desc_sz;
	__u16	max_rq_desc_sz;
	__u32	max_send_wqebb;
	__u32	max_recv_wr;
	__u32	max_srq_recv_wr;
	__u16	num_ports;
	__u16	reserved1;
	__u32	comp_mask;
	__u32	response_length;
	__u8	cqe_version;
	__u8	cmds_supp_uhw;
	__u8	eth_min_inline;
	__u8	reserved2;
	__u64	hca_core_clock_offset;
	__u32	log_uar_size;
	__u32	num_uars_per_page;
};

struct mlx5_ib_alloc_pd_resp {
	__u32	pdn;
};

struct mlx5_ib_tso_caps {
	__u32 max_tso; /* Maximum tso payload size in bytes */

	/* Corresponding bit will be set if qp type from
	 * 'enum ib_qp_type' is supported, e.g.
	 * supported_qpts |= 1 << IB_QPT_UD
	 */
	__u32 supported_qpts;
};

struct mlx5_ib_rss_caps {
	__u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
	__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
	__u8 reserved[7];
};

enum mlx5_ib_cqe_comp_res_format {
	MLX5_IB_CQE_RES_FORMAT_HASH	= 1 << 0,
	MLX5_IB_CQE_RES_FORMAT_CSUM	= 1 << 1,
	MLX5_IB_CQE_RES_RESERVED	= 1 << 2,
};

struct mlx5_ib_cqe_comp_caps {
	__u32 max_num;
	__u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
};

struct mlx5_packet_pacing_caps {
	__u32 qp_rate_limit_min;
	__u32 qp_rate_limit_max; /* In kpbs */

	/* Corresponding bit will be set if qp type from
	 * 'enum ib_qp_type' is supported, e.g.
	 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
	 */
	__u32 supported_qpts;
	__u32 reserved;
};

enum mlx5_ib_mpw_caps {
	MPW_RESERVED		= 1 << 0,
	MLX5_IB_ALLOW_MPW	= 1 << 1,
	MLX5_IB_SUPPORT_EMPW	= 1 << 2,
};

enum mlx5_ib_sw_parsing_offloads {
	MLX5_IB_SW_PARSING = 1 << 0,
	MLX5_IB_SW_PARSING_CSUM = 1 << 1,
	MLX5_IB_SW_PARSING_LSO = 1 << 2,
};

struct mlx5_ib_sw_parsing_caps {
	__u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */

	/* Corresponding bit will be set if qp type from
	 * 'enum ib_qp_type' is supported, e.g.
	 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
	 */
	__u32 supported_qpts;
};

struct mlx5_ib_query_device_resp {
	__u32	comp_mask;
	__u32	response_length;
	struct	mlx5_ib_tso_caps tso_caps;
	struct	mlx5_ib_rss_caps rss_caps;
	struct	mlx5_ib_cqe_comp_caps cqe_comp_caps;
	struct	mlx5_packet_pacing_caps packet_pacing_caps;
	__u32	mlx5_ib_support_multi_pkt_send_wqes;
	__u32	reserved;
	struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
};

struct mlx5_ib_create_cq {
	__u64	buf_addr;
	__u64	db_addr;
	__u32	cqe_size;
	__u8    cqe_comp_en;
	__u8    cqe_comp_res_format;
	__u16	reserved; /* explicit padding (optional on i386) */
};

struct mlx5_ib_create_cq_resp {
	__u32	cqn;
	__u32	reserved;
};

struct mlx5_ib_resize_cq {
	__u64	buf_addr;
	__u16	cqe_size;
	__u16	reserved0;
	__u32	reserved1;
};

struct mlx5_ib_create_srq {
	__u64	buf_addr;
	__u64	db_addr;
	__u32	flags;
	__u32	reserved0; /* explicit padding (optional on i386) */
	__u32	uidx;
	__u32	reserved1;
};

struct mlx5_ib_create_srq_resp {
	__u32	srqn;
	__u32	reserved;
};

struct mlx5_ib_create_qp {
	__u64	buf_addr;
	__u64	db_addr;
	__u32	sq_wqe_count;
	__u32	rq_wqe_count;
	__u32	rq_wqe_shift;
	__u32	flags;
	__u32	uidx;
	__u32	reserved0;
	__u64	sq_buf_addr;
};

/* RX Hash function flags */
enum mlx5_rx_hash_function_flags {
	MLX5_RX_HASH_FUNC_TOEPLITZ	= 1 << 0,
};

/*
 * RX Hash flags, these flags allows to set which incoming packet's field should
 * participates in RX Hash. Each flag represent certain packet's field,
 * when the flag is set the field that is represented by the flag will
 * participate in RX Hash calculation.
 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
 * and *TCP and *UDP flags can't be enabled together on the same QP.
*/
enum mlx5_rx_hash_fields {
	MLX5_RX_HASH_SRC_IPV4	= 1 << 0,
	MLX5_RX_HASH_DST_IPV4	= 1 << 1,
	MLX5_RX_HASH_SRC_IPV6	= 1 << 2,
	MLX5_RX_HASH_DST_IPV6	= 1 << 3,
	MLX5_RX_HASH_SRC_PORT_TCP	= 1 << 4,
	MLX5_RX_HASH_DST_PORT_TCP	= 1 << 5,
	MLX5_RX_HASH_SRC_PORT_UDP	= 1 << 6,
	MLX5_RX_HASH_DST_PORT_UDP	= 1 << 7
};

struct mlx5_ib_create_qp_rss {
	__u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
	__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
	__u8 rx_key_len; /* valid only for Toeplitz */
	__u8 reserved[6];
	__u8 rx_hash_key[128]; /* valid only for Toeplitz */
	__u32   comp_mask;
	__u32   reserved1;
};

struct mlx5_ib_create_qp_resp {
	__u32	bfreg_index;
};

struct mlx5_ib_alloc_mw {
	__u32	comp_mask;
	__u8	num_klms;
	__u8	reserved1;
	__u16	reserved2;
};

struct mlx5_ib_create_wq {
	__u64   buf_addr;
	__u64   db_addr;
	__u32   rq_wqe_count;
	__u32   rq_wqe_shift;
	__u32   user_index;
	__u32   flags;
	__u32   comp_mask;
	__u32   reserved;
};

struct mlx5_ib_create_ah_resp {
	__u32	response_length;
	__u8	dmac[ETH_ALEN];
	__u8	reserved[6];
};

struct mlx5_ib_create_wq_resp {
	__u32	response_length;
	__u32	reserved;
};

struct mlx5_ib_create_rwq_ind_tbl_resp {
	__u32	response_length;
	__u32	reserved;
};

struct mlx5_ib_modify_wq {
	__u32	comp_mask;
	__u32	reserved;
};
#endif /* MLX5_ABI_USER_H */
Commit	Line	Data
e2be04c7	1	/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
e126ba97	2	/*
6cf0a15f	3	* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97 EC	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the
	9	* OpenIB.org BSD license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or
	12	* without modification, are permitted provided that the following
	13	* conditions are met:
	14	*
	15	* - Redistributions of source code must retain the above
	16	* copyright notice, this list of conditions and the following
	17	* disclaimer.
	18	*
	19	* - Redistributions in binary form must reproduce the above
	20	* copyright notice, this list of conditions and the following
	21	* disclaimer in the documentation and/or other materials
	22	* provided with the distribution.
	23	*
	24	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	25	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	26	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	27	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	28	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	29	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	30	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	31	* SOFTWARE.
	32	*/
	33
3085e29e LR	34	#ifndef MLX5_ABI_USER_H
3085e29e LR	35	#define MLX5_ABI_USER_H
e126ba97 EC	36
e126ba97 EC	37	#include <linux/types.h>
812755d6	38	#include <linux/if_ether.h> /* For ETH_ALEN. */
e126ba97 EC	39
	40	enum {
	41	MLX5_QP_FLAG_SIGNATURE = 1 << 0,
	42	MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
	43	};
	44
	45	enum {
	46	MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
	47	};
	48
79b20a6c YH	49	enum {
	50	MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
	51	};
	52
e126ba97 EC	53	/* Increment this value if any changes that break userspace ABI
	54	* compatibility are made.
	55	*/
	56	#define MLX5_IB_UVERBS_ABI_VERSION 1
	57
	58	/* Make sure that all structs defined in this file remain laid out so
	59	* that they pack the same way on 32-bit and 64-bit architectures (to
	60	* avoid incompatibility between 32-bit userspace and 64-bit kernels).
	61	* In particular do not use pointer types -- pass pointers in __u64
	62	* instead.
	63	*/
	64
	65	struct mlx5_ib_alloc_ucontext_req {
2f5ff264 EC	66	__u32 total_num_bfregs;
2f5ff264 EC	67	__u32 num_low_latency_bfregs;
e126ba97 EC	68	};
e126ba97 EC	69
30aa60b3	70	enum mlx5_lib_caps {
812755d6	71	MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0,
30aa60b3 EC	72	};
30aa60b3 EC	73
78c0f98c	74	struct mlx5_ib_alloc_ucontext_req_v2 {
2f5ff264 EC	75	__u32 total_num_bfregs;
2f5ff264 EC	76	__u32 num_low_latency_bfregs;
78c0f98c	77	__u32 flags;
b368d7cb	78	__u32 comp_mask;
f72300c5 HA	79	__u8 max_cqe_version;
	80	__u8 reserved0;
	81	__u16 reserved1;
	82	__u32 reserved2;
30aa60b3	83	__u64 lib_caps;
b368d7cb MB	84	};
	85
	86	enum mlx5_ib_alloc_ucontext_resp_mask {
	87	MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
78c0f98c EC	88	};
78c0f98c EC	89
402ca536 BW	90	enum mlx5_user_cmds_supp_uhw {
402ca536 BW	91	MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
6ad279c5	92	MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
402ca536 BW	93	};
402ca536 BW	94
78984898 OG	95	/* The eth_min_inline response value is set to off-by-one vs the FW
	96	* returned value to allow user-space to deal with older kernels.
	97	*/
	98	enum mlx5_user_inline_mode {
	99	MLX5_USER_INLINE_MODE_NA,
	100	MLX5_USER_INLINE_MODE_NONE,
	101	MLX5_USER_INLINE_MODE_L2,
	102	MLX5_USER_INLINE_MODE_IP,
	103	MLX5_USER_INLINE_MODE_TCP_UDP,
	104	};
	105
e126ba97 EC	106	struct mlx5_ib_alloc_ucontext_resp {
	107	__u32 qp_tab_size;
	108	__u32 bf_reg_size;
2f5ff264	109	__u32 tot_bfregs;
e126ba97 EC	110	__u32 cache_line_size;
	111	__u16 max_sq_desc_sz;
	112	__u16 max_rq_desc_sz;
	113	__u32 max_send_wqebb;
	114	__u32 max_recv_wr;
	115	__u32 max_srq_recv_wr;
	116	__u16 num_ports;
b368d7cb MB	117	__u16 reserved1;
	118	__u32 comp_mask;
	119	__u32 response_length;
f72300c5	120	__u8 cqe_version;
402ca536	121	__u8 cmds_supp_uhw;
78984898 OG	122	__u8 eth_min_inline;
78984898 OG	123	__u8 reserved2;
b368d7cb	124	__u64 hca_core_clock_offset;
30aa60b3 EC	125	__u32 log_uar_size;
30aa60b3 EC	126	__u32 num_uars_per_page;
e126ba97 EC	127	};
	128
	129	struct mlx5_ib_alloc_pd_resp {
	130	__u32 pdn;
	131	};
	132
402ca536 BW	133	struct mlx5_ib_tso_caps {
	134	__u32 max_tso; /* Maximum tso payload size in bytes */
	135
	136	/* Corresponding bit will be set if qp type from
	137	* 'enum ib_qp_type' is supported, e.g.
	138	* supported_qpts \|= 1 << IB_QPT_UD
	139	*/
	140	__u32 supported_qpts;
	141	};
	142
31f69a82 YH	143	struct mlx5_ib_rss_caps {
	144	__u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
	145	__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
	146	__u8 reserved[7];
	147	};
	148
7e43a2a5 BW	149	enum mlx5_ib_cqe_comp_res_format {
	150	MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
	151	MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
	152	MLX5_IB_CQE_RES_RESERVED = 1 << 2,
	153	};
	154
	155	struct mlx5_ib_cqe_comp_caps {
	156	__u32 max_num;
	157	__u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
	158	};
	159
d949167d BW	160	struct mlx5_packet_pacing_caps {
	161	__u32 qp_rate_limit_min;
	162	__u32 qp_rate_limit_max; /* In kpbs */
	163
	164	/* Corresponding bit will be set if qp type from
	165	* 'enum ib_qp_type' is supported, e.g.
	166	* supported_qpts \|= 1 << IB_QPT_RAW_PACKET
	167	*/
	168	__u32 supported_qpts;
	169	__u32 reserved;
	170	};
	171
795b609c BW	172	enum mlx5_ib_mpw_caps {
	173	MPW_RESERVED = 1 << 0,
	174	MLX5_IB_ALLOW_MPW = 1 << 1,
050da902	175	MLX5_IB_SUPPORT_EMPW = 1 << 2,
795b609c BW	176	};
795b609c BW	177
96dc3fc5 NO	178	enum mlx5_ib_sw_parsing_offloads {
	179	MLX5_IB_SW_PARSING = 1 << 0,
	180	MLX5_IB_SW_PARSING_CSUM = 1 << 1,
	181	MLX5_IB_SW_PARSING_LSO = 1 << 2,
	182	};
	183
	184	struct mlx5_ib_sw_parsing_caps {
	185	__u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */
	186
	187	/* Corresponding bit will be set if qp type from
	188	* 'enum ib_qp_type' is supported, e.g.
	189	* supported_qpts \|= 1 << IB_QPT_RAW_PACKET
	190	*/
	191	__u32 supported_qpts;
	192	};
	193
402ca536 BW	194	struct mlx5_ib_query_device_resp {
	195	__u32 comp_mask;
	196	__u32 response_length;
	197	struct mlx5_ib_tso_caps tso_caps;
31f69a82	198	struct mlx5_ib_rss_caps rss_caps;
7e43a2a5	199	struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
d949167d	200	struct mlx5_packet_pacing_caps packet_pacing_caps;
191ded4a BW	201	__u32 mlx5_ib_support_multi_pkt_send_wqes;
191ded4a BW	202	__u32 reserved;
96dc3fc5	203	struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
402ca536 BW	204	};
402ca536 BW	205
e126ba97 EC	206	struct mlx5_ib_create_cq {
	207	__u64 buf_addr;
	208	__u64 db_addr;
	209	__u32 cqe_size;
1cbe6fc8 BW	210	__u8 cqe_comp_en;
	211	__u8 cqe_comp_res_format;
	212	__u16 reserved; /* explicit padding (optional on i386) */
e126ba97 EC	213	};
	214
	215	struct mlx5_ib_create_cq_resp {
	216	__u32 cqn;
	217	__u32 reserved;
	218	};
	219
	220	struct mlx5_ib_resize_cq {
	221	__u64 buf_addr;
bde51583 EC	222	__u16 cqe_size;
	223	__u16 reserved0;
	224	__u32 reserved1;
e126ba97 EC	225	};
	226
	227	struct mlx5_ib_create_srq {
	228	__u64 buf_addr;
	229	__u64 db_addr;
	230	__u32 flags;
cfb5e088 HA	231	__u32 reserved0; /* explicit padding (optional on i386) */
	232	__u32 uidx;
	233	__u32 reserved1;
e126ba97 EC	234	};
	235
	236	struct mlx5_ib_create_srq_resp {
	237	__u32 srqn;
	238	__u32 reserved;
	239	};
	240
	241	struct mlx5_ib_create_qp {
	242	__u64 buf_addr;
	243	__u64 db_addr;
	244	__u32 sq_wqe_count;
	245	__u32 rq_wqe_count;
	246	__u32 rq_wqe_shift;
	247	__u32 flags;
cfb5e088 HA	248	__u32 uidx;
cfb5e088 HA	249	__u32 reserved0;
0fb2ed66	250	__u64 sq_buf_addr;
e126ba97 EC	251	};
e126ba97 EC	252
28d61370 YH	253	/* RX Hash function flags */
	254	enum mlx5_rx_hash_function_flags {
	255	MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
	256	};
	257
	258	/*
	259	* RX Hash flags, these flags allows to set which incoming packet's field should
	260	* participates in RX Hash. Each flag represent certain packet's field,
	261	* when the flag is set the field that is represented by the flag will
	262	* participate in RX Hash calculation.
	263	* Note: IPV4 and IPV6 flags can't be enabled together on the same QP
	264	* and TCP and UDP flags can't be enabled together on the same QP.
	265	*/
	266	enum mlx5_rx_hash_fields {
	267	MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
	268	MLX5_RX_HASH_DST_IPV4 = 1 << 1,
	269	MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
	270	MLX5_RX_HASH_DST_IPV6 = 1 << 3,
	271	MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
	272	MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
	273	MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
	274	MLX5_RX_HASH_DST_PORT_UDP = 1 << 7
	275	};
	276
	277	struct mlx5_ib_create_qp_rss {
	278	__u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
	279	__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
	280	__u8 rx_key_len; /* valid only for Toeplitz */
	281	__u8 reserved[6];
	282	__u8 rx_hash_key[128]; /* valid only for Toeplitz */
	283	__u32 comp_mask;
	284	__u32 reserved1;
	285	};
	286
e126ba97	287	struct mlx5_ib_create_qp_resp {
2f5ff264	288	__u32 bfreg_index;
e126ba97	289	};
cfb5e088	290
d2370e0a MB	291	struct mlx5_ib_alloc_mw {
	292	__u32 comp_mask;
	293	__u8 num_klms;
	294	__u8 reserved1;
	295	__u16 reserved2;
	296	};
	297
79b20a6c YH	298	struct mlx5_ib_create_wq {
	299	__u64 buf_addr;
	300	__u64 db_addr;
	301	__u32 rq_wqe_count;
	302	__u32 rq_wqe_shift;
	303	__u32 user_index;
	304	__u32 flags;
	305	__u32 comp_mask;
	306	__u32 reserved;
	307	};
	308
5097e71f MS	309	struct mlx5_ib_create_ah_resp {
	310	__u32 response_length;
	311	__u8 dmac[ETH_ALEN];
	312	__u8 reserved[6];
	313	};
	314
79b20a6c YH	315	struct mlx5_ib_create_wq_resp {
	316	__u32 response_length;
	317	__u32 reserved;
	318	};
	319
c5f90929 YH	320	struct mlx5_ib_create_rwq_ind_tbl_resp {
	321	__u32 response_length;
	322	__u32 reserved;
	323	};
	324
79b20a6c YH	325	struct mlx5_ib_modify_wq {
	326	__u32 comp_mask;
	327	__u32 reserved;
	328	};
3085e29e	329	#endif /* MLX5_ABI_USER_H */