[mirror_ubuntu-bionic-kernel.git] / include / video / imx-ipu-v3.h

/*
 * Copyright 2005-2009 Freescale Semiconductor, Inc.
 *
 * The code contained herein is licensed under the GNU Lesser General
 * Public License.  You may obtain a copy of the GNU Lesser General
 * Public License Version 2.1 or later at the following locations:
 *
 * http://www.opensource.org/licenses/lgpl-license.html
 * http://www.gnu.org/copyleft/lgpl.html
 */

#ifndef __DRM_IPU_H__
#define __DRM_IPU_H__

#include <linux/types.h>
#include <linux/videodev2.h>
#include <linux/bitmap.h>
#include <linux/fb.h>
#include <linux/of.h>
#include <media/v4l2-mediabus.h>
#include <video/videomode.h>

struct ipu_soc;

enum ipuv3_type {
	IPUV3EX,
	IPUV3M,
	IPUV3H,
};

#define IPU_PIX_FMT_GBR24	v4l2_fourcc('G', 'B', 'R', '3')

/*
 * Bitfield of Display Interface signal polarities.
 */
struct ipu_di_signal_cfg {
	unsigned data_pol:1;	/* true = inverted */
	unsigned clk_pol:1;	/* true = rising edge */
	unsigned enable_pol:1;

	struct videomode mode;

	u32 bus_format;
	u32 v_to_h_sync;

#define IPU_DI_CLKMODE_SYNC	(1 << 0)
#define IPU_DI_CLKMODE_EXT	(1 << 1)
	unsigned long clkflags;

	u8 hsync_pin;
	u8 vsync_pin;
};

/*
 * Enumeration of CSI destinations
 */
enum ipu_csi_dest {
	IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
	IPU_CSI_DEST_IC,	/* to Image Converter */
	IPU_CSI_DEST_VDIC,  /* to VDIC */
};

/*
 * Enumeration of IPU rotation modes
 */
#define IPU_ROT_BIT_VFLIP (1 << 0)
#define IPU_ROT_BIT_HFLIP (1 << 1)
#define IPU_ROT_BIT_90    (1 << 2)

enum ipu_rotate_mode {
	IPU_ROTATE_NONE = 0,
	IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFLIP,
	IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HFLIP,
	IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
	IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90,
	IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP),
	IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_HFLIP),
	IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 |
			      IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
};

/* 90-degree rotations require the IRT unit */
#define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT_BIT_90) != 0)

enum ipu_color_space {
	IPUV3_COLORSPACE_RGB,
	IPUV3_COLORSPACE_YUV,
	IPUV3_COLORSPACE_UNKNOWN,
};

/*
 * Enumeration of VDI MOTION select
 */
enum ipu_motion_sel {
	MOTION_NONE = 0,
	LOW_MOTION,
	MED_MOTION,
	HIGH_MOTION,
};

struct ipuv3_channel;

enum ipu_channel_irq {
	IPU_IRQ_EOF = 0,
	IPU_IRQ_NFACK = 64,
	IPU_IRQ_NFB4EOF = 128,
	IPU_IRQ_EOS = 192,
};

/*
 * Enumeration of IDMAC channels
 */
#define IPUV3_CHANNEL_CSI0			 0
#define IPUV3_CHANNEL_CSI1			 1
#define IPUV3_CHANNEL_CSI2			 2
#define IPUV3_CHANNEL_CSI3			 3
#define IPUV3_CHANNEL_VDI_MEM_IC_VF		 5
/*
 * NOTE: channels 6,7 are unused in the IPU and are not IDMAC channels,
 * but the direct CSI->VDI linking is handled the same way as IDMAC
 * channel linking in the FSU via the IPU_FS_PROC_FLOW registers, so
 * these channel names are used to support the direct CSI->VDI link.
 */
#define IPUV3_CHANNEL_CSI_DIRECT		 6
#define IPUV3_CHANNEL_CSI_VDI_PREV		 7
#define IPUV3_CHANNEL_MEM_VDI_PREV		 8
#define IPUV3_CHANNEL_MEM_VDI_CUR		 9
#define IPUV3_CHANNEL_MEM_VDI_NEXT		10
#define IPUV3_CHANNEL_MEM_IC_PP			11
#define IPUV3_CHANNEL_MEM_IC_PRP_VF		12
#define IPUV3_CHANNEL_VDI_MEM_RECENT		13
#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF		14
#define IPUV3_CHANNEL_G_MEM_IC_PP		15
#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA	17
#define IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA		18
#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA	19
#define IPUV3_CHANNEL_IC_PRP_ENC_MEM		20
#define IPUV3_CHANNEL_IC_PRP_VF_MEM		21
#define IPUV3_CHANNEL_IC_PP_MEM			22
#define IPUV3_CHANNEL_MEM_BG_SYNC		23
#define IPUV3_CHANNEL_MEM_BG_ASYNC		24
#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB	25
#define IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB	26
#define IPUV3_CHANNEL_MEM_FG_SYNC		27
#define IPUV3_CHANNEL_MEM_DC_SYNC		28
#define IPUV3_CHANNEL_MEM_FG_ASYNC		29
#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA		31
#define IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA	33
#define IPUV3_CHANNEL_DC_MEM_READ		40
#define IPUV3_CHANNEL_MEM_DC_ASYNC		41
#define IPUV3_CHANNEL_MEM_DC_COMMAND		42
#define IPUV3_CHANNEL_MEM_DC_COMMAND2		43
#define IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK	44
#define IPUV3_CHANNEL_MEM_ROT_ENC		45
#define IPUV3_CHANNEL_MEM_ROT_VF		46
#define IPUV3_CHANNEL_MEM_ROT_PP		47
#define IPUV3_CHANNEL_ROT_ENC_MEM		48
#define IPUV3_CHANNEL_ROT_VF_MEM		49
#define IPUV3_CHANNEL_ROT_PP_MEM		50
#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA		51
#define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA	52
#define IPUV3_NUM_CHANNELS			64

static inline int ipu_channel_alpha_channel(int ch_num)
{
	switch (ch_num) {
	case IPUV3_CHANNEL_G_MEM_IC_PRP_VF:
		return IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA;
	case IPUV3_CHANNEL_G_MEM_IC_PP:
		return IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA;
	case IPUV3_CHANNEL_MEM_FG_SYNC:
		return IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA;
	case IPUV3_CHANNEL_MEM_FG_ASYNC:
		return IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA;
	case IPUV3_CHANNEL_MEM_BG_SYNC:
		return IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA;
	case IPUV3_CHANNEL_MEM_BG_ASYNC:
		return IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA;
	case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB:
		return IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA;
	default:
		return -EINVAL;
	}
}

int ipu_map_irq(struct ipu_soc *ipu, int irq);
int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
		enum ipu_channel_irq irq);

#define IPU_IRQ_DP_SF_START		(448 + 2)
#define IPU_IRQ_DP_SF_END		(448 + 3)
#define IPU_IRQ_BG_SF_END		IPU_IRQ_DP_SF_END,
#define IPU_IRQ_DC_FC_0			(448 + 8)
#define IPU_IRQ_DC_FC_1			(448 + 9)
#define IPU_IRQ_DC_FC_2			(448 + 10)
#define IPU_IRQ_DC_FC_3			(448 + 11)
#define IPU_IRQ_DC_FC_4			(448 + 12)
#define IPU_IRQ_DC_FC_6			(448 + 13)
#define IPU_IRQ_VSYNC_PRE_0		(448 + 14)
#define IPU_IRQ_VSYNC_PRE_1		(448 + 15)

/*
 * IPU Common functions
 */
int ipu_get_num(struct ipu_soc *ipu);
void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
void ipu_dump(struct ipu_soc *ipu);

/*
 * IPU Image DMA Controller (idmac) functions
 */
struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
void ipu_idmac_put(struct ipuv3_channel *);

int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);

void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
		bool doublebuffer);
int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch);
int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch);
int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink);
int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink);

/*
 * IPU Channel Parameter Memory (cpmem) functions
 */
struct ipu_rgb {
	struct fb_bitfield      red;
	struct fb_bitfield      green;
	struct fb_bitfield      blue;
	struct fb_bitfield      transp;
	int                     bits_per_pixel;
};

struct ipu_image {
	struct v4l2_pix_format pix;
	struct v4l2_rect rect;
	dma_addr_t phys0;
	dma_addr_t phys1;
};

void ipu_cpmem_zero(struct ipuv3_channel *ch);
void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
void ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch);
void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch);
void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
			    enum ipu_rotate_mode rot);
int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
			     const struct ipu_rgb *rgb);
int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
				   unsigned int uv_stride,
				   unsigned int u_offset,
				   unsigned int v_offset);
int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
void ipu_cpmem_dump(struct ipuv3_channel *ch);

/*
 * IPU Display Controller (dc) functions
 */
struct ipu_dc;
struct ipu_di;
struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
void ipu_dc_put(struct ipu_dc *dc);
int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
		u32 pixel_fmt, u32 width);
void ipu_dc_enable(struct ipu_soc *ipu);
void ipu_dc_enable_channel(struct ipu_dc *dc);
void ipu_dc_disable_channel(struct ipu_dc *dc);
void ipu_dc_disable(struct ipu_soc *ipu);

/*
 * IPU Display Interface (di) functions
 */
struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
void ipu_di_put(struct ipu_di *);
int ipu_di_disable(struct ipu_di *);
int ipu_di_enable(struct ipu_di *);
int ipu_di_get_num(struct ipu_di *);
int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode);
int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);

/*
 * IPU Display Multi FIFO Controller (dmfc) functions
 */
struct dmfc_channel;
int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width);
struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
void ipu_dmfc_put(struct dmfc_channel *dmfc);

/*
 * IPU Display Processor (dp) functions
 */
#define IPU_DP_FLOW_SYNC_BG	0
#define IPU_DP_FLOW_SYNC_FG	1
#define IPU_DP_FLOW_ASYNC0_BG	2
#define IPU_DP_FLOW_ASYNC0_FG	3
#define IPU_DP_FLOW_ASYNC1_BG	4
#define IPU_DP_FLOW_ASYNC1_FG	5

struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
void ipu_dp_put(struct ipu_dp *);
int ipu_dp_enable(struct ipu_soc *ipu);
int ipu_dp_enable_channel(struct ipu_dp *dp);
void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync);
void ipu_dp_disable(struct ipu_soc *ipu);
int ipu_dp_setup_channel(struct ipu_dp *dp,
		enum ipu_color_space in, enum ipu_color_space out);
int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
		bool bg_chan);

/*
 * IPU Prefetch Resolve Gasket (prg) functions
 */
int ipu_prg_max_active_channels(void);
bool ipu_prg_present(struct ipu_soc *ipu);
bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format,
			      uint64_t modifier);
int ipu_prg_enable(struct ipu_soc *ipu);
void ipu_prg_disable(struct ipu_soc *ipu);
void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan);
int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
			      unsigned int axi_id,  unsigned int width,
			      unsigned int height, unsigned int stride,
			      u32 format, unsigned long *eba);

/*
 * IPU CMOS Sensor Interface (csi) functions
 */
struct ipu_csi;
int ipu_csi_init_interface(struct ipu_csi *csi,
			   struct v4l2_mbus_config *mbus_cfg,
			   struct v4l2_mbus_framefmt *mbus_fmt);
bool ipu_csi_is_interlaced(struct ipu_csi *csi);
void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert);
void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
				u32 r_value, u32 g_value, u32 b_value,
				u32 pix_clk);
int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
			      struct v4l2_mbus_framefmt *mbus_fmt);
int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
			  u32 max_ratio, u32 id);
int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
int ipu_csi_enable(struct ipu_csi *csi);
int ipu_csi_disable(struct ipu_csi *csi);
struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
void ipu_csi_put(struct ipu_csi *csi);
void ipu_csi_dump(struct ipu_csi *csi);

/*
 * IPU Image Converter (ic) functions
 */
enum ipu_ic_task {
	IC_TASK_ENCODER,
	IC_TASK_VIEWFINDER,
	IC_TASK_POST_PROCESSOR,
	IC_NUM_TASKS,
};

struct ipu_ic;
int ipu_ic_task_init(struct ipu_ic *ic,
		     int in_width, int in_height,
		     int out_width, int out_height,
		     enum ipu_color_space in_cs,
		     enum ipu_color_space out_cs);
int ipu_ic_task_graphics_init(struct ipu_ic *ic,
			      enum ipu_color_space in_g_cs,
			      bool galpha_en, u32 galpha,
			      bool colorkey_en, u32 colorkey);
void ipu_ic_task_enable(struct ipu_ic *ic);
void ipu_ic_task_disable(struct ipu_ic *ic);
int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
			  u32 width, u32 height, int burst_size,
			  enum ipu_rotate_mode rot);
int ipu_ic_enable(struct ipu_ic *ic);
int ipu_ic_disable(struct ipu_ic *ic);
struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
void ipu_ic_put(struct ipu_ic *ic);
void ipu_ic_dump(struct ipu_ic *ic);

/*
 * IPU Video De-Interlacer (vdi) functions
 */
struct ipu_vdi;
void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field);
void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel);
void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres);
void ipu_vdi_unsetup(struct ipu_vdi *vdi);
int ipu_vdi_enable(struct ipu_vdi *vdi);
int ipu_vdi_disable(struct ipu_vdi *vdi);
struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu);
void ipu_vdi_put(struct ipu_vdi *vdi);

/*
 * IPU Sensor Multiple FIFO Controller (SMFC) functions
 */
struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
void ipu_smfc_put(struct ipu_smfc *smfc);
int ipu_smfc_enable(struct ipu_smfc *smfc);
int ipu_smfc_disable(struct ipu_smfc *smfc);
int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);

enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
bool ipu_pixelformat_is_planar(u32 pixelformat);
int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
			    bool hflip, bool vflip);
int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
			    bool hflip, bool vflip);

struct ipu_client_platformdata {
	int csi;
	int di;
	int dc;
	int dp;
	int dma[2];
	struct device_node *of_node;
};

#endif /* __DRM_IPU_H__ */
Commit	Line	Data
aecfbdb1 SH	1	/*
	2	* Copyright 2005-2009 Freescale Semiconductor, Inc.
	3	*
	4	* The code contained herein is licensed under the GNU Lesser General
	5	* Public License. You may obtain a copy of the GNU Lesser General
	6	* Public License Version 2.1 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/lgpl-license.html
	9	* http://www.gnu.org/copyleft/lgpl.html
	10	*/
	11
	12	#ifndef __DRM_IPU_H__
	13	#define __DRM_IPU_H__
	14
	15	#include <linux/types.h>
	16	#include <linux/videodev2.h>
	17	#include <linux/bitmap.h>
	18	#include <linux/fb.h>
310944d1	19	#include <linux/of.h>
2ffd48f2	20	#include <media/v4l2-mediabus.h>
6541d710	21	#include <video/videomode.h>
aecfbdb1 SH	22
	23	struct ipu_soc;
	24
	25	enum ipuv3_type {
	26	IPUV3EX,
	27	IPUV3M,
	28	IPUV3H,
	29	};
	30
7f4392aa PZ	31	#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
7f4392aa PZ	32
aecfbdb1 SH	33	/*
	34	* Bitfield of Display Interface signal polarities.
	35	*/
	36	struct ipu_di_signal_cfg {
aecfbdb1 SH	37	unsigned data_pol:1; /* true = inverted */
	38	unsigned clk_pol:1; /* true = rising edge */
	39	unsigned enable_pol:1;
aecfbdb1	40
b6835a71 SL	41	struct videomode mode;
b6835a71 SL	42
2872c807	43	u32 bus_format;
aecfbdb1	44	u32 v_to_h_sync;
b6835a71	45
aecfbdb1 SH	46	#define IPU_DI_CLKMODE_SYNC (1 << 0)
	47	#define IPU_DI_CLKMODE_EXT (1 << 1)
	48	unsigned long clkflags;
2ea42608 PZ	49
	50	u8 hsync_pin;
	51	u8 vsync_pin;
aecfbdb1 SH	52	};
aecfbdb1 SH	53
2ffd48f2 SL	54	/*
	55	* Enumeration of CSI destinations
	56	*/
	57	enum ipu_csi_dest {
	58	IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
	59	IPU_CSI_DEST_IC, /* to Image Converter */
	60	IPU_CSI_DEST_VDIC, /* to VDIC */
	61	};
	62
1aa8ea0d SL	63	/*
	64	* Enumeration of IPU rotation modes
	65	*/
8b9c3d50 SL	66	#define IPU_ROT_BIT_VFLIP (1 << 0)
	67	#define IPU_ROT_BIT_HFLIP (1 << 1)
	68	#define IPU_ROT_BIT_90 (1 << 2)
	69
1aa8ea0d SL	70	enum ipu_rotate_mode {
1aa8ea0d SL	71	IPU_ROTATE_NONE = 0,
8b9c3d50 SL	72	IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFLIP,
	73	IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HFLIP,
	74	IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP \| IPU_ROT_BIT_HFLIP),
	75	IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90,
	76	IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_BIT_90 \| IPU_ROT_BIT_VFLIP),
	77	IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_BIT_90 \| IPU_ROT_BIT_HFLIP),
	78	IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 \|
	79	IPU_ROT_BIT_VFLIP \| IPU_ROT_BIT_HFLIP),
1aa8ea0d SL	80	};
1aa8ea0d SL	81
8b9c3d50 SL	82	/* 90-degree rotations require the IRT unit */
	83	#define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT_BIT_90) != 0)
	84
aecfbdb1 SH	85	enum ipu_color_space {
	86	IPUV3_COLORSPACE_RGB,
	87	IPUV3_COLORSPACE_YUV,
	88	IPUV3_COLORSPACE_UNKNOWN,
	89	};
	90
2d2ead45 SL	91	/*
	92	* Enumeration of VDI MOTION select
	93	*/
	94	enum ipu_motion_sel {
	95	MOTION_NONE = 0,
	96	LOW_MOTION,
	97	MED_MOTION,
	98	HIGH_MOTION,
	99	};
	100
aecfbdb1 SH	101	struct ipuv3_channel;
	102
	103	enum ipu_channel_irq {
	104	IPU_IRQ_EOF = 0,
	105	IPU_IRQ_NFACK = 64,
	106	IPU_IRQ_NFB4EOF = 128,
	107	IPU_IRQ_EOS = 192,
	108	};
	109
a4cd8f22 SL	110	/*
	111	* Enumeration of IDMAC channels
	112	*/
	113	#define IPUV3_CHANNEL_CSI0 0
	114	#define IPUV3_CHANNEL_CSI1 1
	115	#define IPUV3_CHANNEL_CSI2 2
	116	#define IPUV3_CHANNEL_CSI3 3
	117	#define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
ac4708fa SL	118	/*
	119	* NOTE: channels 6,7 are unused in the IPU and are not IDMAC channels,
	120	* but the direct CSI->VDI linking is handled the same way as IDMAC
	121	* channel linking in the FSU via the IPU_FS_PROC_FLOW registers, so
	122	* these channel names are used to support the direct CSI->VDI link.
	123	*/
	124	#define IPUV3_CHANNEL_CSI_DIRECT 6
	125	#define IPUV3_CHANNEL_CSI_VDI_PREV 7
97afc25c SL	126	#define IPUV3_CHANNEL_MEM_VDI_PREV 8
	127	#define IPUV3_CHANNEL_MEM_VDI_CUR 9
	128	#define IPUV3_CHANNEL_MEM_VDI_NEXT 10
a4cd8f22 SL	129	#define IPUV3_CHANNEL_MEM_IC_PP 11
a4cd8f22 SL	130	#define IPUV3_CHANNEL_MEM_IC_PRP_VF 12
bc0a3387	131	#define IPUV3_CHANNEL_VDI_MEM_RECENT 13
a4cd8f22 SL	132	#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14
a4cd8f22 SL	133	#define IPUV3_CHANNEL_G_MEM_IC_PP 15
bc0a3387 PZ	134	#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA 17
	135	#define IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA 18
	136	#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA 19
a4cd8f22 SL	137	#define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20
	138	#define IPUV3_CHANNEL_IC_PRP_VF_MEM 21
	139	#define IPUV3_CHANNEL_IC_PP_MEM 22
	140	#define IPUV3_CHANNEL_MEM_BG_SYNC 23
	141	#define IPUV3_CHANNEL_MEM_BG_ASYNC 24
bc0a3387 PZ	142	#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB 25
bc0a3387 PZ	143	#define IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB 26
a4cd8f22 SL	144	#define IPUV3_CHANNEL_MEM_FG_SYNC 27
	145	#define IPUV3_CHANNEL_MEM_DC_SYNC 28
	146	#define IPUV3_CHANNEL_MEM_FG_ASYNC 29
	147	#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31
bc0a3387 PZ	148	#define IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA 33
bc0a3387 PZ	149	#define IPUV3_CHANNEL_DC_MEM_READ 40
a4cd8f22	150	#define IPUV3_CHANNEL_MEM_DC_ASYNC 41
bc0a3387 PZ	151	#define IPUV3_CHANNEL_MEM_DC_COMMAND 42
	152	#define IPUV3_CHANNEL_MEM_DC_COMMAND2 43
	153	#define IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK 44
a4cd8f22 SL	154	#define IPUV3_CHANNEL_MEM_ROT_ENC 45
	155	#define IPUV3_CHANNEL_MEM_ROT_VF 46
	156	#define IPUV3_CHANNEL_MEM_ROT_PP 47
	157	#define IPUV3_CHANNEL_ROT_ENC_MEM 48
	158	#define IPUV3_CHANNEL_ROT_VF_MEM 49
	159	#define IPUV3_CHANNEL_ROT_PP_MEM 50
	160	#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
bc0a3387	161	#define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA 52
ac4708fa	162	#define IPUV3_NUM_CHANNELS 64
a4cd8f22	163
e72db3b1 PZ	164	static inline int ipu_channel_alpha_channel(int ch_num)
	165	{
	166	switch (ch_num) {
	167	case IPUV3_CHANNEL_G_MEM_IC_PRP_VF:
	168	return IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA;
	169	case IPUV3_CHANNEL_G_MEM_IC_PP:
	170	return IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA;
	171	case IPUV3_CHANNEL_MEM_FG_SYNC:
	172	return IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA;
	173	case IPUV3_CHANNEL_MEM_FG_ASYNC:
	174	return IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA;
	175	case IPUV3_CHANNEL_MEM_BG_SYNC:
	176	return IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA;
	177	case IPUV3_CHANNEL_MEM_BG_ASYNC:
	178	return IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA;
	179	case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB:
	180	return IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA;
	181	default:
	182	return -EINVAL;
	183	}
	184	}
	185
861a50c1	186	int ipu_map_irq(struct ipu_soc *ipu, int irq);
aecfbdb1 SH	187	int ipu_idmac_channel_irq(struct ipu_soc ipu, struct ipuv3_channel channel,
	188	enum ipu_channel_irq irq);
	189
	190	#define IPU_IRQ_DP_SF_START (448 + 2)
	191	#define IPU_IRQ_DP_SF_END (448 + 3)
	192	#define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
	193	#define IPU_IRQ_DC_FC_0 (448 + 8)
	194	#define IPU_IRQ_DC_FC_1 (448 + 9)
	195	#define IPU_IRQ_DC_FC_2 (448 + 10)
	196	#define IPU_IRQ_DC_FC_3 (448 + 11)
	197	#define IPU_IRQ_DC_FC_4 (448 + 12)
	198	#define IPU_IRQ_DC_FC_6 (448 + 13)
	199	#define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
	200	#define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
	201
ba07975f SL	202	/*
	203	* IPU Common functions
	204	*/
572a7615	205	int ipu_get_num(struct ipu_soc *ipu);
ba07975f SL	206	void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
ba07975f SL	207	void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
3feb049f	208	void ipu_dump(struct ipu_soc *ipu);
ba07975f	209
aecfbdb1 SH	210	/*
	211	* IPU Image DMA Controller (idmac) functions
	212	*/
	213	struct ipuv3_channel ipu_idmac_get(struct ipu_soc ipu, unsigned channel);
	214	void ipu_idmac_put(struct ipuv3_channel *);
	215
	216	int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
	217	int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
2bcf577e	218	void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
4fd1a07a	219	int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
fb822a39	220	int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
aecfbdb1 SH	221
	222	void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
	223	bool doublebuffer);
e9046097	224	int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
aa52f578	225	bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
aecfbdb1	226	void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
bce6f087	227	void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
ac4708fa SL	228	int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch);
	229	int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch);
	230	int ipu_idmac_link(struct ipuv3_channel src, struct ipuv3_channel sink);
	231	int ipu_idmac_unlink(struct ipuv3_channel src, struct ipuv3_channel sink);
aecfbdb1	232
7d2691da SL	233	/*
	234	* IPU Channel Parameter Memory (cpmem) functions
	235	*/
	236	struct ipu_rgb {
	237	struct fb_bitfield red;
	238	struct fb_bitfield green;
	239	struct fb_bitfield blue;
	240	struct fb_bitfield transp;
	241	int bits_per_pixel;
	242	};
	243
	244	struct ipu_image {
	245	struct v4l2_pix_format pix;
	246	struct v4l2_rect rect;
2094b603 SL	247	dma_addr_t phys0;
2094b603 SL	248	dma_addr_t phys1;
7d2691da SL	249	};
	250
	251	void ipu_cpmem_zero(struct ipuv3_channel *ch);
	252	void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
e1e9733c	253	void ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch);
7d2691da SL	254	void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
	255	void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
	256	void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
e5e8690f	257	void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
7d2691da	258	void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
555f0e66	259	void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
03085911	260	int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch);
7d2691da	261	void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
9b9da0be	262	void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
c42d37ca SL	263	void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
c42d37ca SL	264	enum ipu_rotate_mode rot);
7d2691da SL	265	int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
	266	const struct ipu_rgb *rgb);
	267	int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
	268	void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
	269	void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
90195c36 PZ	270	unsigned int uv_stride,
	271	unsigned int u_offset,
	272	unsigned int v_offset);
7d2691da SL	273	int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
7d2691da SL	274	int ipu_cpmem_set_image(struct ipuv3_channel ch, struct ipu_image image);
60c04456	275	void ipu_cpmem_dump(struct ipuv3_channel *ch);
7d2691da	276
aecfbdb1 SH	277	/*
	278	* IPU Display Controller (dc) functions
	279	*/
	280	struct ipu_dc;
	281	struct ipu_di;
	282	struct ipu_dc ipu_dc_get(struct ipu_soc ipu, int channel);
	283	void ipu_dc_put(struct ipu_dc *dc);
	284	int ipu_dc_init_sync(struct ipu_dc dc, struct ipu_di di, bool interlaced,
	285	u32 pixel_fmt, u32 width);
1e6d486b	286	void ipu_dc_enable(struct ipu_soc *ipu);
aecfbdb1 SH	287	void ipu_dc_enable_channel(struct ipu_dc *dc);
aecfbdb1 SH	288	void ipu_dc_disable_channel(struct ipu_dc *dc);
1e6d486b	289	void ipu_dc_disable(struct ipu_soc *ipu);
aecfbdb1 SH	290
	291	/*
	292	* IPU Display Interface (di) functions
	293	*/
	294	struct ipu_di ipu_di_get(struct ipu_soc ipu, int disp);
	295	void ipu_di_put(struct ipu_di *);
	296	int ipu_di_disable(struct ipu_di *);
	297	int ipu_di_enable(struct ipu_di *);
	298	int ipu_di_get_num(struct ipu_di *);
6541d710	299	int ipu_di_adjust_videomode(struct ipu_di di, struct videomode mode);
aecfbdb1 SH	300	int ipu_di_init_sync_panel(struct ipu_di , struct ipu_di_signal_cfg sig);
	301
	302	/*
	303	* IPU Display Multi FIFO Controller (dmfc) functions
	304	*/
	305	struct dmfc_channel;
	306	int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
	307	void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
27630c20	308	void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width);
aecfbdb1 SH	309	struct dmfc_channel ipu_dmfc_get(struct ipu_soc ipu, int ipuv3_channel);
	310	void ipu_dmfc_put(struct dmfc_channel *dmfc);
	311
	312	/*
	313	* IPU Display Processor (dp) functions
	314	*/
	315	#define IPU_DP_FLOW_SYNC_BG 0
	316	#define IPU_DP_FLOW_SYNC_FG 1
	317	#define IPU_DP_FLOW_ASYNC0_BG 2
	318	#define IPU_DP_FLOW_ASYNC0_FG 3
	319	#define IPU_DP_FLOW_ASYNC1_BG 4
	320	#define IPU_DP_FLOW_ASYNC1_FG 5
	321
	322	struct ipu_dp ipu_dp_get(struct ipu_soc ipu, unsigned int flow);
	323	void ipu_dp_put(struct ipu_dp *);
285bbb01	324	int ipu_dp_enable(struct ipu_soc *ipu);
aecfbdb1	325	int ipu_dp_enable_channel(struct ipu_dp *dp);
f9bb7acb	326	void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync);
285bbb01	327	void ipu_dp_disable(struct ipu_soc *ipu);
aecfbdb1 SH	328	int ipu_dp_setup_channel(struct ipu_dp *dp,
	329	enum ipu_color_space in, enum ipu_color_space out);
	330	int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
	331	int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
	332	bool bg_chan);
	333
ea9c2605 LS	334	/*
	335	* IPU Prefetch Resolve Gasket (prg) functions
	336	*/
	337	int ipu_prg_max_active_channels(void);
	338	bool ipu_prg_present(struct ipu_soc *ipu);
	339	bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format,
	340	uint64_t modifier);
	341	int ipu_prg_enable(struct ipu_soc *ipu);
	342	void ipu_prg_disable(struct ipu_soc *ipu);
	343	void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan);
	344	int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
	345	unsigned int axi_id, unsigned int width,
	346	unsigned int height, unsigned int stride,
	347	u32 format, unsigned long *eba);
	348
3f5a8a94 PZ	349	/*
	350	* IPU CMOS Sensor Interface (csi) functions
	351	*/
2ffd48f2 SL	352	struct ipu_csi;
	353	int ipu_csi_init_interface(struct ipu_csi *csi,
	354	struct v4l2_mbus_config *mbus_cfg,
	355	struct v4l2_mbus_framefmt *mbus_fmt);
	356	bool ipu_csi_is_interlaced(struct ipu_csi *csi);
	357	void ipu_csi_get_window(struct ipu_csi csi, struct v4l2_rect w);
	358	void ipu_csi_set_window(struct ipu_csi csi, struct v4l2_rect w);
867341b9	359	void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert);
2ffd48f2 SL	360	void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
	361	u32 r_value, u32 g_value, u32 b_value,
	362	u32 pix_clk);
	363	int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
	364	struct v4l2_mbus_framefmt *mbus_fmt);
	365	int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
	366	u32 max_ratio, u32 id);
	367	int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
	368	int ipu_csi_enable(struct ipu_csi *csi);
	369	int ipu_csi_disable(struct ipu_csi *csi);
	370	struct ipu_csi ipu_csi_get(struct ipu_soc ipu, int id);
	371	void ipu_csi_put(struct ipu_csi *csi);
	372	void ipu_csi_dump(struct ipu_csi *csi);
3f5a8a94	373
1aa8ea0d SL	374	/*
	375	* IPU Image Converter (ic) functions
	376	*/
	377	enum ipu_ic_task {
	378	IC_TASK_ENCODER,
	379	IC_TASK_VIEWFINDER,
	380	IC_TASK_POST_PROCESSOR,
	381	IC_NUM_TASKS,
	382	};
	383
	384	struct ipu_ic;
	385	int ipu_ic_task_init(struct ipu_ic *ic,
	386	int in_width, int in_height,
	387	int out_width, int out_height,
	388	enum ipu_color_space in_cs,
	389	enum ipu_color_space out_cs);
	390	int ipu_ic_task_graphics_init(struct ipu_ic *ic,
	391	enum ipu_color_space in_g_cs,
	392	bool galpha_en, u32 galpha,
	393	bool colorkey_en, u32 colorkey);
	394	void ipu_ic_task_enable(struct ipu_ic *ic);
	395	void ipu_ic_task_disable(struct ipu_ic *ic);
	396	int ipu_ic_task_idma_init(struct ipu_ic ic, struct ipuv3_channel channel,
	397	u32 width, u32 height, int burst_size,
	398	enum ipu_rotate_mode rot);
	399	int ipu_ic_enable(struct ipu_ic *ic);
	400	int ipu_ic_disable(struct ipu_ic *ic);
	401	struct ipu_ic ipu_ic_get(struct ipu_soc ipu, enum ipu_ic_task task);
	402	void ipu_ic_put(struct ipu_ic *ic);
	403	void ipu_ic_dump(struct ipu_ic *ic);
	404
2d2ead45 SL	405	/*
	406	* IPU Video De-Interlacer (vdi) functions
	407	*/
	408	struct ipu_vdi;
	409	void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field);
	410	void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel);
	411	void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres);
	412	void ipu_vdi_unsetup(struct ipu_vdi *vdi);
	413	int ipu_vdi_enable(struct ipu_vdi *vdi);
	414	int ipu_vdi_disable(struct ipu_vdi *vdi);
	415	struct ipu_vdi ipu_vdi_get(struct ipu_soc ipu);
	416	void ipu_vdi_put(struct ipu_vdi *vdi);
	417
35de925f PZ	418	/*
	419	* IPU Sensor Multiple FIFO Controller (SMFC) functions
	420	*/
7fafa8f0 SL	421	struct ipu_smfc ipu_smfc_get(struct ipu_soc ipu, unsigned int chno);
	422	void ipu_smfc_put(struct ipu_smfc *smfc);
	423	int ipu_smfc_enable(struct ipu_smfc *smfc);
	424	int ipu_smfc_disable(struct ipu_smfc *smfc);
	425	int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
	426	int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
a2be35e3	427	int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
35de925f	428
7cb17797	429	enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
aecfbdb1	430	enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
ae0e9708	431	enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
6930afdc	432	int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
4cea940d	433	bool ipu_pixelformat_is_planar(u32 pixelformat);
f835f386 SL	434	int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
	435	bool hflip, bool vflip);
	436	int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
	437	bool hflip, bool vflip);
aecfbdb1	438
aecfbdb1	439	struct ipu_client_platformdata {
d6ca8ca7	440	int csi;
aecfbdb1 SH	441	int di;
	442	int dc;
	443	int dp;
aecfbdb1	444	int dma[2];
310944d1	445	struct device_node *of_node;
aecfbdb1 SH	446	};
	447
	448	#endif /* __DRM_IPU_H__ */