[mirror_ubuntu-artful-kernel.git] / include / video / imx-ipu-v3.h

/*
 * Copyright 2005-2009 Freescale Semiconductor, Inc.
 *
 * The code contained herein is licensed under the GNU Lesser General
 * Public License.  You may obtain a copy of the GNU Lesser General
 * Public License Version 2.1 or later at the following locations:
 *
 * http://www.opensource.org/licenses/lgpl-license.html
 * http://www.gnu.org/copyleft/lgpl.html
 */

#ifndef __DRM_IPU_H__
#define __DRM_IPU_H__

#include <linux/types.h>
#include <linux/videodev2.h>
#include <linux/bitmap.h>
#include <linux/fb.h>

struct ipu_soc;

enum ipuv3_type {
	IPUV3EX,
	IPUV3M,
	IPUV3H,
};

#define IPU_PIX_FMT_GBR24	v4l2_fourcc('G', 'B', 'R', '3')

/*
 * Bitfield of Display Interface signal polarities.
 */
struct ipu_di_signal_cfg {
	unsigned datamask_en:1;
	unsigned interlaced:1;
	unsigned odd_field_first:1;
	unsigned clksel_en:1;
	unsigned clkidle_en:1;
	unsigned data_pol:1;	/* true = inverted */
	unsigned clk_pol:1;	/* true = rising edge */
	unsigned enable_pol:1;
	unsigned Hsync_pol:1;	/* true = active high */
	unsigned Vsync_pol:1;

	u16 width;
	u16 height;
	u32 pixel_fmt;
	u16 h_start_width;
	u16 h_sync_width;
	u16 h_end_width;
	u16 v_start_width;
	u16 v_sync_width;
	u16 v_end_width;
	u32 v_to_h_sync;
	unsigned long pixelclock;
#define IPU_DI_CLKMODE_SYNC	(1 << 0)
#define IPU_DI_CLKMODE_EXT	(1 << 1)
	unsigned long clkflags;

	u8 hsync_pin;
	u8 vsync_pin;
};

enum ipu_color_space {
	IPUV3_COLORSPACE_RGB,
	IPUV3_COLORSPACE_YUV,
	IPUV3_COLORSPACE_UNKNOWN,
};

struct ipuv3_channel;

enum ipu_channel_irq {
	IPU_IRQ_EOF = 0,
	IPU_IRQ_NFACK = 64,
	IPU_IRQ_NFB4EOF = 128,
	IPU_IRQ_EOS = 192,
};

int ipu_map_irq(struct ipu_soc *ipu, int irq);
int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
		enum ipu_channel_irq irq);

#define IPU_IRQ_DP_SF_START		(448 + 2)
#define IPU_IRQ_DP_SF_END		(448 + 3)
#define IPU_IRQ_BG_SF_END		IPU_IRQ_DP_SF_END,
#define IPU_IRQ_DC_FC_0			(448 + 8)
#define IPU_IRQ_DC_FC_1			(448 + 9)
#define IPU_IRQ_DC_FC_2			(448 + 10)
#define IPU_IRQ_DC_FC_3			(448 + 11)
#define IPU_IRQ_DC_FC_4			(448 + 12)
#define IPU_IRQ_DC_FC_6			(448 + 13)
#define IPU_IRQ_VSYNC_PRE_0		(448 + 14)
#define IPU_IRQ_VSYNC_PRE_1		(448 + 15)

/*
 * IPU Image DMA Controller (idmac) functions
 */
struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
void ipu_idmac_put(struct ipuv3_channel *);

int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);

void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
		bool doublebuffer);
int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);

/*
 * IPU Channel Parameter Memory (cpmem) functions
 */
struct ipu_rgb {
	struct fb_bitfield      red;
	struct fb_bitfield      green;
	struct fb_bitfield      blue;
	struct fb_bitfield      transp;
	int                     bits_per_pixel;
};

struct ipu_image {
	struct v4l2_pix_format pix;
	struct v4l2_rect rect;
	dma_addr_t phys;
};

void ipu_cpmem_zero(struct ipuv3_channel *ch);
void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
			     const struct ipu_rgb *rgb);
int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
				   u32 pixel_format, int stride,
				   int u_offset, int v_offset);
void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
			      u32 pixel_format, int stride, int height);
int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);

/*
 * IPU Display Controller (dc) functions
 */
struct ipu_dc;
struct ipu_di;
struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
void ipu_dc_put(struct ipu_dc *dc);
int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
		u32 pixel_fmt, u32 width);
void ipu_dc_enable(struct ipu_soc *ipu);
void ipu_dc_enable_channel(struct ipu_dc *dc);
void ipu_dc_disable_channel(struct ipu_dc *dc);
void ipu_dc_disable(struct ipu_soc *ipu);

/*
 * IPU Display Interface (di) functions
 */
struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
void ipu_di_put(struct ipu_di *);
int ipu_di_disable(struct ipu_di *);
int ipu_di_enable(struct ipu_di *);
int ipu_di_get_num(struct ipu_di *);
int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);

/*
 * IPU Display Multi FIFO Controller (dmfc) functions
 */
struct dmfc_channel;
int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
		unsigned long bandwidth_mbs, int burstsize);
void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width);
struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
void ipu_dmfc_put(struct dmfc_channel *dmfc);

/*
 * IPU Display Processor (dp) functions
 */
#define IPU_DP_FLOW_SYNC_BG	0
#define IPU_DP_FLOW_SYNC_FG	1
#define IPU_DP_FLOW_ASYNC0_BG	2
#define IPU_DP_FLOW_ASYNC0_FG	3
#define IPU_DP_FLOW_ASYNC1_BG	4
#define IPU_DP_FLOW_ASYNC1_FG	5

struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
void ipu_dp_put(struct ipu_dp *);
int ipu_dp_enable(struct ipu_soc *ipu);
int ipu_dp_enable_channel(struct ipu_dp *dp);
void ipu_dp_disable_channel(struct ipu_dp *dp);
void ipu_dp_disable(struct ipu_soc *ipu);
int ipu_dp_setup_channel(struct ipu_dp *dp,
		enum ipu_color_space in, enum ipu_color_space out);
int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
		bool bg_chan);

/*
 * IPU CMOS Sensor Interface (csi) functions
 */
int ipu_csi_enable(struct ipu_soc *ipu, int csi);
int ipu_csi_disable(struct ipu_soc *ipu, int csi);

/*
 * IPU Sensor Multiple FIFO Controller (SMFC) functions
 */
int ipu_smfc_enable(struct ipu_soc *ipu);
int ipu_smfc_disable(struct ipu_soc *ipu);
int ipu_smfc_map_channel(struct ipu_soc *ipu, int channel, int csi_id, int mipi_id);
int ipu_smfc_set_burstsize(struct ipu_soc *ipu, int channel, int burstsize);

enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);

struct ipu_client_platformdata {
	int csi;
	int di;
	int dc;
	int dp;
	int dmfc;
	int dma[2];
};

#endif /* __DRM_IPU_H__ */
Commit	Line	Data
aecfbdb1 SH	1	/*
	2	* Copyright 2005-2009 Freescale Semiconductor, Inc.
	3	*
	4	* The code contained herein is licensed under the GNU Lesser General
	5	* Public License. You may obtain a copy of the GNU Lesser General
	6	* Public License Version 2.1 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/lgpl-license.html
	9	* http://www.gnu.org/copyleft/lgpl.html
	10	*/
	11
	12	#ifndef __DRM_IPU_H__
	13	#define __DRM_IPU_H__
	14
	15	#include <linux/types.h>
	16	#include <linux/videodev2.h>
	17	#include <linux/bitmap.h>
	18	#include <linux/fb.h>
aecfbdb1 SH	19
	20	struct ipu_soc;
	21
	22	enum ipuv3_type {
	23	IPUV3EX,
	24	IPUV3M,
	25	IPUV3H,
	26	};
	27
7f4392aa PZ	28	#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
7f4392aa PZ	29
aecfbdb1 SH	30	/*
	31	* Bitfield of Display Interface signal polarities.
	32	*/
	33	struct ipu_di_signal_cfg {
	34	unsigned datamask_en:1;
	35	unsigned interlaced:1;
	36	unsigned odd_field_first:1;
	37	unsigned clksel_en:1;
	38	unsigned clkidle_en:1;
	39	unsigned data_pol:1; /* true = inverted */
	40	unsigned clk_pol:1; /* true = rising edge */
	41	unsigned enable_pol:1;
	42	unsigned Hsync_pol:1; /* true = active high */
	43	unsigned Vsync_pol:1;
	44
	45	u16 width;
	46	u16 height;
	47	u32 pixel_fmt;
	48	u16 h_start_width;
	49	u16 h_sync_width;
	50	u16 h_end_width;
	51	u16 v_start_width;
	52	u16 v_sync_width;
	53	u16 v_end_width;
	54	u32 v_to_h_sync;
	55	unsigned long pixelclock;
	56	#define IPU_DI_CLKMODE_SYNC (1 << 0)
	57	#define IPU_DI_CLKMODE_EXT (1 << 1)
	58	unsigned long clkflags;
2ea42608 PZ	59
	60	u8 hsync_pin;
	61	u8 vsync_pin;
aecfbdb1 SH	62	};
	63
	64	enum ipu_color_space {
	65	IPUV3_COLORSPACE_RGB,
	66	IPUV3_COLORSPACE_YUV,
	67	IPUV3_COLORSPACE_UNKNOWN,
	68	};
	69
	70	struct ipuv3_channel;
	71
	72	enum ipu_channel_irq {
	73	IPU_IRQ_EOF = 0,
	74	IPU_IRQ_NFACK = 64,
	75	IPU_IRQ_NFB4EOF = 128,
	76	IPU_IRQ_EOS = 192,
	77	};
	78
861a50c1	79	int ipu_map_irq(struct ipu_soc *ipu, int irq);
aecfbdb1 SH	80	int ipu_idmac_channel_irq(struct ipu_soc ipu, struct ipuv3_channel channel,
	81	enum ipu_channel_irq irq);
	82
	83	#define IPU_IRQ_DP_SF_START (448 + 2)
	84	#define IPU_IRQ_DP_SF_END (448 + 3)
	85	#define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
	86	#define IPU_IRQ_DC_FC_0 (448 + 8)
	87	#define IPU_IRQ_DC_FC_1 (448 + 9)
	88	#define IPU_IRQ_DC_FC_2 (448 + 10)
	89	#define IPU_IRQ_DC_FC_3 (448 + 11)
	90	#define IPU_IRQ_DC_FC_4 (448 + 12)
	91	#define IPU_IRQ_DC_FC_6 (448 + 13)
	92	#define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
	93	#define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
	94
	95	/*
	96	* IPU Image DMA Controller (idmac) functions
	97	*/
	98	struct ipuv3_channel ipu_idmac_get(struct ipu_soc ipu, unsigned channel);
	99	void ipu_idmac_put(struct ipuv3_channel *);
	100
	101	int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
	102	int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
fb822a39	103	int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
aecfbdb1 SH	104
	105	void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
	106	bool doublebuffer);
e9046097	107	int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
aecfbdb1 SH	108	void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
aecfbdb1 SH	109
7d2691da SL	110	/*
	111	* IPU Channel Parameter Memory (cpmem) functions
	112	*/
	113	struct ipu_rgb {
	114	struct fb_bitfield red;
	115	struct fb_bitfield green;
	116	struct fb_bitfield blue;
	117	struct fb_bitfield transp;
	118	int bits_per_pixel;
	119	};
	120
	121	struct ipu_image {
	122	struct v4l2_pix_format pix;
	123	struct v4l2_rect rect;
	124	dma_addr_t phys;
	125	};
	126
	127	void ipu_cpmem_zero(struct ipuv3_channel *ch);
	128	void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
	129	void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
	130	void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
	131	void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
	132	void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
	133	void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
	134	int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
	135	const struct ipu_rgb *rgb);
	136	int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
	137	void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
	138	void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
	139	u32 pixel_format, int stride,
	140	int u_offset, int v_offset);
	141	void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
	142	u32 pixel_format, int stride, int height);
	143	int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
	144	int ipu_cpmem_set_image(struct ipuv3_channel ch, struct ipu_image image);
	145
aecfbdb1 SH	146	/*
	147	* IPU Display Controller (dc) functions
	148	*/
	149	struct ipu_dc;
	150	struct ipu_di;
	151	struct ipu_dc ipu_dc_get(struct ipu_soc ipu, int channel);
	152	void ipu_dc_put(struct ipu_dc *dc);
	153	int ipu_dc_init_sync(struct ipu_dc dc, struct ipu_di di, bool interlaced,
	154	u32 pixel_fmt, u32 width);
1e6d486b	155	void ipu_dc_enable(struct ipu_soc *ipu);
aecfbdb1 SH	156	void ipu_dc_enable_channel(struct ipu_dc *dc);
aecfbdb1 SH	157	void ipu_dc_disable_channel(struct ipu_dc *dc);
1e6d486b	158	void ipu_dc_disable(struct ipu_soc *ipu);
aecfbdb1 SH	159
	160	/*
	161	* IPU Display Interface (di) functions
	162	*/
	163	struct ipu_di ipu_di_get(struct ipu_soc ipu, int disp);
	164	void ipu_di_put(struct ipu_di *);
	165	int ipu_di_disable(struct ipu_di *);
	166	int ipu_di_enable(struct ipu_di *);
	167	int ipu_di_get_num(struct ipu_di *);
	168	int ipu_di_init_sync_panel(struct ipu_di , struct ipu_di_signal_cfg sig);
	169
	170	/*
	171	* IPU Display Multi FIFO Controller (dmfc) functions
	172	*/
	173	struct dmfc_channel;
	174	int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
	175	void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
	176	int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
	177	unsigned long bandwidth_mbs, int burstsize);
	178	void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
	179	int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width);
	180	struct dmfc_channel ipu_dmfc_get(struct ipu_soc ipu, int ipuv3_channel);
	181	void ipu_dmfc_put(struct dmfc_channel *dmfc);
	182
	183	/*
	184	* IPU Display Processor (dp) functions
	185	*/
	186	#define IPU_DP_FLOW_SYNC_BG 0
	187	#define IPU_DP_FLOW_SYNC_FG 1
	188	#define IPU_DP_FLOW_ASYNC0_BG 2
	189	#define IPU_DP_FLOW_ASYNC0_FG 3
	190	#define IPU_DP_FLOW_ASYNC1_BG 4
	191	#define IPU_DP_FLOW_ASYNC1_FG 5
	192
	193	struct ipu_dp ipu_dp_get(struct ipu_soc ipu, unsigned int flow);
	194	void ipu_dp_put(struct ipu_dp *);
285bbb01	195	int ipu_dp_enable(struct ipu_soc *ipu);
aecfbdb1 SH	196	int ipu_dp_enable_channel(struct ipu_dp *dp);
aecfbdb1 SH	197	void ipu_dp_disable_channel(struct ipu_dp *dp);
285bbb01	198	void ipu_dp_disable(struct ipu_soc *ipu);
aecfbdb1 SH	199	int ipu_dp_setup_channel(struct ipu_dp *dp,
	200	enum ipu_color_space in, enum ipu_color_space out);
	201	int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
	202	int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
	203	bool bg_chan);
	204
3f5a8a94 PZ	205	/*
	206	* IPU CMOS Sensor Interface (csi) functions
	207	*/
	208	int ipu_csi_enable(struct ipu_soc *ipu, int csi);
	209	int ipu_csi_disable(struct ipu_soc *ipu, int csi);
	210
35de925f PZ	211	/*
	212	* IPU Sensor Multiple FIFO Controller (SMFC) functions
	213	*/
3f5a8a94 PZ	214	int ipu_smfc_enable(struct ipu_soc *ipu);
3f5a8a94 PZ	215	int ipu_smfc_disable(struct ipu_soc *ipu);
35de925f PZ	216	int ipu_smfc_map_channel(struct ipu_soc *ipu, int channel, int csi_id, int mipi_id);
	217	int ipu_smfc_set_burstsize(struct ipu_soc *ipu, int channel, int burstsize);
	218
7cb17797	219	enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
aecfbdb1 SH	220	enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
aecfbdb1 SH	221
aecfbdb1	222	struct ipu_client_platformdata {
d6ca8ca7	223	int csi;
aecfbdb1 SH	224	int di;
	225	int dc;
	226	int dp;
	227	int dmfc;
	228	int dma[2];
	229	};
	230
	231	#endif /* __DRM_IPU_H__ */