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aecfbdb1 SH |
1 | /* |
2 | * Copyright 2005-2009 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU Lesser General | |
5 | * Public License. You may obtain a copy of the GNU Lesser General | |
6 | * Public License Version 2.1 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/lgpl-license.html | |
9 | * http://www.gnu.org/copyleft/lgpl.html | |
10 | */ | |
11 | ||
12 | #ifndef __DRM_IPU_H__ | |
13 | #define __DRM_IPU_H__ | |
14 | ||
15 | #include <linux/types.h> | |
16 | #include <linux/videodev2.h> | |
17 | #include <linux/bitmap.h> | |
18 | #include <linux/fb.h> | |
2ffd48f2 | 19 | #include <media/v4l2-mediabus.h> |
aecfbdb1 SH |
20 | |
21 | struct ipu_soc; | |
22 | ||
23 | enum ipuv3_type { | |
24 | IPUV3EX, | |
25 | IPUV3M, | |
26 | IPUV3H, | |
27 | }; | |
28 | ||
7f4392aa PZ |
29 | #define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3') |
30 | ||
aecfbdb1 SH |
31 | /* |
32 | * Bitfield of Display Interface signal polarities. | |
33 | */ | |
34 | struct ipu_di_signal_cfg { | |
35 | unsigned datamask_en:1; | |
36 | unsigned interlaced:1; | |
37 | unsigned odd_field_first:1; | |
38 | unsigned clksel_en:1; | |
39 | unsigned clkidle_en:1; | |
40 | unsigned data_pol:1; /* true = inverted */ | |
41 | unsigned clk_pol:1; /* true = rising edge */ | |
42 | unsigned enable_pol:1; | |
43 | unsigned Hsync_pol:1; /* true = active high */ | |
44 | unsigned Vsync_pol:1; | |
45 | ||
46 | u16 width; | |
47 | u16 height; | |
48 | u32 pixel_fmt; | |
49 | u16 h_start_width; | |
50 | u16 h_sync_width; | |
51 | u16 h_end_width; | |
52 | u16 v_start_width; | |
53 | u16 v_sync_width; | |
54 | u16 v_end_width; | |
55 | u32 v_to_h_sync; | |
56 | unsigned long pixelclock; | |
57 | #define IPU_DI_CLKMODE_SYNC (1 << 0) | |
58 | #define IPU_DI_CLKMODE_EXT (1 << 1) | |
59 | unsigned long clkflags; | |
2ea42608 PZ |
60 | |
61 | u8 hsync_pin; | |
62 | u8 vsync_pin; | |
aecfbdb1 SH |
63 | }; |
64 | ||
2ffd48f2 SL |
65 | /* |
66 | * Enumeration of CSI destinations | |
67 | */ | |
68 | enum ipu_csi_dest { | |
69 | IPU_CSI_DEST_IDMAC, /* to memory via SMFC */ | |
70 | IPU_CSI_DEST_IC, /* to Image Converter */ | |
71 | IPU_CSI_DEST_VDIC, /* to VDIC */ | |
72 | }; | |
73 | ||
1aa8ea0d SL |
74 | /* |
75 | * Enumeration of IPU rotation modes | |
76 | */ | |
77 | enum ipu_rotate_mode { | |
78 | IPU_ROTATE_NONE = 0, | |
79 | IPU_ROTATE_VERT_FLIP, | |
80 | IPU_ROTATE_HORIZ_FLIP, | |
81 | IPU_ROTATE_180, | |
82 | IPU_ROTATE_90_RIGHT, | |
83 | IPU_ROTATE_90_RIGHT_VFLIP, | |
84 | IPU_ROTATE_90_RIGHT_HFLIP, | |
85 | IPU_ROTATE_90_LEFT, | |
86 | }; | |
87 | ||
aecfbdb1 SH |
88 | enum ipu_color_space { |
89 | IPUV3_COLORSPACE_RGB, | |
90 | IPUV3_COLORSPACE_YUV, | |
91 | IPUV3_COLORSPACE_UNKNOWN, | |
92 | }; | |
93 | ||
94 | struct ipuv3_channel; | |
95 | ||
96 | enum ipu_channel_irq { | |
97 | IPU_IRQ_EOF = 0, | |
98 | IPU_IRQ_NFACK = 64, | |
99 | IPU_IRQ_NFB4EOF = 128, | |
100 | IPU_IRQ_EOS = 192, | |
101 | }; | |
102 | ||
861a50c1 | 103 | int ipu_map_irq(struct ipu_soc *ipu, int irq); |
aecfbdb1 SH |
104 | int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, |
105 | enum ipu_channel_irq irq); | |
106 | ||
107 | #define IPU_IRQ_DP_SF_START (448 + 2) | |
108 | #define IPU_IRQ_DP_SF_END (448 + 3) | |
109 | #define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END, | |
110 | #define IPU_IRQ_DC_FC_0 (448 + 8) | |
111 | #define IPU_IRQ_DC_FC_1 (448 + 9) | |
112 | #define IPU_IRQ_DC_FC_2 (448 + 10) | |
113 | #define IPU_IRQ_DC_FC_3 (448 + 11) | |
114 | #define IPU_IRQ_DC_FC_4 (448 + 12) | |
115 | #define IPU_IRQ_DC_FC_6 (448 + 13) | |
116 | #define IPU_IRQ_VSYNC_PRE_0 (448 + 14) | |
117 | #define IPU_IRQ_VSYNC_PRE_1 (448 + 15) | |
118 | ||
ba07975f SL |
119 | /* |
120 | * IPU Common functions | |
121 | */ | |
122 | void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2); | |
123 | void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi); | |
124 | ||
aecfbdb1 SH |
125 | /* |
126 | * IPU Image DMA Controller (idmac) functions | |
127 | */ | |
128 | struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel); | |
129 | void ipu_idmac_put(struct ipuv3_channel *); | |
130 | ||
131 | int ipu_idmac_enable_channel(struct ipuv3_channel *channel); | |
132 | int ipu_idmac_disable_channel(struct ipuv3_channel *channel); | |
fb822a39 | 133 | int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms); |
aecfbdb1 SH |
134 | |
135 | void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel, | |
136 | bool doublebuffer); | |
e9046097 | 137 | int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel); |
aecfbdb1 SH |
138 | void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num); |
139 | ||
7d2691da SL |
140 | /* |
141 | * IPU Channel Parameter Memory (cpmem) functions | |
142 | */ | |
143 | struct ipu_rgb { | |
144 | struct fb_bitfield red; | |
145 | struct fb_bitfield green; | |
146 | struct fb_bitfield blue; | |
147 | struct fb_bitfield transp; | |
148 | int bits_per_pixel; | |
149 | }; | |
150 | ||
151 | struct ipu_image { | |
152 | struct v4l2_pix_format pix; | |
153 | struct v4l2_rect rect; | |
154 | dma_addr_t phys; | |
155 | }; | |
156 | ||
157 | void ipu_cpmem_zero(struct ipuv3_channel *ch); | |
158 | void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres); | |
159 | void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride); | |
160 | void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch); | |
161 | void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf); | |
162 | void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride); | |
163 | void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize); | |
164 | int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch, | |
165 | const struct ipu_rgb *rgb); | |
166 | int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width); | |
167 | void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format); | |
168 | void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch, | |
169 | u32 pixel_format, int stride, | |
170 | int u_offset, int v_offset); | |
171 | void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch, | |
172 | u32 pixel_format, int stride, int height); | |
173 | int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc); | |
174 | int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image); | |
175 | ||
aecfbdb1 SH |
176 | /* |
177 | * IPU Display Controller (dc) functions | |
178 | */ | |
179 | struct ipu_dc; | |
180 | struct ipu_di; | |
181 | struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel); | |
182 | void ipu_dc_put(struct ipu_dc *dc); | |
183 | int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced, | |
184 | u32 pixel_fmt, u32 width); | |
1e6d486b | 185 | void ipu_dc_enable(struct ipu_soc *ipu); |
aecfbdb1 SH |
186 | void ipu_dc_enable_channel(struct ipu_dc *dc); |
187 | void ipu_dc_disable_channel(struct ipu_dc *dc); | |
1e6d486b | 188 | void ipu_dc_disable(struct ipu_soc *ipu); |
aecfbdb1 SH |
189 | |
190 | /* | |
191 | * IPU Display Interface (di) functions | |
192 | */ | |
193 | struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp); | |
194 | void ipu_di_put(struct ipu_di *); | |
195 | int ipu_di_disable(struct ipu_di *); | |
196 | int ipu_di_enable(struct ipu_di *); | |
197 | int ipu_di_get_num(struct ipu_di *); | |
198 | int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig); | |
199 | ||
200 | /* | |
201 | * IPU Display Multi FIFO Controller (dmfc) functions | |
202 | */ | |
203 | struct dmfc_channel; | |
204 | int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc); | |
205 | void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc); | |
206 | int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc, | |
207 | unsigned long bandwidth_mbs, int burstsize); | |
208 | void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc); | |
209 | int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width); | |
210 | struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel); | |
211 | void ipu_dmfc_put(struct dmfc_channel *dmfc); | |
212 | ||
213 | /* | |
214 | * IPU Display Processor (dp) functions | |
215 | */ | |
216 | #define IPU_DP_FLOW_SYNC_BG 0 | |
217 | #define IPU_DP_FLOW_SYNC_FG 1 | |
218 | #define IPU_DP_FLOW_ASYNC0_BG 2 | |
219 | #define IPU_DP_FLOW_ASYNC0_FG 3 | |
220 | #define IPU_DP_FLOW_ASYNC1_BG 4 | |
221 | #define IPU_DP_FLOW_ASYNC1_FG 5 | |
222 | ||
223 | struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow); | |
224 | void ipu_dp_put(struct ipu_dp *); | |
285bbb01 | 225 | int ipu_dp_enable(struct ipu_soc *ipu); |
aecfbdb1 SH |
226 | int ipu_dp_enable_channel(struct ipu_dp *dp); |
227 | void ipu_dp_disable_channel(struct ipu_dp *dp); | |
285bbb01 | 228 | void ipu_dp_disable(struct ipu_soc *ipu); |
aecfbdb1 SH |
229 | int ipu_dp_setup_channel(struct ipu_dp *dp, |
230 | enum ipu_color_space in, enum ipu_color_space out); | |
231 | int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos); | |
232 | int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha, | |
233 | bool bg_chan); | |
234 | ||
3f5a8a94 PZ |
235 | /* |
236 | * IPU CMOS Sensor Interface (csi) functions | |
237 | */ | |
2ffd48f2 SL |
238 | struct ipu_csi; |
239 | int ipu_csi_init_interface(struct ipu_csi *csi, | |
240 | struct v4l2_mbus_config *mbus_cfg, | |
241 | struct v4l2_mbus_framefmt *mbus_fmt); | |
242 | bool ipu_csi_is_interlaced(struct ipu_csi *csi); | |
243 | void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w); | |
244 | void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w); | |
245 | void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active, | |
246 | u32 r_value, u32 g_value, u32 b_value, | |
247 | u32 pix_clk); | |
248 | int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc, | |
249 | struct v4l2_mbus_framefmt *mbus_fmt); | |
250 | int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip, | |
251 | u32 max_ratio, u32 id); | |
252 | int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest); | |
253 | int ipu_csi_enable(struct ipu_csi *csi); | |
254 | int ipu_csi_disable(struct ipu_csi *csi); | |
255 | struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id); | |
256 | void ipu_csi_put(struct ipu_csi *csi); | |
257 | void ipu_csi_dump(struct ipu_csi *csi); | |
3f5a8a94 | 258 | |
1aa8ea0d SL |
259 | /* |
260 | * IPU Image Converter (ic) functions | |
261 | */ | |
262 | enum ipu_ic_task { | |
263 | IC_TASK_ENCODER, | |
264 | IC_TASK_VIEWFINDER, | |
265 | IC_TASK_POST_PROCESSOR, | |
266 | IC_NUM_TASKS, | |
267 | }; | |
268 | ||
269 | struct ipu_ic; | |
270 | int ipu_ic_task_init(struct ipu_ic *ic, | |
271 | int in_width, int in_height, | |
272 | int out_width, int out_height, | |
273 | enum ipu_color_space in_cs, | |
274 | enum ipu_color_space out_cs); | |
275 | int ipu_ic_task_graphics_init(struct ipu_ic *ic, | |
276 | enum ipu_color_space in_g_cs, | |
277 | bool galpha_en, u32 galpha, | |
278 | bool colorkey_en, u32 colorkey); | |
279 | void ipu_ic_task_enable(struct ipu_ic *ic); | |
280 | void ipu_ic_task_disable(struct ipu_ic *ic); | |
281 | int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel, | |
282 | u32 width, u32 height, int burst_size, | |
283 | enum ipu_rotate_mode rot); | |
284 | int ipu_ic_enable(struct ipu_ic *ic); | |
285 | int ipu_ic_disable(struct ipu_ic *ic); | |
286 | struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task); | |
287 | void ipu_ic_put(struct ipu_ic *ic); | |
288 | void ipu_ic_dump(struct ipu_ic *ic); | |
289 | ||
35de925f PZ |
290 | /* |
291 | * IPU Sensor Multiple FIFO Controller (SMFC) functions | |
292 | */ | |
7fafa8f0 SL |
293 | struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno); |
294 | void ipu_smfc_put(struct ipu_smfc *smfc); | |
295 | int ipu_smfc_enable(struct ipu_smfc *smfc); | |
296 | int ipu_smfc_disable(struct ipu_smfc *smfc); | |
297 | int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id); | |
298 | int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize); | |
a2be35e3 | 299 | int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level); |
35de925f | 300 | |
7cb17797 | 301 | enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc); |
aecfbdb1 | 302 | enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat); |
ae0e9708 | 303 | enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code); |
4cea940d | 304 | bool ipu_pixelformat_is_planar(u32 pixelformat); |
f835f386 SL |
305 | int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees, |
306 | bool hflip, bool vflip); | |
307 | int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode, | |
308 | bool hflip, bool vflip); | |
aecfbdb1 | 309 | |
aecfbdb1 | 310 | struct ipu_client_platformdata { |
d6ca8ca7 | 311 | int csi; |
aecfbdb1 SH |
312 | int di; |
313 | int dc; | |
314 | int dp; | |
315 | int dmfc; | |
316 | int dma[2]; | |
317 | }; | |
318 | ||
319 | #endif /* __DRM_IPU_H__ */ |