[mirror_ubuntu-bionic-kernel.git] / include / video / omapdss.h

/*
 * Copyright (C) 2008 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __OMAP_OMAPDSS_H
#define __OMAP_OMAPDSS_H

#include <linux/list.h>
#include <linux/kobject.h>
#include <linux/device.h>

#define DISPC_IRQ_FRAMEDONE		(1 << 0)
#define DISPC_IRQ_VSYNC			(1 << 1)
#define DISPC_IRQ_EVSYNC_EVEN		(1 << 2)
#define DISPC_IRQ_EVSYNC_ODD		(1 << 3)
#define DISPC_IRQ_ACBIAS_COUNT_STAT	(1 << 4)
#define DISPC_IRQ_PROG_LINE_NUM		(1 << 5)
#define DISPC_IRQ_GFX_FIFO_UNDERFLOW	(1 << 6)
#define DISPC_IRQ_GFX_END_WIN		(1 << 7)
#define DISPC_IRQ_PAL_GAMMA_MASK	(1 << 8)
#define DISPC_IRQ_OCP_ERR		(1 << 9)
#define DISPC_IRQ_VID1_FIFO_UNDERFLOW	(1 << 10)
#define DISPC_IRQ_VID1_END_WIN		(1 << 11)
#define DISPC_IRQ_VID2_FIFO_UNDERFLOW	(1 << 12)
#define DISPC_IRQ_VID2_END_WIN		(1 << 13)
#define DISPC_IRQ_SYNC_LOST		(1 << 14)
#define DISPC_IRQ_SYNC_LOST_DIGIT	(1 << 15)
#define DISPC_IRQ_WAKEUP		(1 << 16)
#define DISPC_IRQ_SYNC_LOST2		(1 << 17)
#define DISPC_IRQ_VSYNC2		(1 << 18)
#define DISPC_IRQ_ACBIAS_COUNT_STAT2	(1 << 21)
#define DISPC_IRQ_FRAMEDONE2		(1 << 22)

struct omap_dss_device;
struct omap_overlay_manager;

enum omap_display_type {
	OMAP_DISPLAY_TYPE_NONE		= 0,
	OMAP_DISPLAY_TYPE_DPI		= 1 << 0,
	OMAP_DISPLAY_TYPE_DBI		= 1 << 1,
	OMAP_DISPLAY_TYPE_SDI		= 1 << 2,
	OMAP_DISPLAY_TYPE_DSI		= 1 << 3,
	OMAP_DISPLAY_TYPE_VENC		= 1 << 4,
	OMAP_DISPLAY_TYPE_HDMI		= 1 << 5,
};

enum omap_plane {
	OMAP_DSS_GFX	= 0,
	OMAP_DSS_VIDEO1	= 1,
	OMAP_DSS_VIDEO2	= 2
};

enum omap_channel {
	OMAP_DSS_CHANNEL_LCD	= 0,
	OMAP_DSS_CHANNEL_DIGIT	= 1,
	OMAP_DSS_CHANNEL_LCD2	= 2,
};

enum omap_color_mode {
	OMAP_DSS_COLOR_CLUT1	= 1 << 0,  /* BITMAP 1 */
	OMAP_DSS_COLOR_CLUT2	= 1 << 1,  /* BITMAP 2 */
	OMAP_DSS_COLOR_CLUT4	= 1 << 2,  /* BITMAP 4 */
	OMAP_DSS_COLOR_CLUT8	= 1 << 3,  /* BITMAP 8 */
	OMAP_DSS_COLOR_RGB12U	= 1 << 4,  /* RGB12, 16-bit container */
	OMAP_DSS_COLOR_ARGB16	= 1 << 5,  /* ARGB16 */
	OMAP_DSS_COLOR_RGB16	= 1 << 6,  /* RGB16 */
	OMAP_DSS_COLOR_RGB24U	= 1 << 7,  /* RGB24, 32-bit container */
	OMAP_DSS_COLOR_RGB24P	= 1 << 8,  /* RGB24, 24-bit container */
	OMAP_DSS_COLOR_YUV2	= 1 << 9,  /* YUV2 4:2:2 co-sited */
	OMAP_DSS_COLOR_UYVY	= 1 << 10, /* UYVY 4:2:2 co-sited */
	OMAP_DSS_COLOR_ARGB32	= 1 << 11, /* ARGB32 */
	OMAP_DSS_COLOR_RGBA32	= 1 << 12, /* RGBA32 */
	OMAP_DSS_COLOR_RGBX32	= 1 << 13, /* RGBx32 */
	OMAP_DSS_COLOR_NV12		= 1 << 14, /* NV12 format: YUV 4:2:0 */
	OMAP_DSS_COLOR_RGBA16		= 1 << 15, /* RGBA16 - 4444 */
	OMAP_DSS_COLOR_RGBX16		= 1 << 16, /* RGBx16 - 4444 */
	OMAP_DSS_COLOR_ARGB16_1555	= 1 << 17, /* ARGB16 - 1555 */
	OMAP_DSS_COLOR_XRGB16_1555	= 1 << 18, /* xRGB16 - 1555 */
};

enum omap_lcd_display_type {
	OMAP_DSS_LCD_DISPLAY_STN,
	OMAP_DSS_LCD_DISPLAY_TFT,
};

enum omap_dss_load_mode {
	OMAP_DSS_LOAD_CLUT_AND_FRAME	= 0,
	OMAP_DSS_LOAD_CLUT_ONLY		= 1,
	OMAP_DSS_LOAD_FRAME_ONLY	= 2,
	OMAP_DSS_LOAD_CLUT_ONCE_FRAME	= 3,
};

enum omap_dss_trans_key_type {
	OMAP_DSS_COLOR_KEY_GFX_DST = 0,
	OMAP_DSS_COLOR_KEY_VID_SRC = 1,
};

enum omap_rfbi_te_mode {
	OMAP_DSS_RFBI_TE_MODE_1 = 1,
	OMAP_DSS_RFBI_TE_MODE_2 = 2,
};

enum omap_panel_config {
	OMAP_DSS_LCD_IVS		= 1<<0,
	OMAP_DSS_LCD_IHS		= 1<<1,
	OMAP_DSS_LCD_IPC		= 1<<2,
	OMAP_DSS_LCD_IEO		= 1<<3,
	OMAP_DSS_LCD_RF			= 1<<4,
	OMAP_DSS_LCD_ONOFF		= 1<<5,

	OMAP_DSS_LCD_TFT		= 1<<20,
};

enum omap_dss_venc_type {
	OMAP_DSS_VENC_TYPE_COMPOSITE,
	OMAP_DSS_VENC_TYPE_SVIDEO,
};

enum omap_display_caps {
	OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE	= 1 << 0,
	OMAP_DSS_DISPLAY_CAP_TEAR_ELIM		= 1 << 1,
};

enum omap_dss_display_state {
	OMAP_DSS_DISPLAY_DISABLED = 0,
	OMAP_DSS_DISPLAY_ACTIVE,
	OMAP_DSS_DISPLAY_SUSPENDED,
};

/* XXX perhaps this should be removed */
enum omap_dss_overlay_managers {
	OMAP_DSS_OVL_MGR_LCD,
	OMAP_DSS_OVL_MGR_TV,
	OMAP_DSS_OVL_MGR_LCD2,
};

enum omap_dss_rotation_type {
	OMAP_DSS_ROT_DMA = 0,
	OMAP_DSS_ROT_VRFB = 1,
};

/* clockwise rotation angle */
enum omap_dss_rotation_angle {
	OMAP_DSS_ROT_0   = 0,
	OMAP_DSS_ROT_90  = 1,
	OMAP_DSS_ROT_180 = 2,
	OMAP_DSS_ROT_270 = 3,
};

enum omap_overlay_caps {
	OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
	OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
};

enum omap_overlay_manager_caps {
	OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
};

enum omap_dss_clk_source {
	OMAP_DSS_CLK_SRC_FCK = 0,		/* OMAP2/3: DSS1_ALWON_FCLK
						 * OMAP4: DSS_FCLK */
	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,	/* OMAP3: DSI1_PLL_FCLK
						 * OMAP4: PLL1_CLK1 */
	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,	/* OMAP3: DSI2_PLL_FCLK
						 * OMAP4: PLL1_CLK2 */
	OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC,	/* OMAP4: PLL2_CLK1 */
	OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI,	/* OMAP4: PLL2_CLK2 */
};

/* RFBI */

struct rfbi_timings {
	int cs_on_time;
	int cs_off_time;
	int we_on_time;
	int we_off_time;
	int re_on_time;
	int re_off_time;
	int we_cycle_time;
	int re_cycle_time;
	int cs_pulse_width;
	int access_time;

	int clk_div;

	u32 tim[5];             /* set by rfbi_convert_timings() */

	int converted;
};

void omap_rfbi_write_command(const void *buf, u32 len);
void omap_rfbi_read_data(void *buf, u32 len);
void omap_rfbi_write_data(const void *buf, u32 len);
void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
		u16 x, u16 y,
		u16 w, u16 h);
int omap_rfbi_enable_te(bool enable, unsigned line);
int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
			     unsigned hs_pulse_time, unsigned vs_pulse_time,
			     int hs_pol_inv, int vs_pol_inv, int extif_div);
void rfbi_bus_lock(void);
void rfbi_bus_unlock(void);

/* DSI */
void dsi_bus_lock(struct omap_dss_device *dssdev);
void dsi_bus_unlock(struct omap_dss_device *dssdev);
int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
		int len);
int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel,
		u8 dcs_cmd);
int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 param);
int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
		u8 *data, int len);
int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 *buf, int buflen);
int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 *data);
int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 *data1, u8 *data2);
int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
		u16 len);
int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);

/* Board specific data */
struct omap_dss_board_info {
	int (*get_last_off_on_transaction_id)(struct device *dev);
	int num_devices;
	struct omap_dss_device **devices;
	struct omap_dss_device *default_device;
	void (*dsi_mux_pads)(bool enable);
};

#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
/* Init with the board info */
extern int omap_display_init(struct omap_dss_board_info *board_data);
#else
static inline int omap_display_init(struct omap_dss_board_info *board_data)
{
	return 0;
}
#endif

struct omap_display_platform_data {
	struct omap_dss_board_info *board_data;
	/* TODO: Additional members to be added when PM is considered */

	bool (*opt_clock_available)(const char *clk_role);
};

struct omap_video_timings {
	/* Unit: pixels */
	u16 x_res;
	/* Unit: pixels */
	u16 y_res;
	/* Unit: KHz */
	u32 pixel_clock;
	/* Unit: pixel clocks */
	u16 hsw;	/* Horizontal synchronization pulse width */
	/* Unit: pixel clocks */
	u16 hfp;	/* Horizontal front porch */
	/* Unit: pixel clocks */
	u16 hbp;	/* Horizontal back porch */
	/* Unit: line clocks */
	u16 vsw;	/* Vertical synchronization pulse width */
	/* Unit: line clocks */
	u16 vfp;	/* Vertical front porch */
	/* Unit: line clocks */
	u16 vbp;	/* Vertical back porch */
};

#ifdef CONFIG_OMAP2_DSS_VENC
/* Hardcoded timings for tv modes. Venc only uses these to
 * identify the mode, and does not actually use the configs
 * itself. However, the configs should be something that
 * a normal monitor can also show */
extern const struct omap_video_timings omap_dss_pal_timings;
extern const struct omap_video_timings omap_dss_ntsc_timings;
#endif

struct omap_overlay_info {
	bool enabled;

	u32 paddr;
	void __iomem *vaddr;
	u32 p_uv_addr;  /* for NV12 format */
	u16 screen_width;
	u16 width;
	u16 height;
	enum omap_color_mode color_mode;
	u8 rotation;
	enum omap_dss_rotation_type rotation_type;
	bool mirror;

	u16 pos_x;
	u16 pos_y;
	u16 out_width;	/* if 0, out_width == width */
	u16 out_height;	/* if 0, out_height == height */
	u8 global_alpha;
	u8 pre_mult_alpha;
};

struct omap_overlay {
	struct kobject kobj;
	struct list_head list;

	/* static fields */
	const char *name;
	int id;
	enum omap_color_mode supported_modes;
	enum omap_overlay_caps caps;

	/* dynamic fields */
	struct omap_overlay_manager *manager;
	struct omap_overlay_info info;

	/* if true, info has been changed, but not applied() yet */
	bool info_dirty;

	int (*set_manager)(struct omap_overlay *ovl,
		struct omap_overlay_manager *mgr);
	int (*unset_manager)(struct omap_overlay *ovl);

	int (*set_overlay_info)(struct omap_overlay *ovl,
			struct omap_overlay_info *info);
	void (*get_overlay_info)(struct omap_overlay *ovl,
			struct omap_overlay_info *info);

	int (*wait_for_go)(struct omap_overlay *ovl);
};

struct omap_overlay_manager_info {
	u32 default_color;

	enum omap_dss_trans_key_type trans_key_type;
	u32 trans_key;
	bool trans_enabled;

	bool alpha_enabled;
};

struct omap_overlay_manager {
	struct kobject kobj;
	struct list_head list;

	/* static fields */
	const char *name;
	int id;
	enum omap_overlay_manager_caps caps;
	int num_overlays;
	struct omap_overlay **overlays;
	enum omap_display_type supported_displays;

	/* dynamic fields */
	struct omap_dss_device *device;
	struct omap_overlay_manager_info info;

	bool device_changed;
	/* if true, info has been changed but not applied() yet */
	bool info_dirty;

	int (*set_device)(struct omap_overlay_manager *mgr,
		struct omap_dss_device *dssdev);
	int (*unset_device)(struct omap_overlay_manager *mgr);

	int (*set_manager_info)(struct omap_overlay_manager *mgr,
			struct omap_overlay_manager_info *info);
	void (*get_manager_info)(struct omap_overlay_manager *mgr,
			struct omap_overlay_manager_info *info);

	int (*apply)(struct omap_overlay_manager *mgr);
	int (*wait_for_go)(struct omap_overlay_manager *mgr);
	int (*wait_for_vsync)(struct omap_overlay_manager *mgr);

	int (*enable)(struct omap_overlay_manager *mgr);
	int (*disable)(struct omap_overlay_manager *mgr);
};

struct omap_dss_device {
	struct device dev;

	enum omap_display_type type;

	enum omap_channel channel;

	union {
		struct {
			u8 data_lines;
		} dpi;

		struct {
			u8 channel;
			u8 data_lines;
		} rfbi;

		struct {
			u8 datapairs;
		} sdi;

		struct {
			u8 clk_lane;
			u8 clk_pol;
			u8 data1_lane;
			u8 data1_pol;
			u8 data2_lane;
			u8 data2_pol;
			u8 data3_lane;
			u8 data3_pol;
			u8 data4_lane;
			u8 data4_pol;

			int module;

			bool ext_te;
			u8 ext_te_gpio;
		} dsi;

		struct {
			enum omap_dss_venc_type type;
			bool invert_polarity;
		} venc;
	} phy;

	struct {
		struct {
			struct {
				u16 lck_div;
				u16 pck_div;
				enum omap_dss_clk_source lcd_clk_src;
			} channel;

			enum omap_dss_clk_source dispc_fclk_src;
		} dispc;

		struct {
			u16 regn;
			u16 regm;
			u16 regm_dispc;
			u16 regm_dsi;

			u16 lp_clk_div;
			enum omap_dss_clk_source dsi_fclk_src;
		} dsi;

		struct {
			u16 regn;
			u16 regm2;
		} hdmi;
	} clocks;

	struct {
		struct omap_video_timings timings;

		int acbi;	/* ac-bias pin transitions per interrupt */
		/* Unit: line clocks */
		int acb;	/* ac-bias pin frequency */

		enum omap_panel_config config;
	} panel;

	struct {
		u8 pixel_size;
		struct rfbi_timings rfbi_timings;
	} ctrl;

	int reset_gpio;

	int max_backlight_level;

	const char *name;

	/* used to match device to driver */
	const char *driver_name;

	void *data;

	struct omap_dss_driver *driver;

	/* helper variable for driver suspend/resume */
	bool activate_after_resume;

	enum omap_display_caps caps;

	struct omap_overlay_manager *manager;

	enum omap_dss_display_state state;

	/* platform specific  */
	int (*platform_enable)(struct omap_dss_device *dssdev);
	void (*platform_disable)(struct omap_dss_device *dssdev);
	int (*set_backlight)(struct omap_dss_device *dssdev, int level);
	int (*get_backlight)(struct omap_dss_device *dssdev);
};

struct omap_dss_driver {
	struct device_driver driver;

	int (*probe)(struct omap_dss_device *);
	void (*remove)(struct omap_dss_device *);

	int (*enable)(struct omap_dss_device *display);
	void (*disable)(struct omap_dss_device *display);
	int (*suspend)(struct omap_dss_device *display);
	int (*resume)(struct omap_dss_device *display);
	int (*run_test)(struct omap_dss_device *display, int test);

	int (*update)(struct omap_dss_device *dssdev,
			       u16 x, u16 y, u16 w, u16 h);
	int (*sync)(struct omap_dss_device *dssdev);

	int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
	int (*get_te)(struct omap_dss_device *dssdev);

	u8 (*get_rotate)(struct omap_dss_device *dssdev);
	int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);

	bool (*get_mirror)(struct omap_dss_device *dssdev);
	int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);

	int (*memory_read)(struct omap_dss_device *dssdev,
			void *buf, size_t size,
			u16 x, u16 y, u16 w, u16 h);

	void (*get_resolution)(struct omap_dss_device *dssdev,
			u16 *xres, u16 *yres);
	void (*get_dimensions)(struct omap_dss_device *dssdev,
			u32 *width, u32 *height);
	int (*get_recommended_bpp)(struct omap_dss_device *dssdev);

	int (*check_timings)(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);
	void (*set_timings)(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);
	void (*get_timings)(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);

	int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
	u32 (*get_wss)(struct omap_dss_device *dssdev);
};

int omap_dss_register_driver(struct omap_dss_driver *);
void omap_dss_unregister_driver(struct omap_dss_driver *);

void omap_dss_get_device(struct omap_dss_device *dssdev);
void omap_dss_put_device(struct omap_dss_device *dssdev);
#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
struct omap_dss_device *omap_dss_find_device(void *data,
		int (*match)(struct omap_dss_device *dssdev, void *data));

int omap_dss_start_device(struct omap_dss_device *dssdev);
void omap_dss_stop_device(struct omap_dss_device *dssdev);

int omap_dss_get_num_overlay_managers(void);
struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);

int omap_dss_get_num_overlays(void);
struct omap_overlay *omap_dss_get_overlay(int num);

void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
		u16 *xres, u16 *yres);
int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);

typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);

int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
		unsigned long timeout);

#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)

void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
		bool enable);
int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);

int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
				    u16 *x, u16 *y, u16 *w, u16 *h,
				    bool enlarge_update_area);
int omap_dsi_update(struct omap_dss_device *dssdev,
		int channel,
		u16 x, u16 y, u16 w, u16 h,
		void (*callback)(int, void *), void *data);
int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);

int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
		bool disconnect_lanes, bool enter_ulps);

int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
void dpi_set_timings(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);
int dpi_check_timings(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);

int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);

int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
		u16 *x, u16 *y, u16 *w, u16 *h);
int omap_rfbi_update(struct omap_dss_device *dssdev,
		u16 x, u16 y, u16 w, u16 h,
		void (*callback)(void *), void *data);
int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,
		int data_lines);

#endif
Commit	Line	Data
559d6701	1	/*
559d6701 TV	2	* Copyright (C) 2008 Nokia Corporation
	3	* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published by
	7	* the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
a0b38cc4 TV	18	#ifndef __OMAP_OMAPDSS_H
a0b38cc4 TV	19	#define __OMAP_OMAPDSS_H
559d6701 TV	20
	21	#include <linux/list.h>
	22	#include <linux/kobject.h>
	23	#include <linux/device.h>
559d6701 TV	24
	25	#define DISPC_IRQ_FRAMEDONE (1 << 0)
	26	#define DISPC_IRQ_VSYNC (1 << 1)
	27	#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
	28	#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
	29	#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
	30	#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
	31	#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
	32	#define DISPC_IRQ_GFX_END_WIN (1 << 7)
	33	#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
	34	#define DISPC_IRQ_OCP_ERR (1 << 9)
	35	#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
	36	#define DISPC_IRQ_VID1_END_WIN (1 << 11)
	37	#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
	38	#define DISPC_IRQ_VID2_END_WIN (1 << 13)
	39	#define DISPC_IRQ_SYNC_LOST (1 << 14)
	40	#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
	41	#define DISPC_IRQ_WAKEUP (1 << 16)
2a205f34 SS	42	#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
	43	#define DISPC_IRQ_VSYNC2 (1 << 18)
	44	#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
	45	#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
559d6701 TV	46
	47	struct omap_dss_device;
	48	struct omap_overlay_manager;
	49
	50	enum omap_display_type {
	51	OMAP_DISPLAY_TYPE_NONE = 0,
	52	OMAP_DISPLAY_TYPE_DPI = 1 << 0,
	53	OMAP_DISPLAY_TYPE_DBI = 1 << 1,
	54	OMAP_DISPLAY_TYPE_SDI = 1 << 2,
	55	OMAP_DISPLAY_TYPE_DSI = 1 << 3,
	56	OMAP_DISPLAY_TYPE_VENC = 1 << 4,
b119601d	57	OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
559d6701 TV	58	};
	59
	60	enum omap_plane {
	61	OMAP_DSS_GFX = 0,
	62	OMAP_DSS_VIDEO1 = 1,
	63	OMAP_DSS_VIDEO2 = 2
	64	};
	65
	66	enum omap_channel {
	67	OMAP_DSS_CHANNEL_LCD = 0,
	68	OMAP_DSS_CHANNEL_DIGIT = 1,
8613b000	69	OMAP_DSS_CHANNEL_LCD2 = 2,
559d6701 TV	70	};
	71
	72	enum omap_color_mode {
	73	OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
	74	OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
	75	OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
	76	OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
	77	OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
	78	OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
	79	OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
	80	OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
	81	OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
	82	OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
	83	OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
	84	OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
	85	OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
	86	OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
f20e4220 AJ	87	OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
	88	OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
	89	OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
	90	OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
	91	OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
559d6701 TV	92	};
	93
	94	enum omap_lcd_display_type {
	95	OMAP_DSS_LCD_DISPLAY_STN,
	96	OMAP_DSS_LCD_DISPLAY_TFT,
	97	};
	98
	99	enum omap_dss_load_mode {
	100	OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
	101	OMAP_DSS_LOAD_CLUT_ONLY = 1,
	102	OMAP_DSS_LOAD_FRAME_ONLY = 2,
	103	OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
	104	};
	105
	106	enum omap_dss_trans_key_type {
	107	OMAP_DSS_COLOR_KEY_GFX_DST = 0,
	108	OMAP_DSS_COLOR_KEY_VID_SRC = 1,
	109	};
	110
	111	enum omap_rfbi_te_mode {
	112	OMAP_DSS_RFBI_TE_MODE_1 = 1,
	113	OMAP_DSS_RFBI_TE_MODE_2 = 2,
	114	};
	115
	116	enum omap_panel_config {
	117	OMAP_DSS_LCD_IVS = 1<<0,
	118	OMAP_DSS_LCD_IHS = 1<<1,
	119	OMAP_DSS_LCD_IPC = 1<<2,
	120	OMAP_DSS_LCD_IEO = 1<<3,
	121	OMAP_DSS_LCD_RF = 1<<4,
	122	OMAP_DSS_LCD_ONOFF = 1<<5,
	123
	124	OMAP_DSS_LCD_TFT = 1<<20,
	125	};
	126
	127	enum omap_dss_venc_type {
	128	OMAP_DSS_VENC_TYPE_COMPOSITE,
	129	OMAP_DSS_VENC_TYPE_SVIDEO,
	130	};
	131
	132	enum omap_display_caps {
	133	OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
	134	OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
	135	};
	136
559d6701 TV	137	enum omap_dss_display_state {
	138	OMAP_DSS_DISPLAY_DISABLED = 0,
	139	OMAP_DSS_DISPLAY_ACTIVE,
	140	OMAP_DSS_DISPLAY_SUSPENDED,
	141	};
	142
	143	/* XXX perhaps this should be removed */
	144	enum omap_dss_overlay_managers {
	145	OMAP_DSS_OVL_MGR_LCD,
	146	OMAP_DSS_OVL_MGR_TV,
8613b000	147	OMAP_DSS_OVL_MGR_LCD2,
559d6701 TV	148	};
	149
	150	enum omap_dss_rotation_type {
	151	OMAP_DSS_ROT_DMA = 0,
	152	OMAP_DSS_ROT_VRFB = 1,
	153	};
	154
	155	/* clockwise rotation angle */
	156	enum omap_dss_rotation_angle {
	157	OMAP_DSS_ROT_0 = 0,
	158	OMAP_DSS_ROT_90 = 1,
	159	OMAP_DSS_ROT_180 = 2,
	160	OMAP_DSS_ROT_270 = 3,
	161	};
	162
	163	enum omap_overlay_caps {
	164	OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
	165	OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
	166	};
	167
	168	enum omap_overlay_manager_caps {
	169	OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
	170	};
	171
89a35e51 AT	172	enum omap_dss_clk_source {
	173	OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
	174	* OMAP4: DSS_FCLK */
	175	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
	176	* OMAP4: PLL1_CLK1 */
	177	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
	178	* OMAP4: PLL1_CLK2 */
5a8b572d AT	179	OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
5a8b572d AT	180	OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
89a35e51 AT	181	};
89a35e51 AT	182
559d6701 TV	183	/* RFBI */
	184
	185	struct rfbi_timings {
	186	int cs_on_time;
	187	int cs_off_time;
	188	int we_on_time;
	189	int we_off_time;
	190	int re_on_time;
	191	int re_off_time;
	192	int we_cycle_time;
	193	int re_cycle_time;
	194	int cs_pulse_width;
	195	int access_time;
	196
	197	int clk_div;
	198
	199	u32 tim[5]; /* set by rfbi_convert_timings() */
	200
	201	int converted;
	202	};
	203
	204	void omap_rfbi_write_command(const void *buf, u32 len);
	205	void omap_rfbi_read_data(void *buf, u32 len);
	206	void omap_rfbi_write_data(const void *buf, u32 len);
	207	void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
	208	u16 x, u16 y,
	209	u16 w, u16 h);
	210	int omap_rfbi_enable_te(bool enable, unsigned line);
	211	int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
	212	unsigned hs_pulse_time, unsigned vs_pulse_time,
	213	int hs_pol_inv, int vs_pol_inv, int extif_div);
773139f1 TV	214	void rfbi_bus_lock(void);
773139f1 TV	215	void rfbi_bus_unlock(void);
559d6701 TV	216
559d6701 TV	217	/* DSI */
1ffefe75 AT	218	void dsi_bus_lock(struct omap_dss_device *dssdev);
	219	void dsi_bus_unlock(struct omap_dss_device *dssdev);
	220	int dsi_vc_dcs_write(struct omap_dss_device dssdev, int channel, u8 data,
	221	int len);
	222	int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel,
	223	u8 dcs_cmd);
	224	int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
	225	u8 param);
	226	int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
	227	u8 *data, int len);
	228	int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
	229	u8 *buf, int buflen);
	230	int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
	231	u8 *data);
	232	int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
	233	u8 data1, u8 data2);
	234	int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
	235	u16 len);
	236	int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
	237	int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
559d6701 TV	238
	239	/* Board specific data */
	240	struct omap_dss_board_info {
	241	int (get_last_off_on_transaction_id)(struct device dev);
	242	int num_devices;
	243	struct omap_dss_device **devices;
	244	struct omap_dss_device *default_device;
d1f5857e	245	void (*dsi_mux_pads)(bool enable);
559d6701 TV	246	};
559d6701 TV	247
b7ee79ab SS	248	#if defined(CONFIG_OMAP2_DSS_MODULE) \|\| defined(CONFIG_OMAP2_DSS)
	249	/* Init with the board info */
	250	extern int omap_display_init(struct omap_dss_board_info *board_data);
	251	#else
	252	static inline int omap_display_init(struct omap_dss_board_info *board_data)
	253	{
	254	return 0;
	255	}
	256	#endif
	257
cf07f531 SG	258	struct omap_display_platform_data {
	259	struct omap_dss_board_info *board_data;
	260	/* TODO: Additional members to be added when PM is considered */
fd4b34f6 SS	261
fd4b34f6 SS	262	bool (opt_clock_available)(const char clk_role);
cf07f531 SG	263	};
cf07f531 SG	264
559d6701 TV	265	struct omap_video_timings {
	266	/* Unit: pixels */
	267	u16 x_res;
	268	/* Unit: pixels */
	269	u16 y_res;
	270	/* Unit: KHz */
	271	u32 pixel_clock;
	272	/* Unit: pixel clocks */
	273	u16 hsw; /* Horizontal synchronization pulse width */
	274	/* Unit: pixel clocks */
	275	u16 hfp; /* Horizontal front porch */
	276	/* Unit: pixel clocks */
	277	u16 hbp; /* Horizontal back porch */
	278	/* Unit: line clocks */
	279	u16 vsw; /* Vertical synchronization pulse width */
	280	/* Unit: line clocks */
	281	u16 vfp; /* Vertical front porch */
	282	/* Unit: line clocks */
	283	u16 vbp; /* Vertical back porch */
	284	};
	285
	286	#ifdef CONFIG_OMAP2_DSS_VENC
	287	/* Hardcoded timings for tv modes. Venc only uses these to
	288	* identify the mode, and does not actually use the configs
	289	* itself. However, the configs should be something that
	290	* a normal monitor can also show */
5a1819e3 TK	291	extern const struct omap_video_timings omap_dss_pal_timings;
5a1819e3 TK	292	extern const struct omap_video_timings omap_dss_ntsc_timings;
559d6701 TV	293	#endif
	294
	295	struct omap_overlay_info {
	296	bool enabled;
	297
	298	u32 paddr;
	299	void __iomem *vaddr;
0d66cbb5	300	u32 p_uv_addr; /* for NV12 format */
559d6701 TV	301	u16 screen_width;
	302	u16 width;
	303	u16 height;
	304	enum omap_color_mode color_mode;
	305	u8 rotation;
	306	enum omap_dss_rotation_type rotation_type;
	307	bool mirror;
	308
	309	u16 pos_x;
	310	u16 pos_y;
	311	u16 out_width; /* if 0, out_width == width */
	312	u16 out_height; /* if 0, out_height == height */
	313	u8 global_alpha;
fd28a390	314	u8 pre_mult_alpha;
559d6701 TV	315	};
	316
	317	struct omap_overlay {
	318	struct kobject kobj;
	319	struct list_head list;
	320
	321	/* static fields */
	322	const char *name;
	323	int id;
	324	enum omap_color_mode supported_modes;
	325	enum omap_overlay_caps caps;
	326
	327	/* dynamic fields */
	328	struct omap_overlay_manager *manager;
	329	struct omap_overlay_info info;
	330
	331	/* if true, info has been changed, but not applied() yet */
	332	bool info_dirty;
	333
	334	int (set_manager)(struct omap_overlay ovl,
	335	struct omap_overlay_manager *mgr);
	336	int (unset_manager)(struct omap_overlay ovl);
	337
	338	int (set_overlay_info)(struct omap_overlay ovl,
	339	struct omap_overlay_info *info);
	340	void (get_overlay_info)(struct omap_overlay ovl,
	341	struct omap_overlay_info *info);
	342
	343	int (wait_for_go)(struct omap_overlay ovl);
	344	};
	345
	346	struct omap_overlay_manager_info {
	347	u32 default_color;
	348
	349	enum omap_dss_trans_key_type trans_key_type;
	350	u32 trans_key;
	351	bool trans_enabled;
	352
	353	bool alpha_enabled;
	354	};
	355
	356	struct omap_overlay_manager {
	357	struct kobject kobj;
	358	struct list_head list;
	359
	360	/* static fields */
	361	const char *name;
	362	int id;
	363	enum omap_overlay_manager_caps caps;
	364	int num_overlays;
	365	struct omap_overlay **overlays;
	366	enum omap_display_type supported_displays;
	367
	368	/* dynamic fields */
	369	struct omap_dss_device *device;
	370	struct omap_overlay_manager_info info;
	371
	372	bool device_changed;
	373	/* if true, info has been changed but not applied() yet */
	374	bool info_dirty;
	375
	376	int (set_device)(struct omap_overlay_manager mgr,
	377	struct omap_dss_device *dssdev);
	378	int (unset_device)(struct omap_overlay_manager mgr);
379
380	int (set_manager_info)(struct omap_overlay_manager mgr,
381	struct omap_overlay_manager_info *info);
382	void (get_manager_info)(struct omap_overlay_manager mgr,
383	struct omap_overlay_manager_info *info);
384
385	int (apply)(struct omap_overlay_manager mgr);
386	int (wait_for_go)(struct omap_overlay_manager mgr);
3f71cbe7	387	int (wait_for_vsync)(struct omap_overlay_manager mgr);
a2faee84 TV	388
	389	int (enable)(struct omap_overlay_manager mgr);
	390	int (disable)(struct omap_overlay_manager mgr);
559d6701 TV	391	};
	392
	393	struct omap_dss_device {
	394	struct device dev;
	395
	396	enum omap_display_type type;
	397
18faa1b6 SS	398	enum omap_channel channel;
18faa1b6 SS	399
559d6701 TV	400	union {
	401	struct {
	402	u8 data_lines;
	403	} dpi;
	404
	405	struct {
	406	u8 channel;
	407	u8 data_lines;
	408	} rfbi;
	409
	410	struct {
	411	u8 datapairs;
	412	} sdi;
	413
	414	struct {
	415	u8 clk_lane;
	416	u8 clk_pol;
	417	u8 data1_lane;
	418	u8 data1_pol;
	419	u8 data2_lane;
	420	u8 data2_pol;
75d7247c AT	421	u8 data3_lane;
	422	u8 data3_pol;
	423	u8 data4_lane;
	424	u8 data4_pol;
559d6701	425
a72b64b9 AT	426	int module;
a72b64b9 AT	427
559d6701 TV	428	bool ext_te;
	429	u8 ext_te_gpio;
	430	} dsi;
	431
	432	struct {
	433	enum omap_dss_venc_type type;
	434	bool invert_polarity;
	435	} venc;
	436	} phy;
	437
c6940a3d TV	438	struct {
c6940a3d TV	439	struct {
e8881662 AT	440	struct {
	441	u16 lck_div;
	442	u16 pck_div;
	443	enum omap_dss_clk_source lcd_clk_src;
	444	} channel;
	445
	446	enum omap_dss_clk_source dispc_fclk_src;
c6940a3d TV	447	} dispc;
	448
	449	struct {
	450	u16 regn;
	451	u16 regm;
	452	u16 regm_dispc;
	453	u16 regm_dsi;
	454
	455	u16 lp_clk_div;
e8881662	456	enum omap_dss_clk_source dsi_fclk_src;
c6940a3d	457	} dsi;
6cb07b25 AT	458
	459	struct {
	460	u16 regn;
	461	u16 regm2;
	462	} hdmi;
c6940a3d TV	463	} clocks;
c6940a3d TV	464
559d6701 TV	465	struct {
	466	struct omap_video_timings timings;
	467
	468	int acbi; /* ac-bias pin transitions per interrupt */
	469	/* Unit: line clocks */
	470	int acb; /* ac-bias pin frequency */
	471
	472	enum omap_panel_config config;
559d6701 TV	473	} panel;
	474
	475	struct {
	476	u8 pixel_size;
	477	struct rfbi_timings rfbi_timings;
559d6701 TV	478	} ctrl;
	479
	480	int reset_gpio;
	481
	482	int max_backlight_level;
	483
	484	const char *name;
	485
	486	/* used to match device to driver */
	487	const char *driver_name;
	488
	489	void *data;
	490
	491	struct omap_dss_driver *driver;
	492
	493	/* helper variable for driver suspend/resume */
	494	bool activate_after_resume;
	495
	496	enum omap_display_caps caps;
	497
	498	struct omap_overlay_manager *manager;
	499
	500	enum omap_dss_display_state state;
	501
559d6701 TV	502	/* platform specific */
	503	int (platform_enable)(struct omap_dss_device dssdev);
	504	void (platform_disable)(struct omap_dss_device dssdev);
	505	int (set_backlight)(struct omap_dss_device dssdev, int level);
	506	int (get_backlight)(struct omap_dss_device dssdev);
	507	};
	508
	509	struct omap_dss_driver {
	510	struct device_driver driver;
	511
	512	int (probe)(struct omap_dss_device );
	513	void (remove)(struct omap_dss_device );
	514
	515	int (enable)(struct omap_dss_device display);
	516	void (disable)(struct omap_dss_device display);
	517	int (suspend)(struct omap_dss_device display);
	518	int (resume)(struct omap_dss_device display);
	519	int (run_test)(struct omap_dss_device display, int test);
	520
18946f62 TV	521	int (update)(struct omap_dss_device dssdev,
	522	u16 x, u16 y, u16 w, u16 h);
	523	int (sync)(struct omap_dss_device dssdev);
	524
559d6701	525	int (enable_te)(struct omap_dss_device dssdev, bool enable);
225b650d	526	int (get_te)(struct omap_dss_device dssdev);
559d6701 TV	527
	528	u8 (get_rotate)(struct omap_dss_device dssdev);
	529	int (set_rotate)(struct omap_dss_device dssdev, u8 rotate);
	530
	531	bool (get_mirror)(struct omap_dss_device dssdev);
	532	int (set_mirror)(struct omap_dss_device dssdev, bool enable);
	533
	534	int (memory_read)(struct omap_dss_device dssdev,
	535	void *buf, size_t size,
	536	u16 x, u16 y, u16 w, u16 h);
96adcece TV	537
	538	void (get_resolution)(struct omap_dss_device dssdev,
	539	u16 xres, u16 yres);
7a0987bf JN	540	void (get_dimensions)(struct omap_dss_device dssdev,
7a0987bf JN	541	u32 width, u32 height);
a2699504	542	int (get_recommended_bpp)(struct omap_dss_device dssdev);
36511312	543
69b2048f TV	544	int (check_timings)(struct omap_dss_device dssdev,
	545	struct omap_video_timings *timings);
	546	void (set_timings)(struct omap_dss_device dssdev,
	547	struct omap_video_timings *timings);
	548	void (get_timings)(struct omap_dss_device dssdev,
	549	struct omap_video_timings *timings);
	550
36511312 TV	551	int (set_wss)(struct omap_dss_device dssdev, u32 wss);
36511312 TV	552	u32 (get_wss)(struct omap_dss_device dssdev);
559d6701 TV	553	};
	554
	555	int omap_dss_register_driver(struct omap_dss_driver *);
	556	void omap_dss_unregister_driver(struct omap_dss_driver *);
	557
559d6701 TV	558	void omap_dss_get_device(struct omap_dss_device *dssdev);
	559	void omap_dss_put_device(struct omap_dss_device *dssdev);
	560	#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
	561	struct omap_dss_device omap_dss_get_next_device(struct omap_dss_device from);
	562	struct omap_dss_device omap_dss_find_device(void data,
	563	int (match)(struct omap_dss_device dssdev, void *data));
	564
	565	int omap_dss_start_device(struct omap_dss_device *dssdev);
	566	void omap_dss_stop_device(struct omap_dss_device *dssdev);
	567
	568	int omap_dss_get_num_overlay_managers(void);
	569	struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
	570
	571	int omap_dss_get_num_overlays(void);
	572	struct omap_overlay *omap_dss_get_overlay(int num);
	573
96adcece TV	574	void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
96adcece TV	575	u16 xres, u16 yres);
a2699504 TV	576	int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
a2699504 TV	577
559d6701 TV	578	typedef void (omap_dispc_isr_t) (void arg, u32 mask);
	579	int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
	580	int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
	581
	582	int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
	583	int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
	584	unsigned long timeout);
	585
	586	#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
	587	#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
	588
1ffefe75 AT	589	void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
1ffefe75 AT	590	bool enable);
225b650d	591	int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
61140c9a	592
18946f62	593	int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
26a8c250 TV	594	u16 x, u16 y, u16 w, u16 h,
26a8c250 TV	595	bool enlarge_update_area);
18946f62 TV	596	int omap_dsi_update(struct omap_dss_device *dssdev,
	597	int channel,
	598	u16 x, u16 y, u16 w, u16 h,
	599	void (callback)(int, void ), void *data);
5ee3c144 AT	600	int omap_dsi_request_vc(struct omap_dss_device dssdev, int channel);
	601	int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
	602	void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
18946f62	603
37ac60e4	604	int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
2a89dc15	605	void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
22d6d676	606	bool disconnect_lanes, bool enter_ulps);
37ac60e4 TV	607
	608	int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
	609	void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
69b2048f TV	610	void dpi_set_timings(struct omap_dss_device *dssdev,
	611	struct omap_video_timings *timings);
	612	int dpi_check_timings(struct omap_dss_device *dssdev,
	613	struct omap_video_timings *timings);
37ac60e4 TV	614
	615	int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
	616	void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
	617
	618	int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
	619	void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
18946f62 TV	620	int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
	621	u16 x, u16 y, u16 w, u16 h);
	622	int omap_rfbi_update(struct omap_dss_device *dssdev,
	623	u16 x, u16 y, u16 w, u16 h,
	624	void (callback)(void ), void *data);
1d5952a8 TV	625	int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,
1d5952a8 TV	626	int data_lines);
18946f62	627
559d6701	628	#endif