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Commit | Line | Data |
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559d6701 | 1 | /* |
559d6701 TV |
2 | * Copyright (C) 2008 Nokia Corporation |
3 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
a0b38cc4 TV |
18 | #ifndef __OMAP_OMAPDSS_H |
19 | #define __OMAP_OMAPDSS_H | |
559d6701 TV |
20 | |
21 | #include <linux/list.h> | |
22 | #include <linux/kobject.h> | |
23 | #include <linux/device.h> | |
559d6701 TV |
24 | |
25 | #define DISPC_IRQ_FRAMEDONE (1 << 0) | |
26 | #define DISPC_IRQ_VSYNC (1 << 1) | |
27 | #define DISPC_IRQ_EVSYNC_EVEN (1 << 2) | |
28 | #define DISPC_IRQ_EVSYNC_ODD (1 << 3) | |
29 | #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4) | |
30 | #define DISPC_IRQ_PROG_LINE_NUM (1 << 5) | |
31 | #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6) | |
32 | #define DISPC_IRQ_GFX_END_WIN (1 << 7) | |
33 | #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8) | |
34 | #define DISPC_IRQ_OCP_ERR (1 << 9) | |
35 | #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10) | |
36 | #define DISPC_IRQ_VID1_END_WIN (1 << 11) | |
37 | #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12) | |
38 | #define DISPC_IRQ_VID2_END_WIN (1 << 13) | |
39 | #define DISPC_IRQ_SYNC_LOST (1 << 14) | |
40 | #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15) | |
41 | #define DISPC_IRQ_WAKEUP (1 << 16) | |
2a205f34 SS |
42 | #define DISPC_IRQ_SYNC_LOST2 (1 << 17) |
43 | #define DISPC_IRQ_VSYNC2 (1 << 18) | |
b8c095b4 AT |
44 | #define DISPC_IRQ_VID3_END_WIN (1 << 19) |
45 | #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) | |
2a205f34 SS |
46 | #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) |
47 | #define DISPC_IRQ_FRAMEDONE2 (1 << 22) | |
7f6f3c4b TV |
48 | #define DISPC_IRQ_FRAMEDONEWB (1 << 23) |
49 | #define DISPC_IRQ_FRAMEDONETV (1 << 24) | |
50 | #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25) | |
14d33d38 CM |
51 | #define DISPC_IRQ_SYNC_LOST3 (1 << 27) |
52 | #define DISPC_IRQ_VSYNC3 (1 << 28) | |
53 | #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29) | |
54 | #define DISPC_IRQ_FRAMEDONE3 (1 << 30) | |
559d6701 TV |
55 | |
56 | struct omap_dss_device; | |
57 | struct omap_overlay_manager; | |
9c0b8420 RN |
58 | struct snd_aes_iec958; |
59 | struct snd_cea_861_aud_if; | |
559d6701 TV |
60 | |
61 | enum omap_display_type { | |
62 | OMAP_DISPLAY_TYPE_NONE = 0, | |
63 | OMAP_DISPLAY_TYPE_DPI = 1 << 0, | |
64 | OMAP_DISPLAY_TYPE_DBI = 1 << 1, | |
65 | OMAP_DISPLAY_TYPE_SDI = 1 << 2, | |
66 | OMAP_DISPLAY_TYPE_DSI = 1 << 3, | |
67 | OMAP_DISPLAY_TYPE_VENC = 1 << 4, | |
b119601d | 68 | OMAP_DISPLAY_TYPE_HDMI = 1 << 5, |
559d6701 TV |
69 | }; |
70 | ||
71 | enum omap_plane { | |
72 | OMAP_DSS_GFX = 0, | |
73 | OMAP_DSS_VIDEO1 = 1, | |
b8c095b4 AT |
74 | OMAP_DSS_VIDEO2 = 2, |
75 | OMAP_DSS_VIDEO3 = 3, | |
66a0f9e4 | 76 | OMAP_DSS_WB = 4, |
559d6701 TV |
77 | }; |
78 | ||
79 | enum omap_channel { | |
80 | OMAP_DSS_CHANNEL_LCD = 0, | |
81 | OMAP_DSS_CHANNEL_DIGIT = 1, | |
8613b000 | 82 | OMAP_DSS_CHANNEL_LCD2 = 2, |
ff6331e2 | 83 | OMAP_DSS_CHANNEL_LCD3 = 3, |
559d6701 TV |
84 | }; |
85 | ||
86 | enum omap_color_mode { | |
87 | OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */ | |
88 | OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */ | |
89 | OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */ | |
90 | OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */ | |
91 | OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */ | |
92 | OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */ | |
93 | OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */ | |
94 | OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */ | |
95 | OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */ | |
96 | OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */ | |
97 | OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */ | |
98 | OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */ | |
99 | OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */ | |
100 | OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */ | |
f20e4220 AJ |
101 | OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */ |
102 | OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */ | |
103 | OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */ | |
104 | OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */ | |
105 | OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */ | |
559d6701 TV |
106 | }; |
107 | ||
559d6701 TV |
108 | enum omap_dss_load_mode { |
109 | OMAP_DSS_LOAD_CLUT_AND_FRAME = 0, | |
110 | OMAP_DSS_LOAD_CLUT_ONLY = 1, | |
111 | OMAP_DSS_LOAD_FRAME_ONLY = 2, | |
112 | OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3, | |
113 | }; | |
114 | ||
115 | enum omap_dss_trans_key_type { | |
116 | OMAP_DSS_COLOR_KEY_GFX_DST = 0, | |
117 | OMAP_DSS_COLOR_KEY_VID_SRC = 1, | |
118 | }; | |
119 | ||
120 | enum omap_rfbi_te_mode { | |
121 | OMAP_DSS_RFBI_TE_MODE_1 = 1, | |
122 | OMAP_DSS_RFBI_TE_MODE_2 = 2, | |
123 | }; | |
124 | ||
a8d5e41c AT |
125 | enum omap_dss_signal_level { |
126 | OMAPDSS_SIG_ACTIVE_HIGH = 0, | |
127 | OMAPDSS_SIG_ACTIVE_LOW = 1, | |
128 | }; | |
129 | ||
130 | enum omap_dss_signal_edge { | |
131 | OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES, | |
132 | OMAPDSS_DRIVE_SIG_RISING_EDGE, | |
133 | OMAPDSS_DRIVE_SIG_FALLING_EDGE, | |
134 | }; | |
135 | ||
559d6701 TV |
136 | enum omap_dss_venc_type { |
137 | OMAP_DSS_VENC_TYPE_COMPOSITE, | |
138 | OMAP_DSS_VENC_TYPE_SVIDEO, | |
139 | }; | |
140 | ||
a3b3cc2b AT |
141 | enum omap_dss_dsi_pixel_format { |
142 | OMAP_DSS_DSI_FMT_RGB888, | |
143 | OMAP_DSS_DSI_FMT_RGB666, | |
144 | OMAP_DSS_DSI_FMT_RGB666_PACKED, | |
145 | OMAP_DSS_DSI_FMT_RGB565, | |
146 | }; | |
147 | ||
7e951ee9 AT |
148 | enum omap_dss_dsi_mode { |
149 | OMAP_DSS_DSI_CMD_MODE = 0, | |
150 | OMAP_DSS_DSI_VIDEO_MODE, | |
151 | }; | |
152 | ||
559d6701 TV |
153 | enum omap_display_caps { |
154 | OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0, | |
155 | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1, | |
156 | }; | |
157 | ||
559d6701 TV |
158 | enum omap_dss_display_state { |
159 | OMAP_DSS_DISPLAY_DISABLED = 0, | |
160 | OMAP_DSS_DISPLAY_ACTIVE, | |
559d6701 TV |
161 | }; |
162 | ||
9c0b8420 RN |
163 | enum omap_dss_audio_state { |
164 | OMAP_DSS_AUDIO_DISABLED = 0, | |
165 | OMAP_DSS_AUDIO_ENABLED, | |
166 | OMAP_DSS_AUDIO_CONFIGURED, | |
167 | OMAP_DSS_AUDIO_PLAYING, | |
168 | }; | |
169 | ||
559d6701 | 170 | enum omap_dss_rotation_type { |
65e006ff CM |
171 | OMAP_DSS_ROT_DMA = 1 << 0, |
172 | OMAP_DSS_ROT_VRFB = 1 << 1, | |
173 | OMAP_DSS_ROT_TILER = 1 << 2, | |
559d6701 TV |
174 | }; |
175 | ||
176 | /* clockwise rotation angle */ | |
177 | enum omap_dss_rotation_angle { | |
178 | OMAP_DSS_ROT_0 = 0, | |
179 | OMAP_DSS_ROT_90 = 1, | |
180 | OMAP_DSS_ROT_180 = 2, | |
181 | OMAP_DSS_ROT_270 = 3, | |
182 | }; | |
183 | ||
184 | enum omap_overlay_caps { | |
185 | OMAP_DSS_OVL_CAP_SCALE = 1 << 0, | |
f6dc8150 TV |
186 | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1, |
187 | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2, | |
11354dd5 | 188 | OMAP_DSS_OVL_CAP_ZORDER = 1 << 3, |
d79db853 AT |
189 | OMAP_DSS_OVL_CAP_POS = 1 << 4, |
190 | OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5, | |
559d6701 TV |
191 | }; |
192 | ||
193 | enum omap_overlay_manager_caps { | |
4a9e78ab | 194 | OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */ |
559d6701 TV |
195 | }; |
196 | ||
89a35e51 AT |
197 | enum omap_dss_clk_source { |
198 | OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK | |
199 | * OMAP4: DSS_FCLK */ | |
200 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK | |
201 | * OMAP4: PLL1_CLK1 */ | |
202 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK | |
203 | * OMAP4: PLL1_CLK2 */ | |
5a8b572d AT |
204 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */ |
205 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */ | |
89a35e51 AT |
206 | }; |
207 | ||
9a901683 M |
208 | enum omap_hdmi_flags { |
209 | OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0, | |
210 | }; | |
211 | ||
484dc404 AT |
212 | enum omap_dss_output_id { |
213 | OMAP_DSS_OUTPUT_DPI = 1 << 0, | |
214 | OMAP_DSS_OUTPUT_DBI = 1 << 1, | |
215 | OMAP_DSS_OUTPUT_SDI = 1 << 2, | |
216 | OMAP_DSS_OUTPUT_DSI1 = 1 << 3, | |
217 | OMAP_DSS_OUTPUT_DSI2 = 1 << 4, | |
218 | OMAP_DSS_OUTPUT_VENC = 1 << 5, | |
219 | OMAP_DSS_OUTPUT_HDMI = 1 << 6, | |
220 | }; | |
221 | ||
559d6701 TV |
222 | /* RFBI */ |
223 | ||
224 | struct rfbi_timings { | |
225 | int cs_on_time; | |
226 | int cs_off_time; | |
227 | int we_on_time; | |
228 | int we_off_time; | |
229 | int re_on_time; | |
230 | int re_off_time; | |
231 | int we_cycle_time; | |
232 | int re_cycle_time; | |
233 | int cs_pulse_width; | |
234 | int access_time; | |
235 | ||
236 | int clk_div; | |
237 | ||
238 | u32 tim[5]; /* set by rfbi_convert_timings() */ | |
239 | ||
240 | int converted; | |
241 | }; | |
242 | ||
243 | void omap_rfbi_write_command(const void *buf, u32 len); | |
244 | void omap_rfbi_read_data(void *buf, u32 len); | |
245 | void omap_rfbi_write_data(const void *buf, u32 len); | |
246 | void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width, | |
247 | u16 x, u16 y, | |
248 | u16 w, u16 h); | |
249 | int omap_rfbi_enable_te(bool enable, unsigned line); | |
250 | int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode, | |
251 | unsigned hs_pulse_time, unsigned vs_pulse_time, | |
252 | int hs_pol_inv, int vs_pol_inv, int extif_div); | |
773139f1 TV |
253 | void rfbi_bus_lock(void); |
254 | void rfbi_bus_unlock(void); | |
559d6701 TV |
255 | |
256 | /* DSI */ | |
8af6ff01 | 257 | |
6b849375 | 258 | struct omap_dss_dsi_videomode_timings { |
8af6ff01 AT |
259 | /* DSI video mode blanking data */ |
260 | /* Unit: byte clock cycles */ | |
261 | u16 hsa; | |
262 | u16 hfp; | |
263 | u16 hbp; | |
264 | /* Unit: line clocks */ | |
265 | u16 vsa; | |
266 | u16 vfp; | |
267 | u16 vbp; | |
268 | ||
269 | /* DSI blanking modes */ | |
270 | int blanking_mode; | |
271 | int hsa_blanking_mode; | |
272 | int hbp_blanking_mode; | |
273 | int hfp_blanking_mode; | |
274 | ||
275 | /* Video port sync events */ | |
8af6ff01 AT |
276 | bool vp_vsync_end; |
277 | bool vp_hsync_end; | |
278 | ||
279 | bool ddr_clk_always_on; | |
280 | int window_sync; | |
281 | }; | |
282 | ||
1ffefe75 AT |
283 | void dsi_bus_lock(struct omap_dss_device *dssdev); |
284 | void dsi_bus_unlock(struct omap_dss_device *dssdev); | |
285 | int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, | |
286 | int len); | |
6ff8aa31 AT |
287 | int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, |
288 | int len); | |
289 | int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd); | |
290 | int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel); | |
1ffefe75 AT |
291 | int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
292 | u8 param); | |
6ff8aa31 AT |
293 | int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel, |
294 | u8 param); | |
295 | int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel, | |
296 | u8 param1, u8 param2); | |
1ffefe75 AT |
297 | int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, |
298 | u8 *data, int len); | |
6ff8aa31 AT |
299 | int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, |
300 | u8 *data, int len); | |
1ffefe75 AT |
301 | int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
302 | u8 *buf, int buflen); | |
b3b89c05 AT |
303 | int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf, |
304 | int buflen); | |
305 | int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param, | |
306 | u8 *buf, int buflen); | |
307 | int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel, | |
308 | u8 param1, u8 param2, u8 *buf, int buflen); | |
1ffefe75 AT |
309 | int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, |
310 | u16 len); | |
311 | int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); | |
312 | int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel); | |
9a147a65 TV |
313 | int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel); |
314 | void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel); | |
559d6701 | 315 | |
acd18af9 TV |
316 | enum omapdss_version { |
317 | OMAPDSS_VER_UNKNOWN = 0, | |
318 | OMAPDSS_VER_OMAP24xx, | |
319 | OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */ | |
320 | OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */ | |
321 | OMAPDSS_VER_OMAP3630, | |
322 | OMAPDSS_VER_AM35xx, | |
323 | OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */ | |
324 | OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */ | |
325 | OMAPDSS_VER_OMAP4, /* All other OMAP4s */ | |
326 | OMAPDSS_VER_OMAP5, | |
327 | }; | |
328 | ||
559d6701 TV |
329 | /* Board specific data */ |
330 | struct omap_dss_board_info { | |
aac927c9 | 331 | int (*get_context_loss_count)(struct device *dev); |
559d6701 TV |
332 | int num_devices; |
333 | struct omap_dss_device **devices; | |
334 | struct omap_dss_device *default_device; | |
5bc416cb TV |
335 | int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask); |
336 | void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask); | |
62c1dcfc | 337 | int (*set_min_bus_tput)(struct device *dev, unsigned long r); |
acd18af9 | 338 | enum omapdss_version version; |
559d6701 TV |
339 | }; |
340 | ||
b7ee79ab SS |
341 | /* Init with the board info */ |
342 | extern int omap_display_init(struct omap_dss_board_info *board_data); | |
ee9dfd82 | 343 | /* HDMI mux init*/ |
9a901683 | 344 | extern int omap_hdmi_init(enum omap_hdmi_flags flags); |
b7ee79ab | 345 | |
559d6701 TV |
346 | struct omap_video_timings { |
347 | /* Unit: pixels */ | |
348 | u16 x_res; | |
349 | /* Unit: pixels */ | |
350 | u16 y_res; | |
351 | /* Unit: KHz */ | |
352 | u32 pixel_clock; | |
353 | /* Unit: pixel clocks */ | |
354 | u16 hsw; /* Horizontal synchronization pulse width */ | |
355 | /* Unit: pixel clocks */ | |
356 | u16 hfp; /* Horizontal front porch */ | |
357 | /* Unit: pixel clocks */ | |
358 | u16 hbp; /* Horizontal back porch */ | |
359 | /* Unit: line clocks */ | |
360 | u16 vsw; /* Vertical synchronization pulse width */ | |
361 | /* Unit: line clocks */ | |
362 | u16 vfp; /* Vertical front porch */ | |
363 | /* Unit: line clocks */ | |
364 | u16 vbp; /* Vertical back porch */ | |
a8d5e41c AT |
365 | |
366 | /* Vsync logic level */ | |
367 | enum omap_dss_signal_level vsync_level; | |
368 | /* Hsync logic level */ | |
369 | enum omap_dss_signal_level hsync_level; | |
23c8f88e AT |
370 | /* Interlaced or Progressive timings */ |
371 | bool interlace; | |
a8d5e41c AT |
372 | /* Pixel clock edge to drive LCD data */ |
373 | enum omap_dss_signal_edge data_pclk_edge; | |
374 | /* Data enable logic level */ | |
375 | enum omap_dss_signal_level de_level; | |
376 | /* Pixel clock edges to drive HSYNC and VSYNC signals */ | |
377 | enum omap_dss_signal_edge sync_pclk_edge; | |
559d6701 TV |
378 | }; |
379 | ||
380 | #ifdef CONFIG_OMAP2_DSS_VENC | |
381 | /* Hardcoded timings for tv modes. Venc only uses these to | |
382 | * identify the mode, and does not actually use the configs | |
383 | * itself. However, the configs should be something that | |
384 | * a normal monitor can also show */ | |
5a1819e3 TK |
385 | extern const struct omap_video_timings omap_dss_pal_timings; |
386 | extern const struct omap_video_timings omap_dss_ntsc_timings; | |
559d6701 TV |
387 | #endif |
388 | ||
3c07cae2 TV |
389 | struct omap_dss_cpr_coefs { |
390 | s16 rr, rg, rb; | |
391 | s16 gr, gg, gb; | |
392 | s16 br, bg, bb; | |
393 | }; | |
394 | ||
559d6701 | 395 | struct omap_overlay_info { |
559d6701 | 396 | u32 paddr; |
0d66cbb5 | 397 | u32 p_uv_addr; /* for NV12 format */ |
559d6701 TV |
398 | u16 screen_width; |
399 | u16 width; | |
400 | u16 height; | |
401 | enum omap_color_mode color_mode; | |
402 | u8 rotation; | |
403 | enum omap_dss_rotation_type rotation_type; | |
404 | bool mirror; | |
405 | ||
406 | u16 pos_x; | |
407 | u16 pos_y; | |
408 | u16 out_width; /* if 0, out_width == width */ | |
409 | u16 out_height; /* if 0, out_height == height */ | |
410 | u8 global_alpha; | |
fd28a390 | 411 | u8 pre_mult_alpha; |
54128701 | 412 | u8 zorder; |
559d6701 TV |
413 | }; |
414 | ||
415 | struct omap_overlay { | |
416 | struct kobject kobj; | |
417 | struct list_head list; | |
418 | ||
419 | /* static fields */ | |
420 | const char *name; | |
4a9e78ab | 421 | enum omap_plane id; |
559d6701 TV |
422 | enum omap_color_mode supported_modes; |
423 | enum omap_overlay_caps caps; | |
424 | ||
425 | /* dynamic fields */ | |
426 | struct omap_overlay_manager *manager; | |
559d6701 | 427 | |
9d11c321 TV |
428 | /* |
429 | * The following functions do not block: | |
430 | * | |
431 | * is_enabled | |
432 | * set_overlay_info | |
433 | * get_overlay_info | |
434 | * | |
435 | * The rest of the functions may block and cannot be called from | |
436 | * interrupt context | |
437 | */ | |
438 | ||
aaa874a9 TV |
439 | int (*enable)(struct omap_overlay *ovl); |
440 | int (*disable)(struct omap_overlay *ovl); | |
441 | bool (*is_enabled)(struct omap_overlay *ovl); | |
442 | ||
559d6701 TV |
443 | int (*set_manager)(struct omap_overlay *ovl, |
444 | struct omap_overlay_manager *mgr); | |
445 | int (*unset_manager)(struct omap_overlay *ovl); | |
446 | ||
447 | int (*set_overlay_info)(struct omap_overlay *ovl, | |
448 | struct omap_overlay_info *info); | |
449 | void (*get_overlay_info)(struct omap_overlay *ovl, | |
450 | struct omap_overlay_info *info); | |
451 | ||
452 | int (*wait_for_go)(struct omap_overlay *ovl); | |
794bc4ee AT |
453 | |
454 | struct omap_dss_device *(*get_device)(struct omap_overlay *ovl); | |
559d6701 TV |
455 | }; |
456 | ||
457 | struct omap_overlay_manager_info { | |
458 | u32 default_color; | |
459 | ||
460 | enum omap_dss_trans_key_type trans_key_type; | |
461 | u32 trans_key; | |
462 | bool trans_enabled; | |
463 | ||
11354dd5 | 464 | bool partial_alpha_enabled; |
3c07cae2 TV |
465 | |
466 | bool cpr_enable; | |
467 | struct omap_dss_cpr_coefs cpr_coefs; | |
559d6701 TV |
468 | }; |
469 | ||
470 | struct omap_overlay_manager { | |
471 | struct kobject kobj; | |
559d6701 TV |
472 | |
473 | /* static fields */ | |
474 | const char *name; | |
4a9e78ab | 475 | enum omap_channel id; |
559d6701 | 476 | enum omap_overlay_manager_caps caps; |
07e327c9 | 477 | struct list_head overlays; |
559d6701 | 478 | enum omap_display_type supported_displays; |
97f01b3a | 479 | enum omap_dss_output_id supported_outputs; |
559d6701 TV |
480 | |
481 | /* dynamic fields */ | |
97f01b3a | 482 | struct omap_dss_output *output; |
559d6701 | 483 | |
9d11c321 TV |
484 | /* |
485 | * The following functions do not block: | |
486 | * | |
487 | * set_manager_info | |
488 | * get_manager_info | |
489 | * apply | |
490 | * | |
491 | * The rest of the functions may block and cannot be called from | |
492 | * interrupt context | |
493 | */ | |
494 | ||
97f01b3a AT |
495 | int (*set_output)(struct omap_overlay_manager *mgr, |
496 | struct omap_dss_output *output); | |
497 | int (*unset_output)(struct omap_overlay_manager *mgr); | |
559d6701 TV |
498 | |
499 | int (*set_manager_info)(struct omap_overlay_manager *mgr, | |
500 | struct omap_overlay_manager_info *info); | |
501 | void (*get_manager_info)(struct omap_overlay_manager *mgr, | |
502 | struct omap_overlay_manager_info *info); | |
503 | ||
504 | int (*apply)(struct omap_overlay_manager *mgr); | |
505 | int (*wait_for_go)(struct omap_overlay_manager *mgr); | |
3f71cbe7 | 506 | int (*wait_for_vsync)(struct omap_overlay_manager *mgr); |
794bc4ee AT |
507 | |
508 | struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr); | |
559d6701 TV |
509 | }; |
510 | ||
e4a9e94c TV |
511 | /* 22 pins means 1 clk lane and 10 data lanes */ |
512 | #define OMAP_DSS_MAX_DSI_PINS 22 | |
513 | ||
514 | struct omap_dsi_pin_config { | |
515 | int num_pins; | |
516 | /* | |
517 | * pin numbers in the following order: | |
518 | * clk+, clk- | |
519 | * data1+, data1- | |
520 | * data2+, data2- | |
521 | * ... | |
522 | */ | |
523 | int pins[OMAP_DSS_MAX_DSI_PINS]; | |
524 | }; | |
525 | ||
749feffa AT |
526 | struct omap_dss_writeback_info { |
527 | u32 paddr; | |
528 | u32 p_uv_addr; | |
529 | u16 buf_width; | |
530 | u16 width; | |
531 | u16 height; | |
532 | enum omap_color_mode color_mode; | |
533 | u8 rotation; | |
534 | enum omap_dss_rotation_type rotation_type; | |
535 | bool mirror; | |
536 | u8 pre_mult_alpha; | |
537 | }; | |
538 | ||
484dc404 AT |
539 | struct omap_dss_output { |
540 | struct list_head list; | |
541 | ||
542 | /* display type supported by the output */ | |
543 | enum omap_display_type type; | |
544 | ||
545 | /* output instance */ | |
546 | enum omap_dss_output_id id; | |
547 | ||
548 | /* output's platform device pointer */ | |
549 | struct platform_device *pdev; | |
550 | ||
551 | /* dynamic fields */ | |
552 | struct omap_overlay_manager *manager; | |
553 | ||
554 | struct omap_dss_device *device; | |
555 | }; | |
556 | ||
559d6701 TV |
557 | struct omap_dss_device { |
558 | struct device dev; | |
559 | ||
560 | enum omap_display_type type; | |
561 | ||
18faa1b6 SS |
562 | enum omap_channel channel; |
563 | ||
559d6701 TV |
564 | union { |
565 | struct { | |
566 | u8 data_lines; | |
567 | } dpi; | |
568 | ||
569 | struct { | |
570 | u8 channel; | |
571 | u8 data_lines; | |
572 | } rfbi; | |
573 | ||
574 | struct { | |
575 | u8 datapairs; | |
576 | } sdi; | |
577 | ||
578 | struct { | |
a72b64b9 AT |
579 | int module; |
580 | ||
559d6701 TV |
581 | bool ext_te; |
582 | u8 ext_te_gpio; | |
583 | } dsi; | |
584 | ||
585 | struct { | |
586 | enum omap_dss_venc_type type; | |
587 | bool invert_polarity; | |
588 | } venc; | |
589 | } phy; | |
590 | ||
c6940a3d TV |
591 | struct { |
592 | struct { | |
e8881662 AT |
593 | struct { |
594 | u16 lck_div; | |
595 | u16 pck_div; | |
596 | enum omap_dss_clk_source lcd_clk_src; | |
597 | } channel; | |
598 | ||
599 | enum omap_dss_clk_source dispc_fclk_src; | |
c6940a3d TV |
600 | } dispc; |
601 | ||
602 | struct { | |
c90a78ec | 603 | /* regn is one greater than TRM's REGN value */ |
c6940a3d TV |
604 | u16 regn; |
605 | u16 regm; | |
606 | u16 regm_dispc; | |
607 | u16 regm_dsi; | |
608 | ||
609 | u16 lp_clk_div; | |
e8881662 | 610 | enum omap_dss_clk_source dsi_fclk_src; |
c6940a3d | 611 | } dsi; |
6cb07b25 AT |
612 | |
613 | struct { | |
b44e4582 | 614 | /* regn is one greater than TRM's REGN value */ |
6cb07b25 AT |
615 | u16 regn; |
616 | u16 regm2; | |
617 | } hdmi; | |
c6940a3d TV |
618 | } clocks; |
619 | ||
559d6701 TV |
620 | struct { |
621 | struct omap_video_timings timings; | |
622 | ||
a3b3cc2b | 623 | enum omap_dss_dsi_pixel_format dsi_pix_fmt; |
7e951ee9 | 624 | enum omap_dss_dsi_mode dsi_mode; |
6b849375 | 625 | struct omap_dss_dsi_videomode_timings dsi_vm_timings; |
559d6701 TV |
626 | } panel; |
627 | ||
628 | struct { | |
629 | u8 pixel_size; | |
630 | struct rfbi_timings rfbi_timings; | |
559d6701 TV |
631 | } ctrl; |
632 | ||
633 | int reset_gpio; | |
634 | ||
635 | int max_backlight_level; | |
636 | ||
637 | const char *name; | |
638 | ||
639 | /* used to match device to driver */ | |
640 | const char *driver_name; | |
641 | ||
642 | void *data; | |
643 | ||
644 | struct omap_dss_driver *driver; | |
645 | ||
646 | /* helper variable for driver suspend/resume */ | |
647 | bool activate_after_resume; | |
648 | ||
649 | enum omap_display_caps caps; | |
650 | ||
6d71b923 | 651 | struct omap_dss_output *output; |
559d6701 TV |
652 | |
653 | enum omap_dss_display_state state; | |
654 | ||
9c0b8420 RN |
655 | enum omap_dss_audio_state audio_state; |
656 | ||
559d6701 TV |
657 | /* platform specific */ |
658 | int (*platform_enable)(struct omap_dss_device *dssdev); | |
659 | void (*platform_disable)(struct omap_dss_device *dssdev); | |
660 | int (*set_backlight)(struct omap_dss_device *dssdev, int level); | |
661 | int (*get_backlight)(struct omap_dss_device *dssdev); | |
662 | }; | |
663 | ||
c49d005b TV |
664 | struct omap_dss_hdmi_data |
665 | { | |
cca35017 TV |
666 | int ct_cp_hpd_gpio; |
667 | int ls_oe_gpio; | |
c49d005b TV |
668 | int hpd_gpio; |
669 | }; | |
670 | ||
9c0b8420 RN |
671 | struct omap_dss_audio { |
672 | struct snd_aes_iec958 *iec; | |
673 | struct snd_cea_861_aud_if *cea; | |
674 | }; | |
675 | ||
559d6701 TV |
676 | struct omap_dss_driver { |
677 | struct device_driver driver; | |
678 | ||
679 | int (*probe)(struct omap_dss_device *); | |
680 | void (*remove)(struct omap_dss_device *); | |
681 | ||
682 | int (*enable)(struct omap_dss_device *display); | |
683 | void (*disable)(struct omap_dss_device *display); | |
559d6701 TV |
684 | int (*run_test)(struct omap_dss_device *display, int test); |
685 | ||
18946f62 TV |
686 | int (*update)(struct omap_dss_device *dssdev, |
687 | u16 x, u16 y, u16 w, u16 h); | |
688 | int (*sync)(struct omap_dss_device *dssdev); | |
689 | ||
559d6701 | 690 | int (*enable_te)(struct omap_dss_device *dssdev, bool enable); |
225b650d | 691 | int (*get_te)(struct omap_dss_device *dssdev); |
559d6701 TV |
692 | |
693 | u8 (*get_rotate)(struct omap_dss_device *dssdev); | |
694 | int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate); | |
695 | ||
696 | bool (*get_mirror)(struct omap_dss_device *dssdev); | |
697 | int (*set_mirror)(struct omap_dss_device *dssdev, bool enable); | |
698 | ||
699 | int (*memory_read)(struct omap_dss_device *dssdev, | |
700 | void *buf, size_t size, | |
701 | u16 x, u16 y, u16 w, u16 h); | |
96adcece TV |
702 | |
703 | void (*get_resolution)(struct omap_dss_device *dssdev, | |
704 | u16 *xres, u16 *yres); | |
7a0987bf JN |
705 | void (*get_dimensions)(struct omap_dss_device *dssdev, |
706 | u32 *width, u32 *height); | |
a2699504 | 707 | int (*get_recommended_bpp)(struct omap_dss_device *dssdev); |
36511312 | 708 | |
69b2048f TV |
709 | int (*check_timings)(struct omap_dss_device *dssdev, |
710 | struct omap_video_timings *timings); | |
711 | void (*set_timings)(struct omap_dss_device *dssdev, | |
712 | struct omap_video_timings *timings); | |
713 | void (*get_timings)(struct omap_dss_device *dssdev, | |
714 | struct omap_video_timings *timings); | |
715 | ||
36511312 TV |
716 | int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); |
717 | u32 (*get_wss)(struct omap_dss_device *dssdev); | |
3d5e0ef7 TV |
718 | |
719 | int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); | |
df4769c9 | 720 | bool (*detect)(struct omap_dss_device *dssdev); |
9c0b8420 RN |
721 | |
722 | /* | |
723 | * For display drivers that support audio. This encompasses | |
724 | * HDMI and DisplayPort at the moment. | |
725 | */ | |
726 | /* | |
727 | * Note: These functions might sleep. Do not call while | |
728 | * holding a spinlock/readlock. | |
729 | */ | |
730 | int (*audio_enable)(struct omap_dss_device *dssdev); | |
731 | void (*audio_disable)(struct omap_dss_device *dssdev); | |
732 | bool (*audio_supported)(struct omap_dss_device *dssdev); | |
733 | int (*audio_config)(struct omap_dss_device *dssdev, | |
734 | struct omap_dss_audio *audio); | |
735 | /* Note: These functions may not sleep */ | |
736 | int (*audio_start)(struct omap_dss_device *dssdev); | |
737 | void (*audio_stop)(struct omap_dss_device *dssdev); | |
738 | ||
559d6701 TV |
739 | }; |
740 | ||
b2c7d54f TV |
741 | enum omapdss_version omapdss_get_version(void); |
742 | ||
559d6701 TV |
743 | int omap_dss_register_driver(struct omap_dss_driver *); |
744 | void omap_dss_unregister_driver(struct omap_dss_driver *); | |
745 | ||
559d6701 TV |
746 | void omap_dss_get_device(struct omap_dss_device *dssdev); |
747 | void omap_dss_put_device(struct omap_dss_device *dssdev); | |
748 | #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL) | |
749 | struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from); | |
750 | struct omap_dss_device *omap_dss_find_device(void *data, | |
751 | int (*match)(struct omap_dss_device *dssdev, void *data)); | |
2bbcce5e | 752 | const char *omapdss_get_default_display_name(void); |
559d6701 TV |
753 | |
754 | int omap_dss_start_device(struct omap_dss_device *dssdev); | |
755 | void omap_dss_stop_device(struct omap_dss_device *dssdev); | |
756 | ||
757 | int omap_dss_get_num_overlay_managers(void); | |
758 | struct omap_overlay_manager *omap_dss_get_overlay_manager(int num); | |
759 | ||
760 | int omap_dss_get_num_overlays(void); | |
761 | struct omap_overlay *omap_dss_get_overlay(int num); | |
762 | ||
484dc404 | 763 | struct omap_dss_output *omap_dss_get_output(enum omap_dss_output_id id); |
6d71b923 AT |
764 | int omapdss_output_set_device(struct omap_dss_output *out, |
765 | struct omap_dss_device *dssdev); | |
766 | int omapdss_output_unset_device(struct omap_dss_output *out); | |
484dc404 | 767 | |
96adcece TV |
768 | void omapdss_default_get_resolution(struct omap_dss_device *dssdev, |
769 | u16 *xres, u16 *yres); | |
a2699504 | 770 | int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev); |
4b6430fc GI |
771 | void omapdss_default_get_timings(struct omap_dss_device *dssdev, |
772 | struct omap_video_timings *timings); | |
a2699504 | 773 | |
559d6701 TV |
774 | typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); |
775 | int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); | |
776 | int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); | |
777 | ||
559d6701 TV |
778 | #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver) |
779 | #define to_dss_device(x) container_of((x), struct omap_dss_device, dev) | |
780 | ||
1ffefe75 AT |
781 | void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, |
782 | bool enable); | |
225b650d | 783 | int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable); |
e67458a8 AT |
784 | void omapdss_dsi_set_timings(struct omap_dss_device *dssdev, |
785 | struct omap_video_timings *timings); | |
e352574d | 786 | void omapdss_dsi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h); |
02c3960b AT |
787 | void omapdss_dsi_set_pixel_format(struct omap_dss_device *dssdev, |
788 | enum omap_dss_dsi_pixel_format fmt); | |
dca2b152 AT |
789 | void omapdss_dsi_set_operation_mode(struct omap_dss_device *dssdev, |
790 | enum omap_dss_dsi_mode mode); | |
0b3ffe39 AT |
791 | void omapdss_dsi_set_videomode_timings(struct omap_dss_device *dssdev, |
792 | struct omap_dss_dsi_videomode_timings *timings); | |
61140c9a | 793 | |
5476e74a | 794 | int omap_dsi_update(struct omap_dss_device *dssdev, int channel, |
18946f62 | 795 | void (*callback)(int, void *), void *data); |
5ee3c144 AT |
796 | int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel); |
797 | int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id); | |
798 | void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel); | |
e4a9e94c TV |
799 | int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev, |
800 | const struct omap_dsi_pin_config *pin_cfg); | |
ee144e64 TV |
801 | int omapdss_dsi_set_clocks(struct omap_dss_device *dssdev, |
802 | unsigned long ddr_clk, unsigned long lp_clk); | |
18946f62 | 803 | |
37ac60e4 | 804 | int omapdss_dsi_display_enable(struct omap_dss_device *dssdev); |
2a89dc15 | 805 | void omapdss_dsi_display_disable(struct omap_dss_device *dssdev, |
22d6d676 | 806 | bool disconnect_lanes, bool enter_ulps); |
37ac60e4 TV |
807 | |
808 | int omapdss_dpi_display_enable(struct omap_dss_device *dssdev); | |
809 | void omapdss_dpi_display_disable(struct omap_dss_device *dssdev); | |
c499144c AT |
810 | void omapdss_dpi_set_timings(struct omap_dss_device *dssdev, |
811 | struct omap_video_timings *timings); | |
69b2048f TV |
812 | int dpi_check_timings(struct omap_dss_device *dssdev, |
813 | struct omap_video_timings *timings); | |
c6b393d4 | 814 | void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines); |
37ac60e4 TV |
815 | |
816 | int omapdss_sdi_display_enable(struct omap_dss_device *dssdev); | |
817 | void omapdss_sdi_display_disable(struct omap_dss_device *dssdev); | |
c7833f7b AT |
818 | void omapdss_sdi_set_timings(struct omap_dss_device *dssdev, |
819 | struct omap_video_timings *timings); | |
889b4fd7 | 820 | void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs); |
37ac60e4 TV |
821 | |
822 | int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev); | |
823 | void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev); | |
43eab861 AT |
824 | int omap_rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *), |
825 | void *data); | |
475989b7 | 826 | int omap_rfbi_configure(struct omap_dss_device *dssdev); |
6ff9dd5a | 827 | void omapdss_rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h); |
b02875be AT |
828 | void omapdss_rfbi_set_pixel_size(struct omap_dss_device *dssdev, |
829 | int pixel_size); | |
475989b7 AT |
830 | void omapdss_rfbi_set_data_lines(struct omap_dss_device *dssdev, |
831 | int data_lines); | |
6e883324 AT |
832 | void omapdss_rfbi_set_interface_timings(struct omap_dss_device *dssdev, |
833 | struct rfbi_timings *timings); | |
18946f62 | 834 | |
8dd2491a TV |
835 | int omapdss_compat_init(void); |
836 | void omapdss_compat_uninit(void); | |
837 | ||
559d6701 | 838 | #endif |