[mirror_ubuntu-bionic-kernel.git] / include / video / samsung_fimd.h

/* include/video/samsung_fimd.h
 *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * S3C Platform - new-style fimd and framebuffer register definitions
 *
 * This is the register set for the fimd and new style framebuffer interface
 * found from the S3C2443 onwards into the S3C2416, S3C2450, the
 * S3C64XX series such as the S3C6400 and S3C6410, and EXYNOS series.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

/* VIDCON0 */

#define VIDCON0					0x00
#define VIDCON0_INTERLACE			(1 << 29)
#define VIDCON0_VIDOUT_MASK			(0x7 << 26)
#define VIDCON0_VIDOUT_SHIFT			26
#define VIDCON0_VIDOUT_RGB			(0x0 << 26)
#define VIDCON0_VIDOUT_TV			(0x1 << 26)
#define VIDCON0_VIDOUT_I80_LDI0			(0x2 << 26)
#define VIDCON0_VIDOUT_I80_LDI1			(0x3 << 26)
#define VIDCON0_VIDOUT_WB_RGB			(0x4 << 26)
#define VIDCON0_VIDOUT_WB_I80_LDI0		(0x6 << 26)
#define VIDCON0_VIDOUT_WB_I80_LDI1		(0x7 << 26)

#define VIDCON0_L1_DATA_MASK			(0x7 << 23)
#define VIDCON0_L1_DATA_SHIFT			23
#define VIDCON0_L1_DATA_16BPP			(0x0 << 23)
#define VIDCON0_L1_DATA_18BPP16			(0x1 << 23)
#define VIDCON0_L1_DATA_18BPP9			(0x2 << 23)
#define VIDCON0_L1_DATA_24BPP			(0x3 << 23)
#define VIDCON0_L1_DATA_18BPP			(0x4 << 23)
#define VIDCON0_L1_DATA_16BPP8			(0x5 << 23)

#define VIDCON0_L0_DATA_MASK			(0x7 << 20)
#define VIDCON0_L0_DATA_SHIFT			20
#define VIDCON0_L0_DATA_16BPP			(0x0 << 20)
#define VIDCON0_L0_DATA_18BPP16			(0x1 << 20)
#define VIDCON0_L0_DATA_18BPP9			(0x2 << 20)
#define VIDCON0_L0_DATA_24BPP			(0x3 << 20)
#define VIDCON0_L0_DATA_18BPP			(0x4 << 20)
#define VIDCON0_L0_DATA_16BPP8			(0x5 << 20)

#define VIDCON0_PNRMODE_MASK			(0x3 << 17)
#define VIDCON0_PNRMODE_SHIFT			17
#define VIDCON0_PNRMODE_RGB			(0x0 << 17)
#define VIDCON0_PNRMODE_BGR			(0x1 << 17)
#define VIDCON0_PNRMODE_SERIAL_RGB		(0x2 << 17)
#define VIDCON0_PNRMODE_SERIAL_BGR		(0x3 << 17)

#define VIDCON0_CLKVALUP			(1 << 16)
#define VIDCON0_CLKVAL_F_MASK			(0xff << 6)
#define VIDCON0_CLKVAL_F_SHIFT			6
#define VIDCON0_CLKVAL_F_LIMIT			0xff
#define VIDCON0_CLKVAL_F(_x)			((_x) << 6)
#define VIDCON0_VLCKFREE			(1 << 5)
#define VIDCON0_CLKDIR				(1 << 4)

#define VIDCON0_CLKSEL_MASK			(0x3 << 2)
#define VIDCON0_CLKSEL_SHIFT			2
#define VIDCON0_CLKSEL_HCLK			(0x0 << 2)
#define VIDCON0_CLKSEL_LCD			(0x1 << 2)
#define VIDCON0_CLKSEL_27M			(0x3 << 2)

#define VIDCON0_ENVID				(1 << 1)
#define VIDCON0_ENVID_F				(1 << 0)

#define VIDCON1					0x04
#define VIDCON1_LINECNT_MASK			(0x7ff << 16)
#define VIDCON1_LINECNT_SHIFT			16
#define VIDCON1_LINECNT_GET(_v)			(((_v) >> 16) & 0x7ff)
#define VIDCON1_FSTATUS_EVEN			(1 << 15)
#define VIDCON1_VSTATUS_MASK			(0x3 << 13)
#define VIDCON1_VSTATUS_SHIFT			13
#define VIDCON1_VSTATUS_VSYNC			(0x0 << 13)
#define VIDCON1_VSTATUS_BACKPORCH		(0x1 << 13)
#define VIDCON1_VSTATUS_ACTIVE			(0x2 << 13)
#define VIDCON1_VSTATUS_FRONTPORCH		(0x3 << 13)
#define VIDCON1_VCLK_MASK			(0x3 << 9)
#define VIDCON1_VCLK_HOLD			(0x0 << 9)
#define VIDCON1_VCLK_RUN			(0x1 << 9)

#define VIDCON1_INV_VCLK			(1 << 7)
#define VIDCON1_INV_HSYNC			(1 << 6)
#define VIDCON1_INV_VSYNC			(1 << 5)
#define VIDCON1_INV_VDEN			(1 << 4)

/* VIDCON2 */

#define VIDCON2					0x08
#define VIDCON2_EN601				(1 << 23)
#define VIDCON2_TVFMTSEL_SW			(1 << 14)

#define VIDCON2_TVFMTSEL1_MASK			(0x3 << 12)
#define VIDCON2_TVFMTSEL1_SHIFT			12
#define VIDCON2_TVFMTSEL1_RGB			(0x0 << 12)
#define VIDCON2_TVFMTSEL1_YUV422		(0x1 << 12)
#define VIDCON2_TVFMTSEL1_YUV444		(0x2 << 12)

#define VIDCON2_ORGYCbCr			(1 << 8)
#define VIDCON2_YUVORDCrCb			(1 << 7)

/* PRTCON (S3C6410, S5PC100)
 * Might not be present in the S3C6410 documentation,
 * but tests prove it's there almost for sure; shouldn't hurt in any case.
 */
#define PRTCON					0x0c
#define PRTCON_PROTECT				(1 << 11)

/* VIDTCON0 */

#define VIDTCON0				0x10
#define VIDTCON0_VBPDE_MASK			(0xff << 24)
#define VIDTCON0_VBPDE_SHIFT			24
#define VIDTCON0_VBPDE_LIMIT			0xff
#define VIDTCON0_VBPDE(_x)			((_x) << 24)

#define VIDTCON0_VBPD_MASK			(0xff << 16)
#define VIDTCON0_VBPD_SHIFT			16
#define VIDTCON0_VBPD_LIMIT			0xff
#define VIDTCON0_VBPD(_x)			((_x) << 16)

#define VIDTCON0_VFPD_MASK			(0xff << 8)
#define VIDTCON0_VFPD_SHIFT			8
#define VIDTCON0_VFPD_LIMIT			0xff
#define VIDTCON0_VFPD(_x)			((_x) << 8)

#define VIDTCON0_VSPW_MASK			(0xff << 0)
#define VIDTCON0_VSPW_SHIFT			0
#define VIDTCON0_VSPW_LIMIT			0xff
#define VIDTCON0_VSPW(_x)			((_x) << 0)

/* VIDTCON1 */

#define VIDTCON1				0x14
#define VIDTCON1_VFPDE_MASK			(0xff << 24)
#define VIDTCON1_VFPDE_SHIFT			24
#define VIDTCON1_VFPDE_LIMIT			0xff
#define VIDTCON1_VFPDE(_x)			((_x) << 24)

#define VIDTCON1_HBPD_MASK			(0xff << 16)
#define VIDTCON1_HBPD_SHIFT			16
#define VIDTCON1_HBPD_LIMIT			0xff
#define VIDTCON1_HBPD(_x)			((_x) << 16)

#define VIDTCON1_HFPD_MASK			(0xff << 8)
#define VIDTCON1_HFPD_SHIFT			8
#define VIDTCON1_HFPD_LIMIT			0xff
#define VIDTCON1_HFPD(_x)			((_x) << 8)

#define VIDTCON1_HSPW_MASK			(0xff << 0)
#define VIDTCON1_HSPW_SHIFT			0
#define VIDTCON1_HSPW_LIMIT			0xff
#define VIDTCON1_HSPW(_x)			((_x) << 0)

#define VIDTCON2				0x18
#define VIDTCON2_LINEVAL_E(_x)			((((_x) & 0x800) >> 11) << 23)
#define VIDTCON2_LINEVAL_MASK			(0x7ff << 11)
#define VIDTCON2_LINEVAL_SHIFT			11
#define VIDTCON2_LINEVAL_LIMIT			0x7ff
#define VIDTCON2_LINEVAL(_x)			(((_x) & 0x7ff) << 11)

#define VIDTCON2_HOZVAL_E(_x)			((((_x) & 0x800) >> 11) << 22)
#define VIDTCON2_HOZVAL_MASK			(0x7ff << 0)
#define VIDTCON2_HOZVAL_SHIFT			0
#define VIDTCON2_HOZVAL_LIMIT			0x7ff
#define VIDTCON2_HOZVAL(_x)			(((_x) & 0x7ff) << 0)

/* WINCONx */

#define WINCON(_win)				(0x20 + ((_win) * 4))
#define WINCONx_CSCCON_EQ601			(0x0 << 28)
#define WINCONx_CSCCON_EQ709			(0x1 << 28)
#define WINCONx_CSCWIDTH_MASK			(0x3 << 26)
#define WINCONx_CSCWIDTH_SHIFT			26
#define WINCONx_CSCWIDTH_WIDE			(0x0 << 26)
#define WINCONx_CSCWIDTH_NARROW			(0x3 << 26)
#define WINCONx_ENLOCAL				(1 << 22)
#define WINCONx_BUFSTATUS			(1 << 21)
#define WINCONx_BUFSEL				(1 << 20)
#define WINCONx_BUFAUTOEN			(1 << 19)
#define WINCONx_BITSWP				(1 << 18)
#define WINCONx_BYTSWP				(1 << 17)
#define WINCONx_HAWSWP				(1 << 16)
#define WINCONx_WSWP				(1 << 15)
#define WINCONx_YCbCr				(1 << 13)
#define WINCONx_BURSTLEN_MASK			(0x3 << 9)
#define WINCONx_BURSTLEN_SHIFT			9
#define WINCONx_BURSTLEN_16WORD			(0x0 << 9)
#define WINCONx_BURSTLEN_8WORD			(0x1 << 9)
#define WINCONx_BURSTLEN_4WORD			(0x2 << 9)
#define WINCONx_ENWIN				(1 << 0)

#define WINCON0_BPPMODE_MASK			(0xf << 2)
#define WINCON0_BPPMODE_SHIFT			2
#define WINCON0_BPPMODE_1BPP			(0x0 << 2)
#define WINCON0_BPPMODE_2BPP			(0x1 << 2)
#define WINCON0_BPPMODE_4BPP			(0x2 << 2)
#define WINCON0_BPPMODE_8BPP_PALETTE		(0x3 << 2)
#define WINCON0_BPPMODE_16BPP_565		(0x5 << 2)
#define WINCON0_BPPMODE_16BPP_1555		(0x7 << 2)
#define WINCON0_BPPMODE_18BPP_666		(0x8 << 2)
#define WINCON0_BPPMODE_24BPP_888		(0xb << 2)

#define WINCON1_LOCALSEL_CAMIF			(1 << 23)
#define WINCON1_BLD_PIX				(1 << 6)
#define WINCON1_BPPMODE_MASK			(0xf << 2)
#define WINCON1_BPPMODE_SHIFT			2
#define WINCON1_BPPMODE_1BPP			(0x0 << 2)
#define WINCON1_BPPMODE_2BPP			(0x1 << 2)
#define WINCON1_BPPMODE_4BPP			(0x2 << 2)
#define WINCON1_BPPMODE_8BPP_PALETTE		(0x3 << 2)
#define WINCON1_BPPMODE_8BPP_1232		(0x4 << 2)
#define WINCON1_BPPMODE_16BPP_565		(0x5 << 2)
#define WINCON1_BPPMODE_16BPP_A1555		(0x6 << 2)
#define WINCON1_BPPMODE_16BPP_I1555		(0x7 << 2)
#define WINCON1_BPPMODE_18BPP_666		(0x8 << 2)
#define WINCON1_BPPMODE_18BPP_A1665		(0x9 << 2)
#define WINCON1_BPPMODE_19BPP_A1666		(0xa << 2)
#define WINCON1_BPPMODE_24BPP_888		(0xb << 2)
#define WINCON1_BPPMODE_24BPP_A1887		(0xc << 2)
#define WINCON1_BPPMODE_25BPP_A1888		(0xd << 2)
#define WINCON1_BPPMODE_28BPP_A4888		(0xd << 2)
#define WINCON1_ALPHA_SEL			(1 << 1)

/* S5PV210 */
#define SHADOWCON				0x34
#define SHADOWCON_WINx_PROTECT(_win)		(1 << (10 + (_win)))
/* DMA channels (all windows) */
#define SHADOWCON_CHx_ENABLE(_win)		(1 << (_win))
/* Local input channels (windows 0-2) */
#define SHADOWCON_CHx_LOCAL_ENABLE(_win)	(1 << (5 + (_win)))

/* VIDOSDx */

#define VIDOSD_BASE				0x40
#define VIDOSDxA_TOPLEFT_X_E(_x)		((((_x) & 0x800) >> 11) << 23)
#define VIDOSDxA_TOPLEFT_X_MASK			(0x7ff << 11)
#define VIDOSDxA_TOPLEFT_X_SHIFT		11
#define VIDOSDxA_TOPLEFT_X_LIMIT		0x7ff
#define VIDOSDxA_TOPLEFT_X(_x)			(((_x) & 0x7ff) << 11)

#define VIDOSDxA_TOPLEFT_Y_E(_x)		((((_x) & 0x800) >> 11) << 22)
#define VIDOSDxA_TOPLEFT_Y_MASK			(0x7ff << 0)
#define VIDOSDxA_TOPLEFT_Y_SHIFT		0
#define VIDOSDxA_TOPLEFT_Y_LIMIT		0x7ff
#define VIDOSDxA_TOPLEFT_Y(_x)			(((_x) & 0x7ff) << 0)

#define VIDOSDxB_BOTRIGHT_X_E(_x)		((((_x) & 0x800) >> 11) << 23)
#define VIDOSDxB_BOTRIGHT_X_MASK		(0x7ff << 11)
#define VIDOSDxB_BOTRIGHT_X_SHIFT		11
#define VIDOSDxB_BOTRIGHT_X_LIMIT		0x7ff
#define VIDOSDxB_BOTRIGHT_X(_x)			(((_x) & 0x7ff) << 11)

#define VIDOSDxB_BOTRIGHT_Y_E(_x)		((((_x) & 0x800) >> 11) << 22)
#define VIDOSDxB_BOTRIGHT_Y_MASK		(0x7ff << 0)
#define VIDOSDxB_BOTRIGHT_Y_SHIFT		0
#define VIDOSDxB_BOTRIGHT_Y_LIMIT		0x7ff
#define VIDOSDxB_BOTRIGHT_Y(_x)			(((_x) & 0x7ff) << 0)

/* For VIDOSD[1..4]C */
#define VIDISD14C_ALPHA0_R(_x)			((_x) << 20)
#define VIDISD14C_ALPHA0_G_MASK			(0xf << 16)
#define VIDISD14C_ALPHA0_G_SHIFT		16
#define VIDISD14C_ALPHA0_G_LIMIT		0xf
#define VIDISD14C_ALPHA0_G(_x)			((_x) << 16)
#define VIDISD14C_ALPHA0_B_MASK			(0xf << 12)
#define VIDISD14C_ALPHA0_B_SHIFT		12
#define VIDISD14C_ALPHA0_B_LIMIT		0xf
#define VIDISD14C_ALPHA0_B(_x)			((_x) << 12)
#define VIDISD14C_ALPHA1_R_MASK			(0xf << 8)
#define VIDISD14C_ALPHA1_R_SHIFT		8
#define VIDISD14C_ALPHA1_R_LIMIT		0xf
#define VIDISD14C_ALPHA1_R(_x)			((_x) << 8)
#define VIDISD14C_ALPHA1_G_MASK			(0xf << 4)
#define VIDISD14C_ALPHA1_G_SHIFT		4
#define VIDISD14C_ALPHA1_G_LIMIT		0xf
#define VIDISD14C_ALPHA1_G(_x)			((_x) << 4)
#define VIDISD14C_ALPHA1_B_MASK			(0xf << 0)
#define VIDISD14C_ALPHA1_B_SHIFT		0
#define VIDISD14C_ALPHA1_B_LIMIT		0xf
#define VIDISD14C_ALPHA1_B(_x)			((_x) << 0)

/* Video buffer addresses */
#define VIDW_BUF_START(_buff)			(0xA0 + ((_buff) * 8))
#define VIDW_BUF_START1(_buff)			(0xA4 + ((_buff) * 8))
#define VIDW_BUF_END(_buff)			(0xD0 + ((_buff) * 8))
#define VIDW_BUF_END1(_buff)			(0xD4 + ((_buff) * 8))
#define VIDW_BUF_SIZE(_buff)			(0x100 + ((_buff) * 4))

#define VIDW_BUF_SIZE_OFFSET_E(_x)		((((_x) & 0x2000) >> 13) << 27)
#define VIDW_BUF_SIZE_OFFSET_MASK		(0x1fff << 13)
#define VIDW_BUF_SIZE_OFFSET_SHIFT		13
#define VIDW_BUF_SIZE_OFFSET_LIMIT		0x1fff
#define VIDW_BUF_SIZE_OFFSET(_x)		(((_x) & 0x1fff) << 13)

#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x)		((((_x) & 0x2000) >> 13) << 26)
#define VIDW_BUF_SIZE_PAGEWIDTH_MASK		(0x1fff << 0)
#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT		0
#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT		0x1fff
#define VIDW_BUF_SIZE_PAGEWIDTH(_x)		(((_x) & 0x1fff) << 0)

/* Interrupt controls and status */

#define VIDINTCON0				0x130
#define VIDINTCON0_FIFOINTERVAL_MASK		(0x3f << 20)
#define VIDINTCON0_FIFOINTERVAL_SHIFT		20
#define VIDINTCON0_FIFOINTERVAL_LIMIT		0x3f
#define VIDINTCON0_FIFOINTERVAL(_x)		((_x) << 20)

#define VIDINTCON0_INT_SYSMAINCON		(1 << 19)
#define VIDINTCON0_INT_SYSSUBCON		(1 << 18)
#define VIDINTCON0_INT_I80IFDONE		(1 << 17)

#define VIDINTCON0_FRAMESEL0_MASK		(0x3 << 15)
#define VIDINTCON0_FRAMESEL0_SHIFT		15
#define VIDINTCON0_FRAMESEL0_BACKPORCH		(0x0 << 15)
#define VIDINTCON0_FRAMESEL0_VSYNC		(0x1 << 15)
#define VIDINTCON0_FRAMESEL0_ACTIVE		(0x2 << 15)
#define VIDINTCON0_FRAMESEL0_FRONTPORCH		(0x3 << 15)

#define VIDINTCON0_FRAMESEL1			(1 << 13)
#define VIDINTCON0_FRAMESEL1_MASK		(0x3 << 13)
#define VIDINTCON0_FRAMESEL1_NONE		(0x0 << 13)
#define VIDINTCON0_FRAMESEL1_BACKPORCH		(0x1 << 13)
#define VIDINTCON0_FRAMESEL1_VSYNC		(0x2 << 13)
#define VIDINTCON0_FRAMESEL1_FRONTPORCH		(0x3 << 13)

#define VIDINTCON0_INT_FRAME			(1 << 12)
#define VIDINTCON0_FIFIOSEL_MASK		(0x7f << 5)
#define VIDINTCON0_FIFIOSEL_SHIFT		5
#define VIDINTCON0_FIFIOSEL_WINDOW0		(0x1 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW1		(0x2 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW2		(0x10 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW3		(0x20 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW4		(0x40 << 5)

#define VIDINTCON0_FIFOLEVEL_MASK		(0x7 << 2)
#define VIDINTCON0_FIFOLEVEL_SHIFT		2
#define VIDINTCON0_FIFOLEVEL_TO25PC		(0x0 << 2)
#define VIDINTCON0_FIFOLEVEL_TO50PC		(0x1 << 2)
#define VIDINTCON0_FIFOLEVEL_TO75PC		(0x2 << 2)
#define VIDINTCON0_FIFOLEVEL_EMPTY		(0x3 << 2)
#define VIDINTCON0_FIFOLEVEL_FULL		(0x4 << 2)

#define VIDINTCON0_INT_FIFO_MASK		(0x3 << 0)
#define VIDINTCON0_INT_FIFO_SHIFT		0
#define VIDINTCON0_INT_ENABLE			(1 << 0)

#define VIDINTCON1				0x134
#define VIDINTCON1_INT_I180			(1 << 2)
#define VIDINTCON1_INT_FRAME			(1 << 1)
#define VIDINTCON1_INT_FIFO			(1 << 0)

/* Window colour-key control registers */
#define WKEYCON					0x140

#define WKEYCON0				0x00
#define WKEYCON1				0x04

#define WxKEYCON0_KEYBL_EN			(1 << 26)
#define WxKEYCON0_KEYEN_F			(1 << 25)
#define WxKEYCON0_DIRCON			(1 << 24)
#define WxKEYCON0_COMPKEY_MASK			(0xffffff << 0)
#define WxKEYCON0_COMPKEY_SHIFT			0
#define WxKEYCON0_COMPKEY_LIMIT			0xffffff
#define WxKEYCON0_COMPKEY(_x)			((_x) << 0)
#define WxKEYCON1_COLVAL_MASK			(0xffffff << 0)
#define WxKEYCON1_COLVAL_SHIFT			0
#define WxKEYCON1_COLVAL_LIMIT			0xffffff
#define WxKEYCON1_COLVAL(_x)			((_x) << 0)

/* Dithering control */
#define DITHMODE				0x170
#define DITHMODE_R_POS_MASK			(0x3 << 5)
#define DITHMODE_R_POS_SHIFT			5
#define DITHMODE_R_POS_8BIT			(0x0 << 5)
#define DITHMODE_R_POS_6BIT			(0x1 << 5)
#define DITHMODE_R_POS_5BIT			(0x2 << 5)
#define DITHMODE_G_POS_MASK			(0x3 << 3)
#define DITHMODE_G_POS_SHIFT			3
#define DITHMODE_G_POS_8BIT			(0x0 << 3)
#define DITHMODE_G_POS_6BIT			(0x1 << 3)
#define DITHMODE_G_POS_5BIT			(0x2 << 3)
#define DITHMODE_B_POS_MASK			(0x3 << 1)
#define DITHMODE_B_POS_SHIFT			1
#define DITHMODE_B_POS_8BIT			(0x0 << 1)
#define DITHMODE_B_POS_6BIT			(0x1 << 1)
#define DITHMODE_B_POS_5BIT			(0x2 << 1)
#define DITHMODE_DITH_EN			(1 << 0)

/* Window blanking (MAP) */
#define WINxMAP(_win)				(0x180 + ((_win) * 4))
#define WINxMAP_MAP				(1 << 24)
#define WINxMAP_MAP_COLOUR_MASK			(0xffffff << 0)
#define WINxMAP_MAP_COLOUR_SHIFT		0
#define WINxMAP_MAP_COLOUR_LIMIT		0xffffff
#define WINxMAP_MAP_COLOUR(_x)			((_x) << 0)

/* Winodw palette control */
#define WPALCON					0x1A0
#define WPALCON_PAL_UPDATE			(1 << 9)
#define WPALCON_W4PAL_16BPP_A555		(1 << 8)
#define WPALCON_W3PAL_16BPP_A555		(1 << 7)
#define WPALCON_W2PAL_16BPP_A555		(1 << 6)
#define WPALCON_W1PAL_MASK			(0x7 << 3)
#define WPALCON_W1PAL_SHIFT			3
#define WPALCON_W1PAL_25BPP_A888		(0x0 << 3)
#define WPALCON_W1PAL_24BPP			(0x1 << 3)
#define WPALCON_W1PAL_19BPP_A666		(0x2 << 3)
#define WPALCON_W1PAL_18BPP_A665		(0x3 << 3)
#define WPALCON_W1PAL_18BPP			(0x4 << 3)
#define WPALCON_W1PAL_16BPP_A555		(0x5 << 3)
#define WPALCON_W1PAL_16BPP_565			(0x6 << 3)
#define WPALCON_W0PAL_MASK			(0x7 << 0)
#define WPALCON_W0PAL_SHIFT			0
#define WPALCON_W0PAL_25BPP_A888		(0x0 << 0)
#define WPALCON_W0PAL_24BPP			(0x1 << 0)
#define WPALCON_W0PAL_19BPP_A666		(0x2 << 0)
#define WPALCON_W0PAL_18BPP_A665		(0x3 << 0)
#define WPALCON_W0PAL_18BPP			(0x4 << 0)
#define WPALCON_W0PAL_16BPP_A555		(0x5 << 0)
#define WPALCON_W0PAL_16BPP_565			(0x6 << 0)

/* Blending equation control */
#define BLENDCON				0x260
#define BLENDCON_NEW_MASK			(1 << 0)
#define BLENDCON_NEW_8BIT_ALPHA_VALUE		(1 << 0)
#define BLENDCON_NEW_4BIT_ALPHA_VALUE		(0 << 0)

/* Notes on per-window bpp settings
 *
 * Value	Win0	 Win1	  Win2	   Win3	    Win 4
 * 0000		1(P)	 1(P)	  1(P)	   1(P)	    1(P)
 * 0001		2(P)	 2(P)     2(P)	   2(P)	    2(P)
 * 0010		4(P)	 4(P)     4(P)	   4(P)     -none-
 * 0011		8(P)	 8(P)     -none-   -none-   -none-
 * 0100		-none-	 8(A232)  8(A232)  -none-   -none-
 * 0101		16(565)	 16(565)  16(565)  16(565)   16(565)
 * 0110		-none-	 16(A555) 16(A555) 16(A555)  16(A555)
 * 0111		16(I555) 16(I565) 16(I555) 16(I555)  16(I555)
 * 1000		18(666)	 18(666)  18(666)  18(666)   18(666)
 * 1001		-none-	 18(A665) 18(A665) 18(A665)  16(A665)
 * 1010		-none-	 19(A666) 19(A666) 19(A666)  19(A666)
 * 1011		24(888)	 24(888)  24(888)  24(888)   24(888)
 * 1100		-none-	 24(A887) 24(A887) 24(A887)  24(A887)
 * 1101		-none-	 25(A888) 25(A888) 25(A888)  25(A888)
 * 1110		-none-	 -none-	  -none-   -none-    -none-
 * 1111		-none-	 -none-   -none-   -none-    -none-
*/

/* FIMD Version 8 register offset definitions */
#define FIMD_V8_VIDTCON0	0x20010
#define FIMD_V8_VIDTCON1	0x20014
#define FIMD_V8_VIDTCON2	0x20018
#define FIMD_V8_VIDTCON3	0x2001C
#define FIMD_V8_VIDCON1		0x20004
Commit	Line	Data
5a213a55	1	/* include/video/samsung_fimd.h
8f995cc3 BD	2	*
	3	* Copyright 2008 Openmoko, Inc.
	4	* Copyright 2008 Simtec Electronics
	5	* http://armlinux.simtec.co.uk/
	6	* Ben Dooks <ben@simtec.co.uk>
	7	*
5a213a55	8	* S3C Platform - new-style fimd and framebuffer register definitions
8f995cc3	9	*
5a213a55	10	* This is the register set for the fimd and new style framebuffer interface
fe6863cc JH	11	* found from the S3C2443 onwards into the S3C2416, S3C2450, the
fe6863cc JH	12	* S3C64XX series such as the S3C6400 and S3C6410, and EXYNOS series.
8f995cc3	13	*
8f995cc3 BD	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License version 2 as
	16	* published by the Free Software Foundation.
	17	*/
	18
8f995cc3 BD	19	/* VIDCON0 */
8f995cc3 BD	20
fe6863cc	21	#define VIDCON0 0x00
8f995cc3	22	#define VIDCON0_INTERLACE (1 << 29)
b4da9c9a	23	#define VIDCON0_VIDOUT_MASK (0x7 << 26)
fe6863cc	24	#define VIDCON0_VIDOUT_SHIFT 26
8f995cc3 BD	25	#define VIDCON0_VIDOUT_RGB (0x0 << 26)
	26	#define VIDCON0_VIDOUT_TV (0x1 << 26)
	27	#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
	28	#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
b4da9c9a JH	29	#define VIDCON0_VIDOUT_WB_RGB (0x4 << 26)
	30	#define VIDCON0_VIDOUT_WB_I80_LDI0 (0x6 << 26)
	31	#define VIDCON0_VIDOUT_WB_I80_LDI1 (0x7 << 26)
8f995cc3 BD	32
8f995cc3 BD	33	#define VIDCON0_L1_DATA_MASK (0x7 << 23)
fe6863cc	34	#define VIDCON0_L1_DATA_SHIFT 23
8f995cc3 BD	35	#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
	36	#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
	37	#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
	38	#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
	39	#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
	40	#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
	41
	42	#define VIDCON0_L0_DATA_MASK (0x7 << 20)
fe6863cc	43	#define VIDCON0_L0_DATA_SHIFT 20
8f995cc3 BD	44	#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
	45	#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
	46	#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
	47	#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
	48	#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
	49	#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
	50
	51	#define VIDCON0_PNRMODE_MASK (0x3 << 17)
fe6863cc	52	#define VIDCON0_PNRMODE_SHIFT 17
8f995cc3 BD	53	#define VIDCON0_PNRMODE_RGB (0x0 << 17)
	54	#define VIDCON0_PNRMODE_BGR (0x1 << 17)
	55	#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
	56	#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
	57
	58	#define VIDCON0_CLKVALUP (1 << 16)
	59	#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
fe6863cc JH	60	#define VIDCON0_CLKVAL_F_SHIFT 6
fe6863cc JH	61	#define VIDCON0_CLKVAL_F_LIMIT 0xff
8f995cc3 BD	62	#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
	63	#define VIDCON0_VLCKFREE (1 << 5)
	64	#define VIDCON0_CLKDIR (1 << 4)
	65
	66	#define VIDCON0_CLKSEL_MASK (0x3 << 2)
fe6863cc	67	#define VIDCON0_CLKSEL_SHIFT 2
8f995cc3 BD	68	#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
	69	#define VIDCON0_CLKSEL_LCD (0x1 << 2)
	70	#define VIDCON0_CLKSEL_27M (0x3 << 2)
	71
	72	#define VIDCON0_ENVID (1 << 1)
	73	#define VIDCON0_ENVID_F (1 << 0)
	74
fe6863cc	75	#define VIDCON1 0x04
8f995cc3	76	#define VIDCON1_LINECNT_MASK (0x7ff << 16)
fe6863cc	77	#define VIDCON1_LINECNT_SHIFT 16
8f995cc3	78	#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
31dd94f9	79	#define VIDCON1_FSTATUS_EVEN (1 << 15)
8f995cc3	80	#define VIDCON1_VSTATUS_MASK (0x3 << 13)
fe6863cc	81	#define VIDCON1_VSTATUS_SHIFT 13
8f995cc3 BD	82	#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
	83	#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
	84	#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
678268e5	85	#define VIDCON1_VSTATUS_FRONTPORCH (0x3 << 13)
d8b97db4 JH	86	#define VIDCON1_VCLK_MASK (0x3 << 9)
	87	#define VIDCON1_VCLK_HOLD (0x0 << 9)
	88	#define VIDCON1_VCLK_RUN (0x1 << 9)
8f995cc3 BD	89
	90	#define VIDCON1_INV_VCLK (1 << 7)
	91	#define VIDCON1_INV_HSYNC (1 << 6)
	92	#define VIDCON1_INV_VSYNC (1 << 5)
	93	#define VIDCON1_INV_VDEN (1 << 4)
	94
	95	/* VIDCON2 */
	96
fe6863cc	97	#define VIDCON2 0x08
8f995cc3 BD	98	#define VIDCON2_EN601 (1 << 23)
	99	#define VIDCON2_TVFMTSEL_SW (1 << 14)
	100
	101	#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
fe6863cc	102	#define VIDCON2_TVFMTSEL1_SHIFT 12
8f995cc3 BD	103	#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
	104	#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
	105	#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
	106
	107	#define VIDCON2_ORGYCbCr (1 << 8)
	108	#define VIDCON2_YUVORDCrCb (1 << 7)
	109
067b226b PO	110	/* PRTCON (S3C6410, S5PC100)
	111	* Might not be present in the S3C6410 documentation,
	112	* but tests prove it's there almost for sure; shouldn't hurt in any case.
	113	*/
fe6863cc	114	#define PRTCON 0x0c
067b226b PO	115	#define PRTCON_PROTECT (1 << 11)
067b226b PO	116
8f995cc3 BD	117	/* VIDTCON0 */
8f995cc3 BD	118
fe6863cc	119	#define VIDTCON0 0x10
8f995cc3	120	#define VIDTCON0_VBPDE_MASK (0xff << 24)
fe6863cc JH	121	#define VIDTCON0_VBPDE_SHIFT 24
fe6863cc JH	122	#define VIDTCON0_VBPDE_LIMIT 0xff
8f995cc3 BD	123	#define VIDTCON0_VBPDE(_x) ((_x) << 24)
	124
	125	#define VIDTCON0_VBPD_MASK (0xff << 16)
fe6863cc JH	126	#define VIDTCON0_VBPD_SHIFT 16
fe6863cc JH	127	#define VIDTCON0_VBPD_LIMIT 0xff
8f995cc3 BD	128	#define VIDTCON0_VBPD(_x) ((_x) << 16)
	129
	130	#define VIDTCON0_VFPD_MASK (0xff << 8)
fe6863cc JH	131	#define VIDTCON0_VFPD_SHIFT 8
fe6863cc JH	132	#define VIDTCON0_VFPD_LIMIT 0xff
8f995cc3 BD	133	#define VIDTCON0_VFPD(_x) ((_x) << 8)
	134
	135	#define VIDTCON0_VSPW_MASK (0xff << 0)
fe6863cc JH	136	#define VIDTCON0_VSPW_SHIFT 0
fe6863cc JH	137	#define VIDTCON0_VSPW_LIMIT 0xff
8f995cc3 BD	138	#define VIDTCON0_VSPW(_x) ((_x) << 0)
	139
	140	/* VIDTCON1 */
	141
fe6863cc	142	#define VIDTCON1 0x14
8f995cc3	143	#define VIDTCON1_VFPDE_MASK (0xff << 24)
fe6863cc JH	144	#define VIDTCON1_VFPDE_SHIFT 24
fe6863cc JH	145	#define VIDTCON1_VFPDE_LIMIT 0xff
8f995cc3 BD	146	#define VIDTCON1_VFPDE(_x) ((_x) << 24)
	147
	148	#define VIDTCON1_HBPD_MASK (0xff << 16)
fe6863cc JH	149	#define VIDTCON1_HBPD_SHIFT 16
fe6863cc JH	150	#define VIDTCON1_HBPD_LIMIT 0xff
8f995cc3 BD	151	#define VIDTCON1_HBPD(_x) ((_x) << 16)
	152
	153	#define VIDTCON1_HFPD_MASK (0xff << 8)
fe6863cc JH	154	#define VIDTCON1_HFPD_SHIFT 8
fe6863cc JH	155	#define VIDTCON1_HFPD_LIMIT 0xff
8f995cc3 BD	156	#define VIDTCON1_HFPD(_x) ((_x) << 8)
	157
	158	#define VIDTCON1_HSPW_MASK (0xff << 0)
fe6863cc JH	159	#define VIDTCON1_HSPW_SHIFT 0
fe6863cc JH	160	#define VIDTCON1_HSPW_LIMIT 0xff
8f995cc3 BD	161	#define VIDTCON1_HSPW(_x) ((_x) << 0)
8f995cc3 BD	162
fe6863cc	163	#define VIDTCON2 0x18
5c44778e	164	#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
8f995cc3	165	#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
fe6863cc JH	166	#define VIDTCON2_LINEVAL_SHIFT 11
fe6863cc JH	167	#define VIDTCON2_LINEVAL_LIMIT 0x7ff
5c44778e	168	#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
8f995cc3	169
5c44778e	170	#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
8f995cc3	171	#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
fe6863cc JH	172	#define VIDTCON2_HOZVAL_SHIFT 0
fe6863cc JH	173	#define VIDTCON2_HOZVAL_LIMIT 0x7ff
5c44778e	174	#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
8f995cc3 BD	175
	176	/* WINCONx */
	177
36ff8d54	178	#define WINCON(_win) (0x20 + ((_win) * 4))
90dd0b07 JH	179	#define WINCONx_CSCCON_EQ601 (0x0 << 28)
90dd0b07 JH	180	#define WINCONx_CSCCON_EQ709 (0x1 << 28)
36ff8d54	181	#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
fe6863cc	182	#define WINCONx_CSCWIDTH_SHIFT 26
36ff8d54 JH	183	#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
	184	#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
	185	#define WINCONx_ENLOCAL (1 << 22)
	186	#define WINCONx_BUFSTATUS (1 << 21)
	187	#define WINCONx_BUFSEL (1 << 20)
	188	#define WINCONx_BUFAUTOEN (1 << 19)
8f995cc3 BD	189	#define WINCONx_BITSWP (1 << 18)
	190	#define WINCONx_BYTSWP (1 << 17)
	191	#define WINCONx_HAWSWP (1 << 16)
dc8498c0	192	#define WINCONx_WSWP (1 << 15)
36ff8d54	193	#define WINCONx_YCbCr (1 << 13)
8f995cc3	194	#define WINCONx_BURSTLEN_MASK (0x3 << 9)
fe6863cc	195	#define WINCONx_BURSTLEN_SHIFT 9
8f995cc3 BD	196	#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
	197	#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
	198	#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
8f995cc3	199	#define WINCONx_ENWIN (1 << 0)
36ff8d54	200
8f995cc3	201	#define WINCON0_BPPMODE_MASK (0xf << 2)
fe6863cc	202	#define WINCON0_BPPMODE_SHIFT 2
8f995cc3 BD	203	#define WINCON0_BPPMODE_1BPP (0x0 << 2)
	204	#define WINCON0_BPPMODE_2BPP (0x1 << 2)
	205	#define WINCON0_BPPMODE_4BPP (0x2 << 2)
	206	#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
	207	#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
	208	#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
	209	#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
	210	#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
	211
36ff8d54	212	#define WINCON1_LOCALSEL_CAMIF (1 << 23)
8f995cc3	213	#define WINCON1_BLD_PIX (1 << 6)
8f995cc3	214	#define WINCON1_BPPMODE_MASK (0xf << 2)
fe6863cc	215	#define WINCON1_BPPMODE_SHIFT 2
8f995cc3 BD	216	#define WINCON1_BPPMODE_1BPP (0x0 << 2)
	217	#define WINCON1_BPPMODE_2BPP (0x1 << 2)
	218	#define WINCON1_BPPMODE_4BPP (0x2 << 2)
	219	#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
	220	#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
	221	#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
	222	#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
	223	#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
	224	#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
	225	#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
	226	#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
	227	#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
	228	#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
	229	#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
	230	#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
36ff8d54	231	#define WINCON1_ALPHA_SEL (1 << 1)
8f995cc3	232
f5ec546f	233	/* S5PV210 */
fe6863cc	234	#define SHADOWCON 0x34
f5ec546f	235	#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
04ab9ef9 PO	236	/* DMA channels (all windows) */
	237	#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))
	238	/* Local input channels (windows 0-2) */
	239	#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
8f995cc3	240
99a2c61e JH	241	/* VIDOSDx */
99a2c61e JH	242
fe6863cc	243	#define VIDOSD_BASE 0x40
5c44778e	244	#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
8f995cc3	245	#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
fe6863cc JH	246	#define VIDOSDxA_TOPLEFT_X_SHIFT 11
fe6863cc JH	247	#define VIDOSDxA_TOPLEFT_X_LIMIT 0x7ff
5c44778e	248	#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
8f995cc3	249
5c44778e	250	#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
8f995cc3	251	#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
fe6863cc JH	252	#define VIDOSDxA_TOPLEFT_Y_SHIFT 0
fe6863cc JH	253	#define VIDOSDxA_TOPLEFT_Y_LIMIT 0x7ff
5c44778e	254	#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
8f995cc3	255
5c44778e	256	#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
8f995cc3	257	#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
fe6863cc JH	258	#define VIDOSDxB_BOTRIGHT_X_SHIFT 11
fe6863cc JH	259	#define VIDOSDxB_BOTRIGHT_X_LIMIT 0x7ff
5c44778e	260	#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
8f995cc3	261
5c44778e	262	#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
8f995cc3	263	#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
fe6863cc JH	264	#define VIDOSDxB_BOTRIGHT_Y_SHIFT 0
fe6863cc JH	265	#define VIDOSDxB_BOTRIGHT_Y_LIMIT 0x7ff
5c44778e	266	#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
8f995cc3 BD	267
	268	/* For VIDOSD[1..4]C */
	269	#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
	270	#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
fe6863cc JH	271	#define VIDISD14C_ALPHA0_G_SHIFT 16
fe6863cc JH	272	#define VIDISD14C_ALPHA0_G_LIMIT 0xf
8f995cc3 BD	273	#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
8f995cc3 BD	274	#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
fe6863cc JH	275	#define VIDISD14C_ALPHA0_B_SHIFT 12
fe6863cc JH	276	#define VIDISD14C_ALPHA0_B_LIMIT 0xf
8f995cc3 BD	277	#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
8f995cc3 BD	278	#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
fe6863cc JH	279	#define VIDISD14C_ALPHA1_R_SHIFT 8
fe6863cc JH	280	#define VIDISD14C_ALPHA1_R_LIMIT 0xf
8f995cc3 BD	281	#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
8f995cc3 BD	282	#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
fe6863cc JH	283	#define VIDISD14C_ALPHA1_G_SHIFT 4
fe6863cc JH	284	#define VIDISD14C_ALPHA1_G_LIMIT 0xf
8f995cc3 BD	285	#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
8f995cc3 BD	286	#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
fe6863cc JH	287	#define VIDISD14C_ALPHA1_B_SHIFT 0
fe6863cc JH	288	#define VIDISD14C_ALPHA1_B_LIMIT 0xf
8f995cc3 BD	289	#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
	290
	291	/* Video buffer addresses */
	292	#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
	293	#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
	294	#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
	295	#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
	296	#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
	297
5c44778e	298	#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
8f995cc3	299	#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
fe6863cc JH	300	#define VIDW_BUF_SIZE_OFFSET_SHIFT 13
fe6863cc JH	301	#define VIDW_BUF_SIZE_OFFSET_LIMIT 0x1fff
5c44778e	302	#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
8f995cc3	303
5c44778e	304	#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
8f995cc3	305	#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
fe6863cc JH	306	#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT 0
fe6863cc JH	307	#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT 0x1fff
5c44778e	308	#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
8f995cc3 BD	309
	310	/* Interrupt controls and status */
	311
fe6863cc	312	#define VIDINTCON0 0x130
8f995cc3	313	#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
fe6863cc JH	314	#define VIDINTCON0_FIFOINTERVAL_SHIFT 20
fe6863cc JH	315	#define VIDINTCON0_FIFOINTERVAL_LIMIT 0x3f
8f995cc3 BD	316	#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
	317
	318	#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
	319	#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
	320	#define VIDINTCON0_INT_I80IFDONE (1 << 17)
	321
	322	#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
fe6863cc	323	#define VIDINTCON0_FRAMESEL0_SHIFT 15
8f995cc3 BD	324	#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
	325	#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
	326	#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
	327	#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
	328
9fa424a4	329	#define VIDINTCON0_FRAMESEL1 (1 << 13)
efdc846d	330	#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)
9fa424a4 PO	331	#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)
	332	#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)
	333	#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
	334	#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)
8f995cc3 BD	335
	336	#define VIDINTCON0_INT_FRAME (1 << 12)
	337	#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
fe6863cc	338	#define VIDINTCON0_FIFIOSEL_SHIFT 5
8f995cc3 BD	339	#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
8f995cc3 BD	340	#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
60eb8d83 JH	341	#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
	342	#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
	343	#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
8f995cc3 BD	344
8f995cc3 BD	345	#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
fe6863cc	346	#define VIDINTCON0_FIFOLEVEL_SHIFT 2
8f995cc3 BD	347	#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
	348	#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
	349	#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
	350	#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
	351	#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
	352
	353	#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
fe6863cc	354	#define VIDINTCON0_INT_FIFO_SHIFT 0
8f995cc3 BD	355	#define VIDINTCON0_INT_ENABLE (1 << 0)
8f995cc3 BD	356
fe6863cc	357	#define VIDINTCON1 0x134
8f995cc3 BD	358	#define VIDINTCON1_INT_I180 (1 << 2)
	359	#define VIDINTCON1_INT_FRAME (1 << 1)
	360	#define VIDINTCON1_INT_FIFO (1 << 0)
	361
	362	/* Window colour-key control registers */
fe6863cc	363	#define WKEYCON 0x140
c4bb6ffa	364
fe6863cc JH	365	#define WKEYCON0 0x00
fe6863cc JH	366	#define WKEYCON1 0x04
8f995cc3 BD	367
	368	#define WxKEYCON0_KEYBL_EN (1 << 26)
	369	#define WxKEYCON0_KEYEN_F (1 << 25)
	370	#define WxKEYCON0_DIRCON (1 << 24)
	371	#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
fe6863cc JH	372	#define WxKEYCON0_COMPKEY_SHIFT 0
fe6863cc JH	373	#define WxKEYCON0_COMPKEY_LIMIT 0xffffff
8f995cc3 BD	374	#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
8f995cc3 BD	375	#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
fe6863cc JH	376	#define WxKEYCON1_COLVAL_SHIFT 0
fe6863cc JH	377	#define WxKEYCON1_COLVAL_LIMIT 0xffffff
8f995cc3 BD	378	#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
8f995cc3 BD	379
31dd94f9	380	/* Dithering control */
fe6863cc	381	#define DITHMODE 0x170
31dd94f9	382	#define DITHMODE_R_POS_MASK (0x3 << 5)
fe6863cc	383	#define DITHMODE_R_POS_SHIFT 5
31dd94f9 JH	384	#define DITHMODE_R_POS_8BIT (0x0 << 5)
	385	#define DITHMODE_R_POS_6BIT (0x1 << 5)
	386	#define DITHMODE_R_POS_5BIT (0x2 << 5)
	387	#define DITHMODE_G_POS_MASK (0x3 << 3)
fe6863cc	388	#define DITHMODE_G_POS_SHIFT 3
31dd94f9 JH	389	#define DITHMODE_G_POS_8BIT (0x0 << 3)
	390	#define DITHMODE_G_POS_6BIT (0x1 << 3)
	391	#define DITHMODE_G_POS_5BIT (0x2 << 3)
	392	#define DITHMODE_B_POS_MASK (0x3 << 1)
fe6863cc	393	#define DITHMODE_B_POS_SHIFT 1
31dd94f9 JH	394	#define DITHMODE_B_POS_8BIT (0x0 << 1)
	395	#define DITHMODE_B_POS_6BIT (0x1 << 1)
	396	#define DITHMODE_B_POS_5BIT (0x2 << 1)
	397	#define DITHMODE_DITH_EN (1 << 0)
	398
8f995cc3	399	/* Window blanking (MAP) */
22254540	400	#define WINxMAP(_win) (0x180 + ((_win) * 4))
8f995cc3 BD	401	#define WINxMAP_MAP (1 << 24)
8f995cc3 BD	402	#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
fe6863cc JH	403	#define WINxMAP_MAP_COLOUR_SHIFT 0
fe6863cc JH	404	#define WINxMAP_MAP_COLOUR_LIMIT 0xffffff
8f995cc3 BD	405	#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
8f995cc3 BD	406
22254540	407	/* Winodw palette control */
fe6863cc	408	#define WPALCON 0x1A0
8f995cc3	409	#define WPALCON_PAL_UPDATE (1 << 9)
22254540 JH	410	#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
	411	#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
	412	#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
8f995cc3	413	#define WPALCON_W1PAL_MASK (0x7 << 3)
fe6863cc	414	#define WPALCON_W1PAL_SHIFT 3
8f995cc3 BD	415	#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
	416	#define WPALCON_W1PAL_24BPP (0x1 << 3)
	417	#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
	418	#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
	419	#define WPALCON_W1PAL_18BPP (0x4 << 3)
	420	#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
	421	#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
8f995cc3	422	#define WPALCON_W0PAL_MASK (0x7 << 0)
fe6863cc	423	#define WPALCON_W0PAL_SHIFT 0
8f995cc3 BD	424	#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
	425	#define WPALCON_W0PAL_24BPP (0x1 << 0)
	426	#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
	427	#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
	428	#define WPALCON_W0PAL_18BPP (0x4 << 0)
	429	#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
	430	#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
	431
f7f31e50	432	/* Blending equation control */
fe6863cc	433	#define BLENDCON 0x260
f7f31e50 JH	434	#define BLENDCON_NEW_MASK (1 << 0)
	435	#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
	436	#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
	437
5a213a55 LKA	438	/* Notes on per-window bpp settings
	439	*
	440	* Value Win0 Win1 Win2 Win3 Win 4
	441	* 0000 1(P) 1(P) 1(P) 1(P) 1(P)
	442	* 0001 2(P) 2(P) 2(P) 2(P) 2(P)
	443	* 0010 4(P) 4(P) 4(P) 4(P) -none-
	444	* 0011 8(P) 8(P) -none- -none- -none-
	445	* 0100 -none- 8(A232) 8(A232) -none- -none-
	446	* 0101 16(565) 16(565) 16(565) 16(565) 16(565)
	447	* 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
	448	* 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
	449	* 1000 18(666) 18(666) 18(666) 18(666) 18(666)
	450	* 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
	451	* 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
	452	* 1011 24(888) 24(888) 24(888) 24(888) 24(888)
	453	* 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
	454	* 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
	455	* 1110 -none- -none- -none- -none- -none-
	456	* 1111 -none- -none- -none- -none- -none-
	457	*/
a44cf75d LKA	458
a44cf75d LKA	459	/* FIMD Version 8 register offset definitions */
fe6863cc JH	460	#define FIMD_V8_VIDTCON0 0x20010
	461	#define FIMD_V8_VIDTCON1 0x20014
	462	#define FIMD_V8_VIDTCON2 0x20018
	463	#define FIMD_V8_VIDTCON3 0x2001C
	464	#define FIMD_V8_VIDCON1 0x20004