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1da177e4 LT |
1 | /* |
2 | * linux/drivers/video/sstfb.h -- voodoo graphics frame buffer | |
3 | * | |
4 | * Copyright (c) 2000,2001 Ghozlane Toumi <gtoumi@messel.emse.fr> | |
5 | * | |
6 | * Created 28 Aug 2001 by Ghozlane Toumi | |
7 | */ | |
8 | ||
9 | ||
10 | #ifndef _SSTFB_H_ | |
11 | #define _SSTFB_H_ | |
12 | ||
13 | /* | |
14 | * | |
15 | * Debug Stuff | |
16 | * | |
17 | */ | |
18 | ||
19 | #ifdef SST_DEBUG | |
20 | # define dprintk(X...) printk("sstfb: " X) | |
21 | # define SST_DEBUG_REG 1 | |
22 | # define SST_DEBUG_FUNC 1 | |
23 | # define SST_DEBUG_VAR 1 | |
24 | #else | |
25 | # define dprintk(X...) | |
26 | # define SST_DEBUG_REG 0 | |
27 | # define SST_DEBUG_FUNC 0 | |
28 | # define SST_DEBUG_VAR 0 | |
29 | #endif | |
30 | ||
31 | #if (SST_DEBUG_REG > 0) | |
32 | # define r_dprintk(X...) dprintk(X) | |
33 | #else | |
34 | # define r_dprintk(X...) | |
35 | #endif | |
36 | #if (SST_DEBUG_REG > 1) | |
37 | # define r_ddprintk(X...) dprintk(" " X) | |
38 | #else | |
39 | # define r_ddprintk(X...) | |
40 | #endif | |
41 | ||
42 | #if (SST_DEBUG_FUNC > 0) | |
43 | # define f_dprintk(X...) dprintk(X) | |
44 | #else | |
45 | # define f_dprintk(X...) | |
46 | #endif | |
47 | #if (SST_DEBUG_FUNC > 1) | |
48 | # define f_ddprintk(X...) dprintk(" " X) | |
49 | #else | |
50 | # define f_ddprintk(X...) | |
51 | #endif | |
52 | #if (SST_DEBUG_FUNC > 2) | |
53 | # define f_dddprintk(X...) dprintk(" " X) | |
54 | #else | |
55 | # define f_dddprintk(X...) | |
56 | #endif | |
57 | ||
58 | #if (SST_DEBUG_VAR > 0) | |
59 | # define v_dprintk(X...) dprintk(X) | |
60 | # define print_var(V, X...) \ | |
61 | { \ | |
62 | dprintk(X); \ | |
63 | printk(" :\n"); \ | |
64 | sst_dbg_print_var(V); \ | |
65 | } | |
66 | #else | |
67 | # define v_dprintk(X...) | |
68 | # define print_var(X,Y...) | |
69 | #endif | |
70 | ||
71 | #define eprintk(X...) printk(KERN_ERR "sstfb: " X) | |
72 | #define iprintk(X...) printk(KERN_INFO "sstfb: " X) | |
73 | #define wprintk(X...) printk(KERN_WARNING "sstfb: " X) | |
74 | ||
75 | #define BIT(x) (1ul<<(x)) | |
76 | #define POW2(x) (1ul<<(x)) | |
77 | ||
78 | /* | |
79 | * | |
80 | * Const | |
81 | * | |
82 | */ | |
83 | ||
84 | /* pci stuff */ | |
85 | #define PCI_INIT_ENABLE 0x40 | |
86 | # define PCI_EN_INIT_WR BIT(0) | |
87 | # define PCI_EN_FIFO_WR BIT(1) | |
88 | # define PCI_REMAP_DAC BIT(2) | |
89 | #define PCI_VCLK_ENABLE 0xc0 /* enable video */ | |
90 | #define PCI_VCLK_DISABLE 0xe0 | |
91 | ||
92 | /* register offsets from memBaseAddr */ | |
93 | #define STATUS 0x0000 | |
94 | # define STATUS_FBI_BUSY BIT(7) | |
95 | #define FBZMODE 0x0110 | |
96 | # define EN_CLIPPING BIT(0) /* enable clipping */ | |
97 | # define EN_RGB_WRITE BIT(9) /* enable writes to rgb area */ | |
98 | # define EN_ALPHA_WRITE BIT(10) | |
99 | # define ENGINE_INVERT_Y BIT(17) /* invert Y origin (pipe) */ | |
100 | #define LFBMODE 0x0114 | |
101 | # define LFB_565 0 /* bits 3:0 .16 bits RGB */ | |
102 | # define LFB_888 4 /* 24 bits RGB */ | |
103 | # define LFB_8888 5 /* 32 bits ARGB */ | |
104 | # define WR_BUFF_FRONT 0 /* write buf select (front) */ | |
105 | # define WR_BUFF_BACK (1 << 4) /* back */ | |
106 | # define RD_BUFF_FRONT 0 /* read buff select (front) */ | |
107 | # define RD_BUFF_BACK (1 << 6) /* back */ | |
108 | # define EN_PXL_PIPELINE BIT(8) /* pixel pipeline (clip..)*/ | |
109 | # define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */ | |
110 | # define LFB_BYTE_SWIZZLE_WR BIT(12) /* enable write-byteswap (big-endian) */ | |
111 | # define LFB_INVERT_Y BIT(13) /* invert Y origin (LFB) */ | |
112 | # define LFB_WORD_SWIZZLE_RD BIT(15) /* enable read-wordswap (big-endian) */ | |
113 | # define LFB_BYTE_SWIZZLE_RD BIT(16) /* enable read-byteswap (big-endian) */ | |
114 | #define CLIP_LEFT_RIGHT 0x0118 | |
115 | #define CLIP_LOWY_HIGHY 0x011c | |
116 | #define NOPCMD 0x0120 | |
117 | #define FASTFILLCMD 0x0124 | |
118 | #define SWAPBUFFCMD 0x0128 | |
119 | #define FBIINIT4 0x0200 /* misc controls */ | |
120 | # define FAST_PCI_READS 0 /* 1 waitstate */ | |
121 | # define SLOW_PCI_READS BIT(0) /* 2 ws */ | |
122 | # define LFB_READ_AHEAD BIT(1) | |
123 | #define BACKPORCH 0x0208 | |
124 | #define VIDEODIMENSIONS 0x020c | |
125 | #define FBIINIT0 0x0210 /* misc+fifo controls */ | |
126 | # define EN_VGA_PASSTHROUGH BIT(0) | |
127 | # define FBI_RESET BIT(1) | |
128 | # define FIFO_RESET BIT(2) | |
129 | #define FBIINIT1 0x0214 /* PCI + video controls */ | |
130 | # define VIDEO_MASK 0x8080010f /* masks video related bits V1+V2*/ | |
131 | # define FAST_PCI_WRITES 0 /* 0 ws */ | |
132 | # define SLOW_PCI_WRITES BIT(1) /* 1 ws */ | |
133 | # define EN_LFB_READ BIT(3) | |
134 | # define TILES_IN_X_SHIFT 4 | |
135 | # define VIDEO_RESET BIT(8) | |
136 | # define EN_BLANKING BIT(12) | |
137 | # define EN_DATA_OE BIT(13) | |
138 | # define EN_BLANK_OE BIT(14) | |
139 | # define EN_HVSYNC_OE BIT(15) | |
140 | # define EN_DCLK_OE BIT(16) | |
141 | # define SEL_INPUT_VCLK_2X 0 /* bit 17 */ | |
142 | # define SEL_INPUT_VCLK_SLAVE BIT(17) | |
143 | # define SEL_SOURCE_VCLK_SLAVE 0 /* bits 21:20 */ | |
144 | # define SEL_SOURCE_VCLK_2X_DIV2 (0x01 << 20) | |
145 | # define SEL_SOURCE_VCLK_2X_SEL (0x02 << 20) | |
146 | # define EN_24BPP BIT(22) | |
147 | # define TILES_IN_X_MSB_SHIFT 24 /* v2 */ | |
148 | # define VCLK_2X_SEL_DEL_SHIFT 27 /* vclk out delay 0,4,6,8ns */ | |
149 | # define VCLK_DEL_SHIFT 29 /* vclk in delay */ | |
150 | #define FBIINIT2 0x0218 /* Dram controls */ | |
151 | # define EN_FAST_RAS_READ BIT(5) | |
152 | # define EN_DRAM_OE BIT(6) | |
153 | # define EN_FAST_RD_AHEAD_WR BIT(7) | |
154 | # define VIDEO_OFFSET_SHIFT 11 /* unit: #rows tile 64x16/2 */ | |
155 | # define SWAP_DACVSYNC 0 | |
156 | # define SWAP_DACDATA0 (1 << 9) | |
157 | # define SWAP_FIFO_STALL (2 << 9) | |
158 | # define EN_RD_AHEAD_FIFO BIT(21) | |
159 | # define EN_DRAM_REFRESH BIT(22) | |
160 | # define DRAM_REFRESH_16 (0x30 << 23) /* dram 16 ms */ | |
161 | #define DAC_READ FBIINIT2 /* in remap mode */ | |
162 | #define FBIINIT3 0x021c /* fbi controls */ | |
163 | # define DISABLE_TEXTURE BIT(6) | |
164 | # define Y_SWAP_ORIGIN_SHIFT 22 /* Y swap substraction value */ | |
165 | #define HSYNC 0x0220 | |
166 | #define VSYNC 0x0224 | |
167 | #define DAC_DATA 0x022c | |
168 | # define DAC_READ_CMD BIT(11) /* set read dacreg mode */ | |
169 | #define FBIINIT5 0x0244 /* v2 specific */ | |
170 | # define FBIINIT5_MASK 0xfa40ffff /* mask video bits*/ | |
171 | # define HDOUBLESCAN BIT(20) | |
172 | # define VDOUBLESCAN BIT(21) | |
173 | # define HSYNC_HIGH BIT(23) | |
174 | # define VSYNC_HIGH BIT(24) | |
175 | # define INTERLACE BIT(26) | |
176 | #define FBIINIT6 0x0248 /* v2 specific */ | |
177 | # define TILES_IN_X_LSB_SHIFT 30 /* v2 */ | |
178 | #define FBIINIT7 0x024c /* v2 specific */ | |
179 | ||
180 | #define BLTSRCBASEADDR 0x02c0 /* BitBLT Source base address */ | |
181 | #define BLTDSTBASEADDR 0x02c4 /* BitBLT Destination base address */ | |
182 | #define BLTXYSTRIDES 0x02c8 /* BitBLT Source and Destination strides */ | |
183 | #define BLTSRCCHROMARANGE 0x02cc /* BitBLT Source Chroma key range */ | |
184 | #define BLTDSTCHROMARANGE 0x02d0 /* BitBLT Destination Chroma key range */ | |
185 | #define BLTCLIPX 0x02d4 /* BitBLT Min/Max X clip values */ | |
186 | #define BLTCLIPY 0x02d8 /* BitBLT Min/Max Y clip values */ | |
187 | #define BLTSRCXY 0x02e0 /* BitBLT Source starting XY coordinates */ | |
188 | #define BLTDSTXY 0x02e4 /* BitBLT Destination starting XY coordinates */ | |
189 | #define BLTSIZE 0x02e8 /* BitBLT width and height */ | |
190 | #define BLTROP 0x02ec /* BitBLT Raster operations */ | |
191 | # define BLTROP_COPY 0x0cccc | |
192 | # define BLTROP_INVERT 0x05555 | |
193 | # define BLTROP_XOR 0x06666 | |
194 | #define BLTCOLOR 0x02f0 /* BitBLT and foreground background colors */ | |
195 | #define BLTCOMMAND 0x02f8 /* BitBLT command mode (v2 specific) */ | |
196 | # define BLT_SCR2SCR_BITBLT 0 /* Screen-to-Screen BitBLT */ | |
197 | # define BLT_CPU2SCR_BITBLT 1 /* CPU-to-screen BitBLT */ | |
198 | # define BLT_RECFILL_BITBLT 2 /* BitBLT Rectangle Fill */ | |
199 | # define BLT_16BPP_FMT 2 /* 16 BPP (5-6-5 RGB) */ | |
200 | #define BLTDATA 0x02fc /* BitBLT data for CPU-to-Screen BitBLTs */ | |
201 | # define LAUNCH_BITBLT BIT(31) /* Launch BitBLT in BltCommand, bltDstXY or bltSize */ | |
202 | ||
203 | /* Dac Registers */ | |
204 | #define DACREG_WMA 0x0 /* pixel write mode address */ | |
205 | #define DACREG_LUT 0x01 /* color value */ | |
206 | #define DACREG_RMR 0x02 /* pixel mask */ | |
207 | #define DACREG_RMA 0x03 /* pixel read mode address */ | |
208 | /*Dac registers in indexed mode (TI, ATT dacs) */ | |
209 | #define DACREG_ADDR_I DACREG_WMA | |
210 | #define DACREG_DATA_I DACREG_RMR | |
211 | #define DACREG_RMR_I 0x00 | |
212 | #define DACREG_CR0_I 0x01 | |
213 | # define DACREG_CR0_EN_INDEXED BIT(0) /* enable indexec mode */ | |
214 | # define DACREG_CR0_8BIT BIT(1) /* set dac to 8 bits/read */ | |
215 | # define DACREG_CR0_PWDOWN BIT(3) /* powerdown dac */ | |
216 | # define DACREG_CR0_16BPP 0x30 /* mode 3 */ | |
217 | # define DACREG_CR0_24BPP 0x50 /* mode 5 */ | |
218 | #define DACREG_CR1_I 0x05 | |
219 | #define DACREG_CC_I 0x06 | |
220 | # define DACREG_CC_CLKA BIT(7) /* clk A controled by regs */ | |
221 | # define DACREG_CC_CLKA_C (2<<4) /* clk A uses reg C */ | |
222 | # define DACREG_CC_CLKB BIT(3) /* clk B controled by regs */ | |
223 | # define DACREG_CC_CLKB_D 3 /* clkB uses reg D */ | |
224 | #define DACREG_AC0_I 0x48 /* clock A reg C */ | |
225 | #define DACREG_AC1_I 0x49 | |
226 | #define DACREG_BD0_I 0x6c /* clock B reg D */ | |
227 | #define DACREG_BD1_I 0x6d | |
228 | ||
229 | /* identification constants */ | |
230 | #define DACREG_MIR_TI 0x97 | |
231 | #define DACREG_DIR_TI 0x09 | |
232 | #define DACREG_MIR_ATT 0x84 | |
233 | #define DACREG_DIR_ATT 0x09 | |
234 | /* ics dac specific registers */ | |
235 | #define DACREG_ICS_PLLWMA 0x04 /* PLL write mode address */ | |
236 | #define DACREG_ICS_PLLDATA 0x05 /* PLL data /parameter */ | |
237 | #define DACREG_ICS_CMD 0x06 /* command */ | |
238 | # define DACREG_ICS_CMD_16BPP 0x50 /* ics color mode 6 (16bpp bypass)*/ | |
239 | # define DACREG_ICS_CMD_24BPP 0x70 /* ics color mode 7 (24bpp bypass)*/ | |
240 | # define DACREG_ICS_CMD_PWDOWN BIT(0) /* powerdown dac */ | |
241 | #define DACREG_ICS_PLLRMA 0x07 /* PLL read mode address */ | |
242 | /* | |
243 | * pll parameter register: | |
244 | * indexed : write addr to PLLWMA, write data in PLLDATA. | |
245 | * for reads use PLLRMA . | |
246 | * 8 freq registers (0-7) for video clock (CLK0) | |
247 | * 2 freq registers (a-b) for graphic clock (CLK1) | |
248 | */ | |
249 | #define DACREG_ICS_PLL_CLK0_1_INI 0x55 /* initial pll M value for freq f1 */ | |
250 | #define DACREG_ICS_PLL_CLK0_7_INI 0x71 /* f7 */ | |
251 | #define DACREG_ICS_PLL_CLK1_B_INI 0x79 /* fb */ | |
252 | #define DACREG_ICS_PLL_CTRL 0x0e | |
253 | # define DACREG_ICS_CLK0 BIT(5) | |
254 | # define DACREG_ICS_CLK0_0 0 | |
255 | # define DACREG_ICS_CLK1_A 0 /* bit4 */ | |
256 | ||
257 | /* sst default init registers */ | |
258 | #define FBIINIT0_DEFAULT EN_VGA_PASSTHROUGH | |
259 | ||
260 | #define FBIINIT1_DEFAULT \ | |
261 | ( \ | |
262 | FAST_PCI_WRITES \ | |
263 | /* SLOW_PCI_WRITES*/ \ | |
264 | | VIDEO_RESET \ | |
265 | | 10 << TILES_IN_X_SHIFT\ | |
266 | | SEL_SOURCE_VCLK_2X_SEL\ | |
267 | | EN_LFB_READ \ | |
268 | ) | |
269 | ||
270 | #define FBIINIT2_DEFAULT \ | |
271 | ( \ | |
272 | SWAP_DACVSYNC \ | |
273 | | EN_DRAM_OE \ | |
274 | | DRAM_REFRESH_16 \ | |
275 | | EN_DRAM_REFRESH \ | |
276 | | EN_FAST_RAS_READ \ | |
277 | | EN_RD_AHEAD_FIFO \ | |
278 | | EN_FAST_RD_AHEAD_WR \ | |
279 | ) | |
280 | ||
281 | #define FBIINIT3_DEFAULT \ | |
282 | ( DISABLE_TEXTURE ) | |
283 | ||
284 | #define FBIINIT4_DEFAULT \ | |
285 | ( \ | |
286 | FAST_PCI_READS \ | |
287 | /* SLOW_PCI_READS*/ \ | |
288 | | LFB_READ_AHEAD \ | |
289 | ) | |
290 | /* Careful with this one : writing back the data just read will trash the DAC | |
291 | reading some fields give logic value on pins, but setting this field will | |
292 | set the source signal driving the pin. conclusion : just use the default | |
293 | as a base before writing back . | |
294 | */ | |
295 | #define FBIINIT6_DEFAULT (0x0) | |
296 | ||
297 | /* | |
298 | * | |
299 | * Misc Const | |
300 | * | |
301 | */ | |
302 | ||
303 | /* used to know witch clock to set */ | |
304 | enum { | |
305 | VID_CLOCK=0, | |
306 | GFX_CLOCK=1, | |
307 | }; | |
308 | ||
309 | /* freq max */ | |
310 | #define DAC_FREF 14318 /* DAC reference freq (Khz) */ | |
311 | #define VCO_MAX 260000 | |
312 | ||
313 | /* | |
314 | * driver structs | |
315 | */ | |
316 | ||
317 | struct pll_timing { | |
318 | unsigned int m; | |
319 | unsigned int n; | |
320 | unsigned int p; | |
321 | }; | |
322 | ||
323 | struct dac_switch { | |
324 | char * name; | |
325 | int (*detect) (struct fb_info *info); | |
326 | int (*set_pll) (struct fb_info *info, const struct pll_timing *t, const int clock); | |
327 | void (*set_vidmod) (struct fb_info *info, const int bpp); | |
328 | }; | |
329 | ||
330 | struct sst_spec { | |
331 | char * name; | |
332 | int default_gfx_clock; /* 50000 for voodoo1, 75000 for voodoo2 */ | |
333 | int max_gfxclk; /* ! in Mhz ie 60 for voodoo 1 */ | |
334 | }; | |
335 | ||
336 | struct sstfb_par { | |
7227576f | 337 | u32 palette[16]; |
1da177e4 LT |
338 | unsigned int yDim; |
339 | unsigned int hSyncOn; /* hsync_len */ | |
340 | unsigned int hSyncOff; /* left_margin + xres + right_margin */ | |
341 | unsigned int hBackPorch;/* left_margin */ | |
342 | unsigned int vSyncOn; | |
343 | unsigned int vSyncOff; | |
344 | unsigned int vBackPorch; | |
345 | struct pll_timing pll; | |
346 | unsigned int tiles_in_X;/* num of tiles in X res */ | |
347 | u8 __iomem *mmio_vbase; | |
348 | struct dac_switch dac_sw; /* dac specific functions */ | |
349 | struct pci_dev *dev; | |
350 | int type; | |
351 | u8 revision; | |
352 | int gfx_clock; /* status */ | |
353 | }; | |
354 | ||
355 | #endif /* _SSTFB_H_ */ |