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a42089dd JF |
1 | /****************************************************************************** |
2 | * xen.h | |
3 | * | |
4 | * Guest OS interface to Xen. | |
5 | * | |
bca9b685 JG |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to | |
8 | * deal in the Software without restriction, including without limitation the | |
9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or | |
10 | * sell copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE | |
19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
a42089dd JF |
24 | * Copyright (c) 2004, K A Fraser |
25 | */ | |
26 | ||
27 | #ifndef __XEN_PUBLIC_XEN_H__ | |
28 | #define __XEN_PUBLIC_XEN_H__ | |
29 | ||
30 | #include <asm/xen/interface.h> | |
31 | ||
32 | /* | |
33 | * XEN "SYSTEM CALLS" (a.k.a. HYPERCALLS). | |
34 | */ | |
35 | ||
36 | /* | |
37 | * x86_32: EAX = vector; EBX, ECX, EDX, ESI, EDI = args 1, 2, 3, 4, 5. | |
38 | * EAX = return value | |
39 | * (argument registers may be clobbered on return) | |
40 | * x86_64: RAX = vector; RDI, RSI, RDX, R10, R8, R9 = args 1, 2, 3, 4, 5, 6. | |
41 | * RAX = return value | |
42 | * (argument registers not clobbered on return; RCX, R11 are) | |
43 | */ | |
44 | #define __HYPERVISOR_set_trap_table 0 | |
45 | #define __HYPERVISOR_mmu_update 1 | |
46 | #define __HYPERVISOR_set_gdt 2 | |
47 | #define __HYPERVISOR_stack_switch 3 | |
48 | #define __HYPERVISOR_set_callbacks 4 | |
49 | #define __HYPERVISOR_fpu_taskswitch 5 | |
a8b74583 | 50 | #define __HYPERVISOR_sched_op_compat 6 |
cfafae94 | 51 | #define __HYPERVISOR_platform_op 7 |
a42089dd JF |
52 | #define __HYPERVISOR_set_debugreg 8 |
53 | #define __HYPERVISOR_get_debugreg 9 | |
54 | #define __HYPERVISOR_update_descriptor 10 | |
55 | #define __HYPERVISOR_memory_op 12 | |
56 | #define __HYPERVISOR_multicall 13 | |
57 | #define __HYPERVISOR_update_va_mapping 14 | |
58 | #define __HYPERVISOR_set_timer_op 15 | |
59 | #define __HYPERVISOR_event_channel_op_compat 16 | |
60 | #define __HYPERVISOR_xen_version 17 | |
61 | #define __HYPERVISOR_console_io 18 | |
62 | #define __HYPERVISOR_physdev_op_compat 19 | |
63 | #define __HYPERVISOR_grant_table_op 20 | |
64 | #define __HYPERVISOR_vm_assist 21 | |
65 | #define __HYPERVISOR_update_va_mapping_otherdomain 22 | |
66 | #define __HYPERVISOR_iret 23 /* x86 only */ | |
67 | #define __HYPERVISOR_vcpu_op 24 | |
68 | #define __HYPERVISOR_set_segment_base 25 /* x86/64 only */ | |
69 | #define __HYPERVISOR_mmuext_op 26 | |
16b12d60 | 70 | #define __HYPERVISOR_xsm_op 27 |
a42089dd | 71 | #define __HYPERVISOR_nmi_op 28 |
a8b74583 | 72 | #define __HYPERVISOR_sched_op 29 |
a42089dd JF |
73 | #define __HYPERVISOR_callback_op 30 |
74 | #define __HYPERVISOR_xenoprof_op 31 | |
75 | #define __HYPERVISOR_event_channel_op 32 | |
76 | #define __HYPERVISOR_physdev_op 33 | |
77 | #define __HYPERVISOR_hvm_op 34 | |
16b12d60 JG |
78 | #define __HYPERVISOR_sysctl 35 |
79 | #define __HYPERVISOR_domctl 36 | |
80 | #define __HYPERVISOR_kexec_op 37 | |
5bc20fc5 | 81 | #define __HYPERVISOR_tmem_op 38 |
16b12d60 | 82 | #define __HYPERVISOR_xc_reserved_op 39 /* reserved for XenClient */ |
5f141548 | 83 | #define __HYPERVISOR_xenpmu_op 40 |
a42089dd | 84 | |
9a9db275 IY |
85 | /* Architecture-specific hypercall definitions. */ |
86 | #define __HYPERVISOR_arch_0 48 | |
87 | #define __HYPERVISOR_arch_1 49 | |
88 | #define __HYPERVISOR_arch_2 50 | |
89 | #define __HYPERVISOR_arch_3 51 | |
90 | #define __HYPERVISOR_arch_4 52 | |
91 | #define __HYPERVISOR_arch_5 53 | |
92 | #define __HYPERVISOR_arch_6 54 | |
93 | #define __HYPERVISOR_arch_7 55 | |
94 | ||
a42089dd JF |
95 | /* |
96 | * VIRTUAL INTERRUPTS | |
97 | * | |
98 | * Virtual interrupts that a guest OS may receive from Xen. | |
bca9b685 JG |
99 | * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a |
100 | * global VIRQ. The former can be bound once per VCPU and cannot be re-bound. | |
101 | * The latter can be allocated only once per guest: they must initially be | |
102 | * allocated to VCPU0 but can subsequently be re-bound. | |
a42089dd | 103 | */ |
bca9b685 JG |
104 | #define VIRQ_TIMER 0 /* V. Timebase update, and/or requested timeout. */ |
105 | #define VIRQ_DEBUG 1 /* V. Request guest to dump debug info. */ | |
106 | #define VIRQ_CONSOLE 2 /* G. (DOM0) Bytes received on emergency console. */ | |
107 | #define VIRQ_DOM_EXC 3 /* G. (DOM0) Exceptional event for some domain. */ | |
108 | #define VIRQ_TBUF 4 /* G. (DOM0) Trace buffer has records available. */ | |
109 | #define VIRQ_DEBUGGER 6 /* G. (DOM0) A domain has paused for debugging. */ | |
110 | #define VIRQ_XENOPROF 7 /* V. XenOprofile interrupt: new sample available */ | |
111 | #define VIRQ_CON_RING 8 /* G. (DOM0) Bytes received on console */ | |
112 | #define VIRQ_PCPU_STATE 9 /* G. (DOM0) PCPU state changed */ | |
113 | #define VIRQ_MEM_EVENT 10 /* G. (DOM0) A memory event has occured */ | |
114 | #define VIRQ_XC_RESERVED 11 /* G. Reserved for XenClient */ | |
115 | #define VIRQ_ENOMEM 12 /* G. (DOM0) Low on heap memory */ | |
65d0cf0b | 116 | #define VIRQ_XENPMU 13 /* PMC interrupt */ |
a42089dd | 117 | |
2eb6d5eb IY |
118 | /* Architecture-specific VIRQ definitions. */ |
119 | #define VIRQ_ARCH_0 16 | |
120 | #define VIRQ_ARCH_1 17 | |
121 | #define VIRQ_ARCH_2 18 | |
122 | #define VIRQ_ARCH_3 19 | |
123 | #define VIRQ_ARCH_4 20 | |
124 | #define VIRQ_ARCH_5 21 | |
125 | #define VIRQ_ARCH_6 22 | |
126 | #define VIRQ_ARCH_7 23 | |
127 | ||
128 | #define NR_VIRQS 24 | |
bca9b685 | 129 | |
a42089dd | 130 | /* |
bca9b685 JG |
131 | * enum neg_errnoval HYPERVISOR_mmu_update(const struct mmu_update reqs[], |
132 | * unsigned count, unsigned *done_out, | |
133 | * unsigned foreigndom) | |
134 | * @reqs is an array of mmu_update_t structures ((ptr, val) pairs). | |
135 | * @count is the length of the above array. | |
136 | * @pdone is an output parameter indicating number of completed operations | |
137 | * @foreigndom[15:0]: FD, the expected owner of data pages referenced in this | |
138 | * hypercall invocation. Can be DOMID_SELF. | |
139 | * @foreigndom[31:16]: PFD, the expected owner of pagetable pages referenced | |
140 | * in this hypercall invocation. The value of this field | |
141 | * (x) encodes the PFD as follows: | |
142 | * x == 0 => PFD == DOMID_SELF | |
143 | * x != 0 => PFD == x - 1 | |
a42089dd | 144 | * |
bca9b685 JG |
145 | * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command. |
146 | * ------------- | |
a42089dd | 147 | * ptr[1:0] == MMU_NORMAL_PT_UPDATE: |
bca9b685 JG |
148 | * Updates an entry in a page table belonging to PFD. If updating an L1 table, |
149 | * and the new table entry is valid/present, the mapped frame must belong to | |
150 | * FD. If attempting to map an I/O page then the caller assumes the privilege | |
151 | * of the FD. | |
a42089dd JF |
152 | * FD == DOMID_IO: Permit /only/ I/O mappings, at the priv level of the caller. |
153 | * FD == DOMID_XEN: Map restricted areas of Xen's heap space. | |
154 | * ptr[:2] -- Machine address of the page-table entry to modify. | |
155 | * val -- Value to write. | |
156 | * | |
bca9b685 JG |
157 | * There also certain implicit requirements when using this hypercall. The |
158 | * pages that make up a pagetable must be mapped read-only in the guest. | |
159 | * This prevents uncontrolled guest updates to the pagetable. Xen strictly | |
160 | * enforces this, and will disallow any pagetable update which will end up | |
161 | * mapping pagetable page RW, and will disallow using any writable page as a | |
162 | * pagetable. In practice it means that when constructing a page table for a | |
163 | * process, thread, etc, we MUST be very dilligient in following these rules: | |
164 | * 1). Start with top-level page (PGD or in Xen language: L4). Fill out | |
165 | * the entries. | |
166 | * 2). Keep on going, filling out the upper (PUD or L3), and middle (PMD | |
167 | * or L2). | |
168 | * 3). Start filling out the PTE table (L1) with the PTE entries. Once | |
169 | * done, make sure to set each of those entries to RO (so writeable bit | |
170 | * is unset). Once that has been completed, set the PMD (L2) for this | |
171 | * PTE table as RO. | |
172 | * 4). When completed with all of the PMD (L2) entries, and all of them have | |
173 | * been set to RO, make sure to set RO the PUD (L3). Do the same | |
174 | * operation on PGD (L4) pagetable entries that have a PUD (L3) entry. | |
175 | * 5). Now before you can use those pages (so setting the cr3), you MUST also | |
176 | * pin them so that the hypervisor can verify the entries. This is done | |
177 | * via the HYPERVISOR_mmuext_op(MMUEXT_PIN_L4_TABLE, guest physical frame | |
178 | * number of the PGD (L4)). And this point the HYPERVISOR_mmuext_op( | |
179 | * MMUEXT_NEW_BASEPTR, guest physical frame number of the PGD (L4)) can be | |
180 | * issued. | |
181 | * For 32-bit guests, the L4 is not used (as there is less pagetables), so | |
182 | * instead use L3. | |
183 | * At this point the pagetables can be modified using the MMU_NORMAL_PT_UPDATE | |
184 | * hypercall. Also if so desired the OS can also try to write to the PTE | |
185 | * and be trapped by the hypervisor (as the PTE entry is RO). | |
186 | * | |
187 | * To deallocate the pages, the operations are the reverse of the steps | |
188 | * mentioned above. The argument is MMUEXT_UNPIN_TABLE for all levels and the | |
189 | * pagetable MUST not be in use (meaning that the cr3 is not set to it). | |
190 | * | |
a42089dd JF |
191 | * ptr[1:0] == MMU_MACHPHYS_UPDATE: |
192 | * Updates an entry in the machine->pseudo-physical mapping table. | |
193 | * ptr[:2] -- Machine address within the frame whose mapping to modify. | |
194 | * The frame must belong to the FD, if one is specified. | |
195 | * val -- Value to write into the mapping entry. | |
e57778a1 JF |
196 | * |
197 | * ptr[1:0] == MMU_PT_UPDATE_PRESERVE_AD: | |
198 | * As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are ORed | |
199 | * with those in @val. | |
bca9b685 JG |
200 | * |
201 | * @val is usually the machine frame number along with some attributes. | |
202 | * The attributes by default follow the architecture defined bits. Meaning that | |
203 | * if this is a X86_64 machine and four page table layout is used, the layout | |
204 | * of val is: | |
205 | * - 63 if set means No execute (NX) | |
206 | * - 46-13 the machine frame number | |
207 | * - 12 available for guest | |
208 | * - 11 available for guest | |
209 | * - 10 available for guest | |
210 | * - 9 available for guest | |
211 | * - 8 global | |
212 | * - 7 PAT (PSE is disabled, must use hypercall to make 4MB or 2MB pages) | |
213 | * - 6 dirty | |
214 | * - 5 accessed | |
215 | * - 4 page cached disabled | |
216 | * - 3 page write through | |
217 | * - 2 userspace accessible | |
218 | * - 1 writeable | |
219 | * - 0 present | |
220 | * | |
221 | * The one bits that does not fit with the default layout is the PAGE_PSE | |
222 | * also called PAGE_PAT). The MMUEXT_[UN]MARK_SUPER arguments to the | |
223 | * HYPERVISOR_mmuext_op serve as mechanism to set a pagetable to be 4MB | |
224 | * (or 2MB) instead of using the PAGE_PSE bit. | |
225 | * | |
226 | * The reason that the PAGE_PSE (bit 7) is not being utilized is due to Xen | |
227 | * using it as the Page Attribute Table (PAT) bit - for details on it please | |
228 | * refer to Intel SDM 10.12. The PAT allows to set the caching attributes of | |
229 | * pages instead of using MTRRs. | |
230 | * | |
231 | * The PAT MSR is as follows (it is a 64-bit value, each entry is 8 bits): | |
232 | * PAT4 PAT0 | |
233 | * +-----+-----+----+----+----+-----+----+----+ | |
234 | * | UC | UC- | WC | WB | UC | UC- | WC | WB | <= Linux | |
235 | * +-----+-----+----+----+----+-----+----+----+ | |
236 | * | UC | UC- | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots) | |
237 | * +-----+-----+----+----+----+-----+----+----+ | |
238 | * | rsv | rsv | WP | WC | UC | UC- | WT | WB | <= Xen | |
239 | * +-----+-----+----+----+----+-----+----+----+ | |
240 | * | |
241 | * The lookup of this index table translates to looking up | |
242 | * Bit 7, Bit 4, and Bit 3 of val entry: | |
243 | * | |
244 | * PAT/PSE (bit 7) ... PCD (bit 4) .. PWT (bit 3). | |
245 | * | |
246 | * If all bits are off, then we are using PAT0. If bit 3 turned on, | |
247 | * then we are using PAT1, if bit 3 and bit 4, then PAT2.. | |
248 | * | |
249 | * As you can see, the Linux PAT1 translates to PAT4 under Xen. Which means | |
250 | * that if a guest that follows Linux's PAT setup and would like to set Write | |
251 | * Combined on pages it MUST use PAT4 entry. Meaning that Bit 7 (PAGE_PAT) is | |
252 | * set. For example, under Linux it only uses PAT0, PAT1, and PAT2 for the | |
253 | * caching as: | |
254 | * | |
255 | * WB = none (so PAT0) | |
256 | * WC = PWT (bit 3 on) | |
257 | * UC = PWT | PCD (bit 3 and 4 are on). | |
258 | * | |
259 | * To make it work with Xen, it needs to translate the WC bit as so: | |
260 | * | |
261 | * PWT (so bit 3 on) --> PAT (so bit 7 is on) and clear bit 3 | |
262 | * | |
263 | * And to translate back it would: | |
264 | * | |
265 | * PAT (bit 7 on) --> PWT (bit 3 on) and clear bit 7. | |
a42089dd | 266 | */ |
e57778a1 JF |
267 | #define MMU_NORMAL_PT_UPDATE 0 /* checked '*ptr = val'. ptr is MA. */ |
268 | #define MMU_MACHPHYS_UPDATE 1 /* ptr = MA of frame to modify entry for */ | |
269 | #define MMU_PT_UPDATE_PRESERVE_AD 2 /* atomically: *ptr = val | (*ptr&(A|D)) */ | |
a42089dd JF |
270 | |
271 | /* | |
272 | * MMU EXTENDED OPERATIONS | |
273 | * | |
bca9b685 JG |
274 | * enum neg_errnoval HYPERVISOR_mmuext_op(mmuext_op_t uops[], |
275 | * unsigned int count, | |
276 | * unsigned int *pdone, | |
277 | * unsigned int foreigndom) | |
278 | */ | |
279 | /* HYPERVISOR_mmuext_op() accepts a list of mmuext_op structures. | |
a42089dd JF |
280 | * A foreigndom (FD) can be specified (or DOMID_SELF for none). |
281 | * Where the FD has some effect, it is described below. | |
282 | * | |
283 | * cmd: MMUEXT_(UN)PIN_*_TABLE | |
284 | * mfn: Machine frame number to be (un)pinned as a p.t. page. | |
285 | * The frame must belong to the FD, if one is specified. | |
286 | * | |
287 | * cmd: MMUEXT_NEW_BASEPTR | |
288 | * mfn: Machine frame number of new page-table base to install in MMU. | |
289 | * | |
290 | * cmd: MMUEXT_NEW_USER_BASEPTR [x86/64 only] | |
291 | * mfn: Machine frame number of new page-table base to install in MMU | |
292 | * when in user space. | |
293 | * | |
294 | * cmd: MMUEXT_TLB_FLUSH_LOCAL | |
295 | * No additional arguments. Flushes local TLB. | |
296 | * | |
297 | * cmd: MMUEXT_INVLPG_LOCAL | |
298 | * linear_addr: Linear address to be flushed from the local TLB. | |
299 | * | |
300 | * cmd: MMUEXT_TLB_FLUSH_MULTI | |
301 | * vcpumask: Pointer to bitmap of VCPUs to be flushed. | |
302 | * | |
303 | * cmd: MMUEXT_INVLPG_MULTI | |
304 | * linear_addr: Linear address to be flushed. | |
305 | * vcpumask: Pointer to bitmap of VCPUs to be flushed. | |
306 | * | |
307 | * cmd: MMUEXT_TLB_FLUSH_ALL | |
308 | * No additional arguments. Flushes all VCPUs' TLBs. | |
309 | * | |
310 | * cmd: MMUEXT_INVLPG_ALL | |
311 | * linear_addr: Linear address to be flushed from all VCPUs' TLBs. | |
312 | * | |
313 | * cmd: MMUEXT_FLUSH_CACHE | |
314 | * No additional arguments. Writes back and flushes cache contents. | |
315 | * | |
bca9b685 JG |
316 | * cmd: MMUEXT_FLUSH_CACHE_GLOBAL |
317 | * No additional arguments. Writes back and flushes cache contents | |
318 | * on all CPUs in the system. | |
319 | * | |
a42089dd JF |
320 | * cmd: MMUEXT_SET_LDT |
321 | * linear_addr: Linear address of LDT base (NB. must be page-aligned). | |
322 | * nr_ents: Number of entries in LDT. | |
bca9b685 JG |
323 | * |
324 | * cmd: MMUEXT_CLEAR_PAGE | |
325 | * mfn: Machine frame number to be cleared. | |
326 | * | |
327 | * cmd: MMUEXT_COPY_PAGE | |
328 | * mfn: Machine frame number of the destination page. | |
329 | * src_mfn: Machine frame number of the source page. | |
330 | * | |
331 | * cmd: MMUEXT_[UN]MARK_SUPER | |
332 | * mfn: Machine frame number of head of superpage to be [un]marked. | |
a42089dd JF |
333 | */ |
334 | #define MMUEXT_PIN_L1_TABLE 0 | |
335 | #define MMUEXT_PIN_L2_TABLE 1 | |
336 | #define MMUEXT_PIN_L3_TABLE 2 | |
337 | #define MMUEXT_PIN_L4_TABLE 3 | |
338 | #define MMUEXT_UNPIN_TABLE 4 | |
339 | #define MMUEXT_NEW_BASEPTR 5 | |
340 | #define MMUEXT_TLB_FLUSH_LOCAL 6 | |
341 | #define MMUEXT_INVLPG_LOCAL 7 | |
342 | #define MMUEXT_TLB_FLUSH_MULTI 8 | |
343 | #define MMUEXT_INVLPG_MULTI 9 | |
344 | #define MMUEXT_TLB_FLUSH_ALL 10 | |
345 | #define MMUEXT_INVLPG_ALL 11 | |
346 | #define MMUEXT_FLUSH_CACHE 12 | |
347 | #define MMUEXT_SET_LDT 13 | |
348 | #define MMUEXT_NEW_USER_BASEPTR 15 | |
bca9b685 JG |
349 | #define MMUEXT_CLEAR_PAGE 16 |
350 | #define MMUEXT_COPY_PAGE 17 | |
351 | #define MMUEXT_FLUSH_CACHE_GLOBAL 18 | |
352 | #define MMUEXT_MARK_SUPER 19 | |
353 | #define MMUEXT_UNMARK_SUPER 20 | |
a42089dd JF |
354 | |
355 | #ifndef __ASSEMBLY__ | |
356 | struct mmuext_op { | |
357 | unsigned int cmd; | |
358 | union { | |
bca9b685 JG |
359 | /* [UN]PIN_TABLE, NEW_BASEPTR, NEW_USER_BASEPTR |
360 | * CLEAR_PAGE, COPY_PAGE, [UN]MARK_SUPER */ | |
bd3f79b7 | 361 | xen_pfn_t mfn; |
a42089dd JF |
362 | /* INVLPG_LOCAL, INVLPG_ALL, SET_LDT */ |
363 | unsigned long linear_addr; | |
364 | } arg1; | |
365 | union { | |
366 | /* SET_LDT */ | |
367 | unsigned int nr_ents; | |
368 | /* TLB_FLUSH_MULTI, INVLPG_MULTI */ | |
369 | void *vcpumask; | |
bca9b685 JG |
370 | /* COPY_PAGE */ |
371 | xen_pfn_t src_mfn; | |
a42089dd JF |
372 | } arg2; |
373 | }; | |
374 | DEFINE_GUEST_HANDLE_STRUCT(mmuext_op); | |
375 | #endif | |
376 | ||
377 | /* These are passed as 'flags' to update_va_mapping. They can be ORed. */ | |
378 | /* When specifying UVMF_MULTI, also OR in a pointer to a CPU bitmap. */ | |
379 | /* UVMF_LOCAL is merely UVMF_MULTI with a NULL bitmap pointer. */ | |
380 | #define UVMF_NONE (0UL<<0) /* No flushing at all. */ | |
381 | #define UVMF_TLB_FLUSH (1UL<<0) /* Flush entire TLB(s). */ | |
382 | #define UVMF_INVLPG (2UL<<0) /* Flush only one entry. */ | |
383 | #define UVMF_FLUSHTYPE_MASK (3UL<<0) | |
384 | #define UVMF_MULTI (0UL<<2) /* Flush subset of TLBs. */ | |
385 | #define UVMF_LOCAL (0UL<<2) /* Flush local TLB. */ | |
386 | #define UVMF_ALL (1UL<<2) /* Flush all TLBs. */ | |
387 | ||
388 | /* | |
389 | * Commands to HYPERVISOR_console_io(). | |
390 | */ | |
391 | #define CONSOLEIO_write 0 | |
392 | #define CONSOLEIO_read 1 | |
393 | ||
394 | /* | |
395 | * Commands to HYPERVISOR_vm_assist(). | |
396 | */ | |
397 | #define VMASST_CMD_enable 0 | |
398 | #define VMASST_CMD_disable 1 | |
bca9b685 JG |
399 | |
400 | /* x86/32 guests: simulate full 4GB segment limits. */ | |
a42089dd | 401 | #define VMASST_TYPE_4gb_segments 0 |
bca9b685 JG |
402 | |
403 | /* x86/32 guests: trap (vector 15) whenever above vmassist is used. */ | |
a42089dd | 404 | #define VMASST_TYPE_4gb_segments_notify 1 |
bca9b685 JG |
405 | |
406 | /* | |
407 | * x86 guests: support writes to bottom-level PTEs. | |
408 | * NB1. Page-directory entries cannot be written. | |
409 | * NB2. Guest must continue to remove all writable mappings of PTEs. | |
410 | */ | |
a42089dd | 411 | #define VMASST_TYPE_writable_pagetables 2 |
bca9b685 JG |
412 | |
413 | /* x86/PAE guests: support PDPTs above 4GB. */ | |
a42089dd | 414 | #define VMASST_TYPE_pae_extended_cr3 3 |
bca9b685 | 415 | |
7ba8dba9 JG |
416 | /* |
417 | * x86 guests: Sane behaviour for virtual iopl | |
418 | * - virtual iopl updated from do_iret() hypercalls. | |
419 | * - virtual iopl reported in bounce frames. | |
420 | * - guest kernels assumed to be level 0 for the purpose of iopl checks. | |
421 | */ | |
422 | #define VMASST_TYPE_architectural_iopl 4 | |
423 | ||
424 | /* | |
425 | * All guests: activate update indicator in vcpu_runstate_info | |
426 | * Enable setting the XEN_RUNSTATE_UPDATE flag in guest memory mapped | |
427 | * vcpu_runstate_info during updates of the runstate information. | |
428 | */ | |
429 | #define VMASST_TYPE_runstate_update_flag 5 | |
430 | ||
431 | #define MAX_VMASST_TYPE 5 | |
a42089dd JF |
432 | |
433 | #ifndef __ASSEMBLY__ | |
434 | ||
435 | typedef uint16_t domid_t; | |
436 | ||
437 | /* Domain ids >= DOMID_FIRST_RESERVED cannot be used for ordinary domains. */ | |
438 | #define DOMID_FIRST_RESERVED (0x7FF0U) | |
439 | ||
440 | /* DOMID_SELF is used in certain contexts to refer to oneself. */ | |
441 | #define DOMID_SELF (0x7FF0U) | |
442 | ||
443 | /* | |
444 | * DOMID_IO is used to restrict page-table updates to mapping I/O memory. | |
445 | * Although no Foreign Domain need be specified to map I/O pages, DOMID_IO | |
446 | * is useful to ensure that no mappings to the OS's own heap are accidentally | |
447 | * installed. (e.g., in Linux this could cause havoc as reference counts | |
448 | * aren't adjusted on the I/O-mapping code path). | |
449 | * This only makes sense in MMUEXT_SET_FOREIGNDOM, but in that context can | |
450 | * be specified by any calling domain. | |
451 | */ | |
452 | #define DOMID_IO (0x7FF1U) | |
453 | ||
454 | /* | |
455 | * DOMID_XEN is used to allow privileged domains to map restricted parts of | |
456 | * Xen's heap space (e.g., the machine_to_phys table). | |
457 | * This only makes sense in MMUEXT_SET_FOREIGNDOM, and is only permitted if | |
458 | * the caller is privileged. | |
459 | */ | |
460 | #define DOMID_XEN (0x7FF2U) | |
461 | ||
bca9b685 JG |
462 | /* DOMID_COW is used as the owner of sharable pages */ |
463 | #define DOMID_COW (0x7FF3U) | |
464 | ||
465 | /* DOMID_INVALID is used to identify pages with unknown owner. */ | |
466 | #define DOMID_INVALID (0x7FF4U) | |
467 | ||
468 | /* Idle domain. */ | |
469 | #define DOMID_IDLE (0x7FFFU) | |
470 | ||
a42089dd JF |
471 | /* |
472 | * Send an array of these to HYPERVISOR_mmu_update(). | |
473 | * NB. The fields are natural pointer/address size for this architecture. | |
474 | */ | |
475 | struct mmu_update { | |
476 | uint64_t ptr; /* Machine address of PTE. */ | |
477 | uint64_t val; /* New contents of PTE. */ | |
478 | }; | |
479 | DEFINE_GUEST_HANDLE_STRUCT(mmu_update); | |
480 | ||
481 | /* | |
482 | * Send an array of these to HYPERVISOR_multicall(). | |
bca9b685 JG |
483 | * NB. The fields are logically the natural register size for this |
484 | * architecture. In cases where xen_ulong_t is larger than this then | |
485 | * any unused bits in the upper portion must be zero. | |
a42089dd JF |
486 | */ |
487 | struct multicall_entry { | |
5e40704e IC |
488 | xen_ulong_t op; |
489 | xen_long_t result; | |
490 | xen_ulong_t args[6]; | |
a42089dd JF |
491 | }; |
492 | DEFINE_GUEST_HANDLE_STRUCT(multicall_entry); | |
493 | ||
a42089dd JF |
494 | struct vcpu_time_info { |
495 | /* | |
496 | * Updates to the following values are preceded and followed | |
497 | * by an increment of 'version'. The guest can therefore | |
498 | * detect updates by looking for changes to 'version'. If the | |
499 | * least-significant bit of the version number is set then an | |
500 | * update is in progress and the guest must wait to read a | |
501 | * consistent set of values. The correct way to interact with | |
502 | * the version number is similar to Linux's seqlock: see the | |
503 | * implementations of read_seqbegin/read_seqretry. | |
504 | */ | |
505 | uint32_t version; | |
506 | uint32_t pad0; | |
507 | uint64_t tsc_timestamp; /* TSC at last update of time vals. */ | |
508 | uint64_t system_time; /* Time, in nanosecs, since boot. */ | |
509 | /* | |
510 | * Current system time: | |
511 | * system_time + ((tsc - tsc_timestamp) << tsc_shift) * tsc_to_system_mul | |
512 | * CPU frequency (Hz): | |
513 | * ((10^9 << 32) / tsc_to_system_mul) >> tsc_shift | |
514 | */ | |
515 | uint32_t tsc_to_system_mul; | |
516 | int8_t tsc_shift; | |
517 | int8_t pad1[3]; | |
518 | }; /* 32 bytes */ | |
519 | ||
520 | struct vcpu_info { | |
521 | /* | |
522 | * 'evtchn_upcall_pending' is written non-zero by Xen to indicate | |
523 | * a pending notification for a particular VCPU. It is then cleared | |
524 | * by the guest OS /before/ checking for pending work, thus avoiding | |
525 | * a set-and-check race. Note that the mask is only accessed by Xen | |
526 | * on the CPU that is currently hosting the VCPU. This means that the | |
527 | * pending and mask flags can be updated by the guest without special | |
528 | * synchronisation (i.e., no need for the x86 LOCK prefix). | |
529 | * This may seem suboptimal because if the pending flag is set by | |
530 | * a different CPU then an IPI may be scheduled even when the mask | |
531 | * is set. However, note: | |
532 | * 1. The task of 'interrupt holdoff' is covered by the per-event- | |
533 | * channel mask bits. A 'noisy' event that is continually being | |
534 | * triggered can be masked at source at this very precise | |
535 | * granularity. | |
536 | * 2. The main purpose of the per-VCPU mask is therefore to restrict | |
537 | * reentrant execution: whether for concurrency control, or to | |
538 | * prevent unbounded stack usage. Whatever the purpose, we expect | |
539 | * that the mask will be asserted only for short periods at a time, | |
540 | * and so the likelihood of a 'spurious' IPI is suitably small. | |
541 | * The mask is read before making an event upcall to the guest: a | |
542 | * non-zero mask therefore guarantees that the VCPU will not receive | |
543 | * an upcall activation. The mask is cleared when the VCPU requests | |
544 | * to block: this avoids wakeup-waiting races. | |
545 | */ | |
546 | uint8_t evtchn_upcall_pending; | |
547 | uint8_t evtchn_upcall_mask; | |
c81611c4 | 548 | xen_ulong_t evtchn_pending_sel; |
a42089dd | 549 | struct arch_vcpu_info arch; |
1c7b67f7 | 550 | struct pvclock_vcpu_time_info time; |
a42089dd JF |
551 | }; /* 64 bytes (x86) */ |
552 | ||
553 | /* | |
554 | * Xen/kernel shared data -- pointer provided in start_info. | |
555 | * NB. We expect that this struct is smaller than a page. | |
556 | */ | |
557 | struct shared_info { | |
558 | struct vcpu_info vcpu_info[MAX_VIRT_CPUS]; | |
559 | ||
560 | /* | |
561 | * A domain can create "event channels" on which it can send and receive | |
562 | * asynchronous event notifications. There are three classes of event that | |
563 | * are delivered by this mechanism: | |
564 | * 1. Bi-directional inter- and intra-domain connections. Domains must | |
565 | * arrange out-of-band to set up a connection (usually by allocating | |
566 | * an unbound 'listener' port and avertising that via a storage service | |
567 | * such as xenstore). | |
568 | * 2. Physical interrupts. A domain with suitable hardware-access | |
569 | * privileges can bind an event-channel port to a physical interrupt | |
570 | * source. | |
571 | * 3. Virtual interrupts ('events'). A domain can bind an event-channel | |
572 | * port to a virtual interrupt source, such as the virtual-timer | |
573 | * device or the emergency console. | |
574 | * | |
575 | * Event channels are addressed by a "port index". Each channel is | |
576 | * associated with two bits of information: | |
577 | * 1. PENDING -- notifies the domain that there is a pending notification | |
578 | * to be processed. This bit is cleared by the guest. | |
579 | * 2. MASK -- if this bit is clear then a 0->1 transition of PENDING | |
580 | * will cause an asynchronous upcall to be scheduled. This bit is only | |
581 | * updated by the guest. It is read-only within Xen. If a channel | |
582 | * becomes pending while the channel is masked then the 'edge' is lost | |
583 | * (i.e., when the channel is unmasked, the guest must manually handle | |
584 | * pending notifications as no upcall will be scheduled by Xen). | |
585 | * | |
586 | * To expedite scanning of pending notifications, any 0->1 pending | |
587 | * transition on an unmasked channel causes a corresponding bit in a | |
588 | * per-vcpu selector word to be set. Each bit in the selector covers a | |
589 | * 'C long' in the PENDING bitfield array. | |
590 | */ | |
c81611c4 IC |
591 | xen_ulong_t evtchn_pending[sizeof(xen_ulong_t) * 8]; |
592 | xen_ulong_t evtchn_mask[sizeof(xen_ulong_t) * 8]; | |
a42089dd JF |
593 | |
594 | /* | |
595 | * Wallclock time: updated only by control software. Guests should base | |
596 | * their gettimeofday() syscall on this wallclock-base value. | |
597 | */ | |
1c7b67f7 | 598 | struct pvclock_wall_clock wc; |
a42089dd JF |
599 | |
600 | struct arch_shared_info arch; | |
601 | ||
602 | }; | |
603 | ||
604 | /* | |
17fb46b1 JG |
605 | * Start-of-day memory layout |
606 | * | |
a42089dd JF |
607 | * 1. The domain is started within contiguous virtual-memory region. |
608 | * 2. The contiguous region begins and ends on an aligned 4MB boundary. | |
17fb46b1 | 609 | * 3. This the order of bootstrap elements in the initial virtual region: |
a42089dd JF |
610 | * a. relocated kernel image |
611 | * b. initial ram disk [mod_start, mod_len] | |
17fb46b1 | 612 | * (may be omitted) |
a42089dd | 613 | * c. list of allocated page frames [mfn_list, nr_pages] |
17fb46b1 | 614 | * (unless relocated due to XEN_ELFNOTE_INIT_P2M) |
a42089dd | 615 | * d. start_info_t structure [register ESI (x86)] |
17fb46b1 JG |
616 | * in case of dom0 this page contains the console info, too |
617 | * e. unless dom0: xenstore ring page | |
618 | * f. unless dom0: console ring page | |
619 | * g. bootstrap page tables [pt_base, CR3 (x86)] | |
620 | * h. bootstrap stack [register ESP (x86)] | |
621 | * 4. Bootstrap elements are packed together, but each is 4kB-aligned. | |
622 | * 5. The list of page frames forms a contiguous 'pseudo-physical' memory | |
a42089dd JF |
623 | * layout for the domain. In particular, the bootstrap virtual-memory |
624 | * region is a 1:1 mapping to the first section of the pseudo-physical map. | |
17fb46b1 | 625 | * 6. All bootstrap elements are mapped read-writable for the guest OS. The |
a42089dd | 626 | * only exception is the bootstrap page table, which is mapped read-only. |
17fb46b1 | 627 | * 7. There is guaranteed to be at least 512kB padding after the final |
a42089dd JF |
628 | * bootstrap element. If necessary, the bootstrap virtual region is |
629 | * extended by an extra 4MB to ensure this. | |
630 | */ | |
631 | ||
632 | #define MAX_GUEST_CMDLINE 1024 | |
633 | struct start_info { | |
634 | /* THE FOLLOWING ARE FILLED IN BOTH ON INITIAL BOOT AND ON RESUME. */ | |
635 | char magic[32]; /* "xen-<version>-<platform>". */ | |
636 | unsigned long nr_pages; /* Total pages allocated to this domain. */ | |
637 | unsigned long shared_info; /* MACHINE address of shared info struct. */ | |
638 | uint32_t flags; /* SIF_xxx flags. */ | |
bd3f79b7 | 639 | xen_pfn_t store_mfn; /* MACHINE page number of shared page. */ |
a42089dd JF |
640 | uint32_t store_evtchn; /* Event channel for store communication. */ |
641 | union { | |
642 | struct { | |
bd3f79b7 | 643 | xen_pfn_t mfn; /* MACHINE page number of console page. */ |
a42089dd JF |
644 | uint32_t evtchn; /* Event channel for console page. */ |
645 | } domU; | |
646 | struct { | |
647 | uint32_t info_off; /* Offset of console_info struct. */ | |
648 | uint32_t info_size; /* Size of console_info struct from start.*/ | |
649 | } dom0; | |
650 | } console; | |
651 | /* THE FOLLOWING ARE ONLY FILLED IN ON INITIAL BOOT (NOT RESUME). */ | |
652 | unsigned long pt_base; /* VIRTUAL address of page directory. */ | |
653 | unsigned long nr_pt_frames; /* Number of bootstrap p.t. frames. */ | |
654 | unsigned long mfn_list; /* VIRTUAL address of page-frame list. */ | |
655 | unsigned long mod_start; /* VIRTUAL address of pre-loaded module. */ | |
656 | unsigned long mod_len; /* Size (bytes) of pre-loaded module. */ | |
657 | int8_t cmd_line[MAX_GUEST_CMDLINE]; | |
bca9b685 JG |
658 | /* The pfn range here covers both page table and p->m table frames. */ |
659 | unsigned long first_p2m_pfn;/* 1st pfn forming initial P->M table. */ | |
660 | unsigned long nr_p2m_frames;/* # of pfns forming initial P->M table. */ | |
a42089dd JF |
661 | }; |
662 | ||
bca9b685 | 663 | /* These flags are passed in the 'flags' field of start_info_t. */ |
17fb46b1 JG |
664 | #define SIF_PRIVILEGED (1<<0) /* Is the domain privileged? */ |
665 | #define SIF_INITDOMAIN (1<<1) /* Is this the initial control domain? */ | |
666 | #define SIF_MULTIBOOT_MOD (1<<2) /* Is mod_start a multiboot module? */ | |
667 | #define SIF_MOD_START_PFN (1<<3) /* Is mod_start a PFN? */ | |
668 | #define SIF_VIRT_P2M_4TOOLS (1<<4) /* Do Xen tools understand a virt. mapped */ | |
669 | /* P->M making the 3 level tree obsolete? */ | |
bca9b685 JG |
670 | #define SIF_PM_MASK (0xFF<<8) /* reserve 1 byte for xen-pm options */ |
671 | ||
672 | /* | |
673 | * A multiboot module is a package containing modules very similar to a | |
674 | * multiboot module array. The only differences are: | |
675 | * - the array of module descriptors is by convention simply at the beginning | |
676 | * of the multiboot module, | |
677 | * - addresses in the module descriptors are based on the beginning of the | |
678 | * multiboot module, | |
679 | * - the number of modules is determined by a termination descriptor that has | |
680 | * mod_start == 0. | |
681 | * | |
682 | * This permits to both build it statically and reference it in a configuration | |
683 | * file, and let the PV guest easily rebase the addresses to virtual addresses | |
684 | * and at the same time count the number of modules. | |
685 | */ | |
686 | struct xen_multiboot_mod_list { | |
687 | /* Address of first byte of the module */ | |
688 | uint32_t mod_start; | |
689 | /* Address of last byte of the module (inclusive) */ | |
690 | uint32_t mod_end; | |
691 | /* Address of zero-terminated command line */ | |
692 | uint32_t cmdline; | |
693 | /* Unused, must be zero */ | |
694 | uint32_t pad; | |
695 | }; | |
696 | /* | |
697 | * The console structure in start_info.console.dom0 | |
698 | * | |
699 | * This structure includes a variety of information required to | |
700 | * have a working VGA/VESA console. | |
701 | */ | |
c2419b4a JF |
702 | struct dom0_vga_console_info { |
703 | uint8_t video_type; | |
704 | #define XEN_VGATYPE_TEXT_MODE_3 0x03 | |
705 | #define XEN_VGATYPE_VESA_LFB 0x23 | |
aa387d63 | 706 | #define XEN_VGATYPE_EFI_LFB 0x70 |
c2419b4a JF |
707 | |
708 | union { | |
709 | struct { | |
710 | /* Font height, in pixels. */ | |
711 | uint16_t font_height; | |
712 | /* Cursor location (column, row). */ | |
713 | uint16_t cursor_x, cursor_y; | |
714 | /* Number of rows and columns (dimensions in characters). */ | |
715 | uint16_t rows, columns; | |
716 | } text_mode_3; | |
717 | ||
718 | struct { | |
719 | /* Width and height, in pixels. */ | |
720 | uint16_t width, height; | |
721 | /* Bytes per scan line. */ | |
722 | uint16_t bytes_per_line; | |
723 | /* Bits per pixel. */ | |
724 | uint16_t bits_per_pixel; | |
725 | /* LFB physical address, and size (in units of 64kB). */ | |
726 | uint32_t lfb_base; | |
727 | uint32_t lfb_size; | |
728 | /* RGB mask offsets and sizes, as defined by VBE 1.2+ */ | |
729 | uint8_t red_pos, red_size; | |
730 | uint8_t green_pos, green_size; | |
731 | uint8_t blue_pos, blue_size; | |
732 | uint8_t rsvd_pos, rsvd_size; | |
733 | ||
734 | /* VESA capabilities (offset 0xa, VESA command 0x4f00). */ | |
735 | uint32_t gbl_caps; | |
736 | /* Mode attributes (offset 0x0, VESA command 0x4f01). */ | |
737 | uint16_t mode_attrs; | |
738 | } vesa_lfb; | |
739 | } u; | |
740 | }; | |
741 | ||
a42089dd JF |
742 | typedef uint64_t cpumap_t; |
743 | ||
744 | typedef uint8_t xen_domain_handle_t[16]; | |
745 | ||
746 | /* Turn a plain number into a C unsigned long constant. */ | |
747 | #define __mk_unsigned_long(x) x ## UL | |
748 | #define mk_unsigned_long(x) __mk_unsigned_long(x) | |
749 | ||
5bc20fc5 DM |
750 | #define TMEM_SPEC_VERSION 1 |
751 | ||
752 | struct tmem_op { | |
753 | uint32_t cmd; | |
754 | int32_t pool_id; | |
755 | union { | |
756 | struct { /* for cmd == TMEM_NEW_POOL */ | |
757 | uint64_t uuid[2]; | |
758 | uint32_t flags; | |
759 | } new; | |
760 | struct { | |
761 | uint64_t oid[3]; | |
762 | uint32_t index; | |
763 | uint32_t tmem_offset; | |
764 | uint32_t pfn_offset; | |
765 | uint32_t len; | |
766 | GUEST_HANDLE(void) gmfn; /* guest machine page frame */ | |
767 | } gen; | |
768 | } u; | |
769 | }; | |
770 | ||
0f9f5a95 AL |
771 | DEFINE_GUEST_HANDLE(u64); |
772 | ||
a42089dd JF |
773 | #else /* __ASSEMBLY__ */ |
774 | ||
775 | /* In assembly code we cannot use C numeric constant suffixes. */ | |
776 | #define mk_unsigned_long(x) x | |
777 | ||
778 | #endif /* !__ASSEMBLY__ */ | |
779 | ||
780 | #endif /* __XEN_PUBLIC_XEN_H__ */ |