]> git.proxmox.com Git - mirror_qemu.git/blame - ioport.c
nvdimm acpi: build ACPI nvdimm devices
[mirror_qemu.git] / ioport.c
CommitLineData
32993977
IY
1/*
2 * QEMU System Emulator
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24/*
25 * splitted out ioport related stuffs from vl.c.
26 */
27
022c62cb 28#include "exec/ioport.h"
bd3c9aa5 29#include "trace.h"
022c62cb 30#include "exec/memory.h"
b40acf99 31#include "exec/address-spaces.h"
32993977 32
b40acf99
JK
33typedef struct MemoryRegionPortioList {
34 MemoryRegion mr;
35 void *portio_opaque;
36 MemoryRegionPortio ports[];
37} MemoryRegionPortioList;
38
3bb28b72
JK
39static uint64_t unassigned_io_read(void *opaque, hwaddr addr, unsigned size)
40{
41 return -1ULL;
42}
43
44static void unassigned_io_write(void *opaque, hwaddr addr, uint64_t val,
45 unsigned size)
46{
47}
48
49const MemoryRegionOps unassigned_io_ops = {
50 .read = unassigned_io_read,
51 .write = unassigned_io_write,
52 .endianness = DEVICE_NATIVE_ENDIAN,
53};
54
c227f099 55void cpu_outb(pio_addr_t addr, uint8_t val)
32993977 56{
6f94b7d9 57 trace_cpu_out(addr, 'b', val);
5c9eb028
PM
58 address_space_write(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED,
59 &val, 1);
32993977
IY
60}
61
c227f099 62void cpu_outw(pio_addr_t addr, uint16_t val)
32993977 63{
b40acf99
JK
64 uint8_t buf[2];
65
6f94b7d9 66 trace_cpu_out(addr, 'w', val);
b40acf99 67 stw_p(buf, val);
5c9eb028
PM
68 address_space_write(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED,
69 buf, 2);
32993977
IY
70}
71
c227f099 72void cpu_outl(pio_addr_t addr, uint32_t val)
32993977 73{
b40acf99
JK
74 uint8_t buf[4];
75
6f94b7d9 76 trace_cpu_out(addr, 'l', val);
b40acf99 77 stl_p(buf, val);
5c9eb028
PM
78 address_space_write(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED,
79 buf, 4);
32993977
IY
80}
81
c227f099 82uint8_t cpu_inb(pio_addr_t addr)
32993977 83{
07323531 84 uint8_t val;
b40acf99 85
5c9eb028
PM
86 address_space_read(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED,
87 &val, 1);
6f94b7d9 88 trace_cpu_in(addr, 'b', val);
32993977
IY
89 return val;
90}
91
c227f099 92uint16_t cpu_inw(pio_addr_t addr)
32993977 93{
b40acf99 94 uint8_t buf[2];
07323531 95 uint16_t val;
b40acf99 96
5c9eb028 97 address_space_read(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, buf, 2);
b40acf99 98 val = lduw_p(buf);
6f94b7d9 99 trace_cpu_in(addr, 'w', val);
32993977
IY
100 return val;
101}
102
c227f099 103uint32_t cpu_inl(pio_addr_t addr)
32993977 104{
b40acf99 105 uint8_t buf[4];
07323531 106 uint32_t val;
b40acf99 107
5c9eb028 108 address_space_read(&address_space_io, addr, MEMTXATTRS_UNSPECIFIED, buf, 4);
b40acf99 109 val = ldl_p(buf);
6f94b7d9 110 trace_cpu_in(addr, 'l', val);
32993977
IY
111 return val;
112}
6bf9fd43
AK
113
114void portio_list_init(PortioList *piolist,
db10ca90 115 Object *owner,
6bf9fd43
AK
116 const MemoryRegionPortio *callbacks,
117 void *opaque, const char *name)
118{
119 unsigned n = 0;
120
121 while (callbacks[n].size) {
122 ++n;
123 }
124
125 piolist->ports = callbacks;
126 piolist->nr = 0;
127 piolist->regions = g_new0(MemoryRegion *, n);
128 piolist->address_space = NULL;
129 piolist->opaque = opaque;
db10ca90 130 piolist->owner = owner;
6bf9fd43 131 piolist->name = name;
c76bc480
JK
132 piolist->flush_coalesced_mmio = false;
133}
134
135void portio_list_set_flush_coalesced(PortioList *piolist)
136{
137 piolist->flush_coalesced_mmio = true;
6bf9fd43
AK
138}
139
140void portio_list_destroy(PortioList *piolist)
141{
e3fb0ade
PB
142 MemoryRegionPortioList *mrpio;
143 unsigned i;
144
145 for (i = 0; i < piolist->nr; ++i) {
146 mrpio = container_of(piolist->regions[i], MemoryRegionPortioList, mr);
d8d95814 147 object_unparent(OBJECT(&mrpio->mr));
e3fb0ade
PB
148 g_free(mrpio);
149 }
6bf9fd43
AK
150 g_free(piolist->regions);
151}
152
b40acf99
JK
153static const MemoryRegionPortio *find_portio(MemoryRegionPortioList *mrpio,
154 uint64_t offset, unsigned size,
155 bool write)
156{
157 const MemoryRegionPortio *mrp;
158
159 for (mrp = mrpio->ports; mrp->size; ++mrp) {
160 if (offset >= mrp->offset && offset < mrp->offset + mrp->len &&
161 size == mrp->size &&
162 (write ? (bool)mrp->write : (bool)mrp->read)) {
163 return mrp;
164 }
165 }
166 return NULL;
167}
168
169static uint64_t portio_read(void *opaque, hwaddr addr, unsigned size)
170{
171 MemoryRegionPortioList *mrpio = opaque;
172 const MemoryRegionPortio *mrp = find_portio(mrpio, addr, size, false);
173 uint64_t data;
174
175 data = ((uint64_t)1 << (size * 8)) - 1;
176 if (mrp) {
177 data = mrp->read(mrpio->portio_opaque, mrp->base + addr);
178 } else if (size == 2) {
179 mrp = find_portio(mrpio, addr, 1, false);
147ed379
PB
180 if (mrp) {
181 data = mrp->read(mrpio->portio_opaque, mrp->base + addr);
182 if (addr + 1 < mrp->offset + mrp->len) {
183 data |= mrp->read(mrpio->portio_opaque, mrp->base + addr + 1) << 8;
184 } else {
185 data |= 0xff00;
186 }
187 }
b40acf99
JK
188 }
189 return data;
190}
191
192static void portio_write(void *opaque, hwaddr addr, uint64_t data,
193 unsigned size)
194{
195 MemoryRegionPortioList *mrpio = opaque;
196 const MemoryRegionPortio *mrp = find_portio(mrpio, addr, size, true);
197
198 if (mrp) {
199 mrp->write(mrpio->portio_opaque, mrp->base + addr, data);
200 } else if (size == 2) {
201 mrp = find_portio(mrpio, addr, 1, true);
147ed379
PB
202 if (mrp) {
203 mrp->write(mrpio->portio_opaque, mrp->base + addr, data & 0xff);
204 if (addr + 1 < mrp->offset + mrp->len) {
205 mrp->write(mrpio->portio_opaque, mrp->base + addr + 1, data >> 8);
206 }
207 }
b40acf99
JK
208 }
209}
210
211static const MemoryRegionOps portio_ops = {
212 .read = portio_read,
213 .write = portio_write,
f36a6382 214 .endianness = DEVICE_LITTLE_ENDIAN,
b40acf99
JK
215 .valid.unaligned = true,
216 .impl.unaligned = true,
217};
218
6bf9fd43
AK
219static void portio_list_add_1(PortioList *piolist,
220 const MemoryRegionPortio *pio_init,
221 unsigned count, unsigned start,
222 unsigned off_low, unsigned off_high)
223{
b40acf99 224 MemoryRegionPortioList *mrpio;
6bf9fd43
AK
225 unsigned i;
226
227 /* Copy the sub-list and null-terminate it. */
b40acf99
JK
228 mrpio = g_malloc0(sizeof(MemoryRegionPortioList) +
229 sizeof(MemoryRegionPortio) * (count + 1));
230 mrpio->portio_opaque = piolist->opaque;
231 memcpy(mrpio->ports, pio_init, sizeof(MemoryRegionPortio) * count);
232 memset(mrpio->ports + count, 0, sizeof(MemoryRegionPortio));
6bf9fd43
AK
233
234 /* Adjust the offsets to all be zero-based for the region. */
235 for (i = 0; i < count; ++i) {
b40acf99
JK
236 mrpio->ports[i].offset -= off_low;
237 mrpio->ports[i].base = start + off_low;
6bf9fd43
AK
238 }
239
db10ca90
PB
240 memory_region_init_io(&mrpio->mr, piolist->owner, &portio_ops, mrpio,
241 piolist->name, off_high - off_low);
c76bc480
JK
242 if (piolist->flush_coalesced_mmio) {
243 memory_region_set_flush_coalesced(&mrpio->mr);
244 }
6bf9fd43 245 memory_region_add_subregion(piolist->address_space,
b40acf99
JK
246 start + off_low, &mrpio->mr);
247 piolist->regions[piolist->nr] = &mrpio->mr;
de58ac72 248 ++piolist->nr;
6bf9fd43
AK
249}
250
251void portio_list_add(PortioList *piolist,
252 MemoryRegion *address_space,
253 uint32_t start)
254{
255 const MemoryRegionPortio *pio, *pio_start = piolist->ports;
256 unsigned int off_low, off_high, off_last, count;
257
258 piolist->address_space = address_space;
259
260 /* Handle the first entry specially. */
261 off_last = off_low = pio_start->offset;
4080a13c 262 off_high = off_low + pio_start->len + pio_start->size - 1;
6bf9fd43
AK
263 count = 1;
264
265 for (pio = pio_start + 1; pio->size != 0; pio++, count++) {
266 /* All entries must be sorted by offset. */
267 assert(pio->offset >= off_last);
268 off_last = pio->offset;
269
270 /* If we see a hole, break the region. */
271 if (off_last > off_high) {
272 portio_list_add_1(piolist, pio_start, count, start, off_low,
273 off_high);
274 /* ... and start collecting anew. */
275 pio_start = pio;
276 off_low = off_last;
4080a13c 277 off_high = off_low + pio->len + pio_start->size - 1;
6bf9fd43
AK
278 count = 0;
279 } else if (off_last + pio->len > off_high) {
4080a13c 280 off_high = off_last + pio->len + pio_start->size - 1;
6bf9fd43
AK
281 }
282 }
283
284 /* There will always be an open sub-list. */
285 portio_list_add_1(piolist, pio_start, count, start, off_low, off_high);
286}
287
288void portio_list_del(PortioList *piolist)
289{
b40acf99 290 MemoryRegionPortioList *mrpio;
6bf9fd43
AK
291 unsigned i;
292
293 for (i = 0; i < piolist->nr; ++i) {
b40acf99
JK
294 mrpio = container_of(piolist->regions[i], MemoryRegionPortioList, mr);
295 memory_region_del_subregion(piolist->address_space, &mrpio->mr);
6bf9fd43
AK
296 }
297}