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swiotlb: Refactor swiotlb init functions
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CommitLineData
457c8996 1// SPDX-License-Identifier: GPL-2.0-only
1da177e4
LT
2/*
3 * Dynamic DMA mapping support.
4 *
563aaf06 5 * This implementation is a fallback for platforms that do not support
1da177e4
LT
6 * I/O TLBs (aka DMA address translation hardware).
7 * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com>
8 * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com>
9 * Copyright (C) 2000, 2003 Hewlett-Packard Co
10 * David Mosberger-Tang <davidm@hpl.hp.com>
11 *
12 * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API.
13 * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid
14 * unnecessary i-cache flushing.
569c8bf5
JL
15 * 04/07/.. ak Better overflow handling. Assorted fixes.
16 * 05/09/10 linville Add support for syncing ranges, support syncing for
17 * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup.
fb05a379 18 * 08/12/11 beckyb Add highmem support
1da177e4
LT
19 */
20
7d63fb3a
KC
21#define pr_fmt(fmt) "software IO TLB: " fmt
22
1da177e4 23#include <linux/cache.h>
ea8c64ac 24#include <linux/dma-direct.h>
9f4df96b 25#include <linux/dma-map-ops.h>
1da177e4 26#include <linux/mm.h>
8bc3bcc9 27#include <linux/export.h>
1da177e4
LT
28#include <linux/spinlock.h>
29#include <linux/string.h>
0016fdee 30#include <linux/swiotlb.h>
fb05a379 31#include <linux/pfn.h>
1da177e4
LT
32#include <linux/types.h>
33#include <linux/ctype.h>
ef9b1893 34#include <linux/highmem.h>
5a0e3ad6 35#include <linux/gfp.h>
84be456f 36#include <linux/scatterlist.h>
c7753208 37#include <linux/mem_encrypt.h>
e7de6c7c 38#include <linux/set_memory.h>
71602fe6
DZ
39#ifdef CONFIG_DEBUG_FS
40#include <linux/debugfs.h>
41#endif
1da177e4
LT
42
43#include <asm/io.h>
1da177e4
LT
44#include <asm/dma.h>
45
46#include <linux/init.h>
57c8a661 47#include <linux/memblock.h>
a8522509 48#include <linux/iommu-helper.h>
1da177e4 49
ce5be5a1 50#define CREATE_TRACE_POINTS
2b2b614d
ZK
51#include <trace/events/swiotlb.h>
52
0b9afede
AW
53#define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT))
54
55/*
56 * Minimum IO TLB size to bother booting with. Systems with mainly
57 * 64bit capable cards will only lightly use the swiotlb. If we can't
58 * allocate a contiguous 1MB, we're probably in trouble anyway.
59 */
60#define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT)
61
73f62095 62#define INVALID_PHYS_ADDR (~(phys_addr_t)0)
1da177e4 63
73f62095 64enum swiotlb_force swiotlb_force;
71602fe6 65
2d29960a 66struct io_tlb_mem *io_tlb_default_mem;
1da177e4 67
7453c549
KRW
68/*
69 * Max segment that we can provide which (if pages are contingous) will
70 * not be bounced (unless SWIOTLB_FORCE is set).
71 */
b51e6271 72static unsigned int max_segment;
7453c549 73
2d29960a
CH
74static unsigned long default_nslabs = IO_TLB_DEFAULT_SIZE >> IO_TLB_SHIFT;
75
1da177e4
LT
76static int __init
77setup_io_tlb_npages(char *str)
78{
79 if (isdigit(*str)) {
1da177e4 80 /* avoid tail segment of size < IO_TLB_SEGSIZE */
2d29960a
CH
81 default_nslabs =
82 ALIGN(simple_strtoul(str, &str, 0), IO_TLB_SEGSIZE);
1da177e4
LT
83 }
84 if (*str == ',')
85 ++str;
2726bf3f 86 if (!strcmp(str, "force"))
ae7871be 87 swiotlb_force = SWIOTLB_FORCE;
2726bf3f 88 else if (!strcmp(str, "noforce"))
fff5d992 89 swiotlb_force = SWIOTLB_NO_FORCE;
b18485e7 90
c729de8f 91 return 0;
1da177e4 92}
c729de8f 93early_param("swiotlb", setup_io_tlb_npages);
1da177e4 94
7453c549
KRW
95unsigned int swiotlb_max_segment(void)
96{
2d29960a 97 return io_tlb_default_mem ? max_segment : 0;
7453c549
KRW
98}
99EXPORT_SYMBOL_GPL(swiotlb_max_segment);
100
101void swiotlb_set_max_segment(unsigned int val)
102{
103 if (swiotlb_force == SWIOTLB_FORCE)
104 max_segment = 1;
105 else
106 max_segment = rounddown(val, PAGE_SIZE);
107}
108
c729de8f
YL
109unsigned long swiotlb_size_or_default(void)
110{
2d29960a 111 return default_nslabs << IO_TLB_SHIFT;
c729de8f
YL
112}
113
2d29960a 114void __init swiotlb_adjust_size(unsigned long size)
e998879d 115{
e998879d
AK
116 /*
117 * If swiotlb parameter has not been specified, give a chance to
118 * architectures such as those supporting memory encryption to
119 * adjust/expand SWIOTLB size for their use.
120 */
dfc06b38
CH
121 if (default_nslabs != IO_TLB_DEFAULT_SIZE >> IO_TLB_SHIFT)
122 return;
2d29960a
CH
123 size = ALIGN(size, IO_TLB_SIZE);
124 default_nslabs = ALIGN(size >> IO_TLB_SHIFT, IO_TLB_SEGSIZE);
125 pr_info("SWIOTLB bounce buffer size adjusted to %luMB", size >> 20);
e998879d
AK
126}
127
ad32e8cb 128void swiotlb_print_info(void)
2e5b2b86 129{
2d29960a 130 struct io_tlb_mem *mem = io_tlb_default_mem;
2e5b2b86 131
2d29960a 132 if (!mem) {
7d63fb3a 133 pr_warn("No low mem\n");
ac2cbab2
YL
134 return;
135 }
136
73f62095 137 pr_info("mapped [mem %pa-%pa] (%luMB)\n", &mem->start, &mem->end,
2d29960a 138 (mem->nslabs << IO_TLB_SHIFT) >> 20);
2e5b2b86
IC
139}
140
c7fbeca7
CH
141static inline unsigned long io_tlb_offset(unsigned long val)
142{
143 return val & (IO_TLB_SEGSIZE - 1);
144}
145
c32a77fd
CH
146static inline unsigned long nr_slots(u64 val)
147{
148 return DIV_ROUND_UP(val, IO_TLB_SIZE);
149}
150
c7753208
TL
151/*
152 * Early SWIOTLB allocation may be too early to allow an architecture to
153 * perform the desired operations. This function allows the architecture to
154 * call SWIOTLB when the operations are possible. It needs to be called
155 * before the SWIOTLB memory is used.
156 */
157void __init swiotlb_update_mem_attributes(void)
158{
2d29960a 159 struct io_tlb_mem *mem = io_tlb_default_mem;
c7753208
TL
160 void *vaddr;
161 unsigned long bytes;
162
2d29960a 163 if (!mem || mem->late_alloc)
c7753208 164 return;
73f62095
CC
165 vaddr = phys_to_virt(mem->start);
166 bytes = PAGE_ALIGN(mem->nslabs << IO_TLB_SHIFT);
e7de6c7c 167 set_memory_decrypted((unsigned long)vaddr, bytes >> PAGE_SHIFT);
c7753208 168 memset(vaddr, 0, bytes);
c7753208
TL
169}
170
0a65579c
CC
171static void swiotlb_init_io_tlb_mem(struct io_tlb_mem *mem, phys_addr_t start,
172 unsigned long nslabs, bool late_alloc)
1da177e4 173{
0a65579c 174 void *vaddr = phys_to_virt(start);
2d29960a 175 unsigned long bytes = nslabs << IO_TLB_SHIFT, i;
0a65579c
CC
176
177 mem->nslabs = nslabs;
178 mem->start = start;
179 mem->end = mem->start + bytes;
180 mem->index = 0;
181 mem->late_alloc = late_alloc;
182 spin_lock_init(&mem->lock);
183 for (i = 0; i < mem->nslabs; i++) {
184 mem->slots[i].list = IO_TLB_SEGSIZE - io_tlb_offset(i);
185 mem->slots[i].orig_addr = INVALID_PHYS_ADDR;
186 mem->slots[i].alloc_size = 0;
187 }
188 memset(vaddr, 0, bytes);
189}
190
191int __init swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose)
192{
2d29960a 193 struct io_tlb_mem *mem;
a0bf842e 194 size_t alloc_size;
1da177e4 195
2726bf3f
FF
196 if (swiotlb_force == SWIOTLB_NO_FORCE)
197 return 0;
198
5d0538b2 199 /* protect against double initialization */
2d29960a 200 if (WARN_ON_ONCE(io_tlb_default_mem))
5d0538b2
CH
201 return -ENOMEM;
202
2d29960a
CH
203 alloc_size = PAGE_ALIGN(struct_size(mem, slots, nslabs));
204 mem = memblock_alloc(alloc_size, PAGE_SIZE);
205 if (!mem)
206 panic("%s: Failed to allocate %zu bytes align=0x%lx\n",
207 __func__, alloc_size, PAGE_SIZE);
0a65579c
CC
208
209 swiotlb_init_io_tlb_mem(mem, __pa(tlb), nslabs, false);
1da177e4 210
2d29960a 211 io_tlb_default_mem = mem;
ad32e8cb
FT
212 if (verbose)
213 swiotlb_print_info();
73f62095 214 swiotlb_set_max_segment(mem->nslabs << IO_TLB_SHIFT);
ac2cbab2 215 return 0;
1da177e4
LT
216}
217
abbceff7
FT
218/*
219 * Statically reserve bounce buffer space and initialize bounce buffer data
220 * structures for the software IO TLB used to implement the DMA API.
221 */
ac2cbab2
YL
222void __init
223swiotlb_init(int verbose)
abbceff7 224{
2d29960a
CH
225 size_t bytes = PAGE_ALIGN(default_nslabs << IO_TLB_SHIFT);
226 void *tlb;
abbceff7 227
2726bf3f
FF
228 if (swiotlb_force == SWIOTLB_NO_FORCE)
229 return;
230
ac2cbab2 231 /* Get IO TLB memory from the low pages */
2d29960a
CH
232 tlb = memblock_alloc_low(bytes, PAGE_SIZE);
233 if (!tlb)
234 goto fail;
235 if (swiotlb_init_with_tbl(tlb, default_nslabs, verbose))
236 goto fail_free_mem;
237 return;
238
239fail_free_mem:
240 memblock_free_early(__pa(tlb), bytes);
241fail:
7d63fb3a 242 pr_warn("Cannot allocate buffer");
1da177e4
LT
243}
244
0b9afede
AW
245/*
246 * Systems with larger DMA zones (those that don't support ISA) can
247 * initialize the swiotlb later using the slab allocator if needed.
248 * This should be just like above, but with some error catching.
249 */
250int
563aaf06 251swiotlb_late_init_with_default_size(size_t default_size)
0b9afede 252{
2d29960a
CH
253 unsigned long nslabs =
254 ALIGN(default_size >> IO_TLB_SHIFT, IO_TLB_SEGSIZE);
255 unsigned long bytes;
ff7204a7 256 unsigned char *vstart = NULL;
0b9afede 257 unsigned int order;
74838b75 258 int rc = 0;
0b9afede 259
2726bf3f
FF
260 if (swiotlb_force == SWIOTLB_NO_FORCE)
261 return 0;
262
0b9afede
AW
263 /*
264 * Get IO TLB memory from the low pages
265 */
2d29960a
CH
266 order = get_order(nslabs << IO_TLB_SHIFT);
267 nslabs = SLABS_PER_PAGE << order;
268 bytes = nslabs << IO_TLB_SHIFT;
0b9afede
AW
269
270 while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) {
ff7204a7
AD
271 vstart = (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN,
272 order);
273 if (vstart)
0b9afede
AW
274 break;
275 order--;
276 }
277
2d29960a 278 if (!vstart)
74838b75 279 return -ENOMEM;
2d29960a 280
563aaf06 281 if (order != get_order(bytes)) {
7d63fb3a
KC
282 pr_warn("only able to allocate %ld MB\n",
283 (PAGE_SIZE << order) >> 20);
2d29960a 284 nslabs = SLABS_PER_PAGE << order;
0b9afede 285 }
2d29960a 286 rc = swiotlb_late_init_with_tbl(vstart, nslabs);
74838b75 287 if (rc)
ff7204a7 288 free_pages((unsigned long)vstart, order);
7453c549 289
74838b75
KRW
290 return rc;
291}
292
293int
294swiotlb_late_init_with_tbl(char *tlb, unsigned long nslabs)
295{
2d29960a 296 struct io_tlb_mem *mem;
0a65579c 297 unsigned long bytes = nslabs << IO_TLB_SHIFT;
2726bf3f
FF
298
299 if (swiotlb_force == SWIOTLB_NO_FORCE)
300 return 0;
74838b75 301
5d0538b2 302 /* protect against double initialization */
2d29960a 303 if (WARN_ON_ONCE(io_tlb_default_mem))
5d0538b2
CH
304 return -ENOMEM;
305
2d29960a
CH
306 mem = (void *)__get_free_pages(GFP_KERNEL,
307 get_order(struct_size(mem, slots, nslabs)));
308 if (!mem)
309 return -ENOMEM;
74838b75 310
0a65579c 311 memset(mem, 0, sizeof(*mem));
e7de6c7c 312 set_memory_decrypted((unsigned long)tlb, bytes >> PAGE_SHIFT);
0a65579c 313 swiotlb_init_io_tlb_mem(mem, virt_to_phys(tlb), nslabs, true);
0b9afede 314
2d29960a 315 io_tlb_default_mem = mem;
ad32e8cb 316 swiotlb_print_info();
73f62095 317 swiotlb_set_max_segment(mem->nslabs << IO_TLB_SHIFT);
0b9afede 318 return 0;
0b9afede
AW
319}
320
7f2c8bbd 321void __init swiotlb_exit(void)
5740afdb 322{
2d29960a
CH
323 struct io_tlb_mem *mem = io_tlb_default_mem;
324 size_t size;
73f62095 325
2d29960a 326 if (!mem)
5740afdb
FT
327 return;
328
2d29960a
CH
329 size = struct_size(mem, slots, mem->nslabs);
330 if (mem->late_alloc)
331 free_pages((unsigned long)mem, get_order(size));
332 else
333 memblock_free_late(__pa(mem), PAGE_ALIGN(size));
334 io_tlb_default_mem = NULL;
5740afdb
FT
335}
336
5f89468e
BL
337/*
338 * Return the offset into a iotlb slot required to keep the device happy.
339 */
340static unsigned int swiotlb_align_offset(struct device *dev, u64 addr)
341{
342 return addr & dma_get_min_align_mask(dev) & (IO_TLB_SIZE - 1);
343}
344
fb05a379 345/*
6442ca2a 346 * Bounce: copy the swiotlb buffer from or back to the original dma location
fb05a379 347 */
2bdba622
CH
348static void swiotlb_bounce(struct device *dev, phys_addr_t tlb_addr, size_t size,
349 enum dma_data_direction dir)
fb05a379 350{
2d29960a 351 struct io_tlb_mem *mem = io_tlb_default_mem;
73f62095 352 int index = (tlb_addr - mem->start) >> IO_TLB_SHIFT;
2d29960a
CH
353 phys_addr_t orig_addr = mem->slots[index].orig_addr;
354 size_t alloc_size = mem->slots[index].alloc_size;
af51a9f1
AD
355 unsigned long pfn = PFN_DOWN(orig_addr);
356 unsigned char *vaddr = phys_to_virt(tlb_addr);
5f89468e 357 unsigned int tlb_offset;
fb05a379 358
2bdba622
CH
359 if (orig_addr == INVALID_PHYS_ADDR)
360 return;
361
5f89468e
BL
362 tlb_offset = (tlb_addr & (IO_TLB_SIZE - 1)) -
363 swiotlb_align_offset(dev, orig_addr);
364
365 orig_addr += tlb_offset;
366 alloc_size -= tlb_offset;
367
2bdba622
CH
368 if (size > alloc_size) {
369 dev_WARN_ONCE(dev, 1,
370 "Buffer overflow detected. Allocation size: %zu. Mapping size: %zu.\n",
371 alloc_size, size);
372 size = alloc_size;
373 }
374
fb05a379
BB
375 if (PageHighMem(pfn_to_page(pfn))) {
376 /* The buffer does not have a mapping. Map it in and copy */
af51a9f1 377 unsigned int offset = orig_addr & ~PAGE_MASK;
fb05a379
BB
378 char *buffer;
379 unsigned int sz = 0;
380 unsigned long flags;
381
382 while (size) {
67131ad0 383 sz = min_t(size_t, PAGE_SIZE - offset, size);
fb05a379
BB
384
385 local_irq_save(flags);
c3eede8e 386 buffer = kmap_atomic(pfn_to_page(pfn));
fb05a379 387 if (dir == DMA_TO_DEVICE)
af51a9f1 388 memcpy(vaddr, buffer + offset, sz);
ef9b1893 389 else
af51a9f1 390 memcpy(buffer + offset, vaddr, sz);
c3eede8e 391 kunmap_atomic(buffer);
ef9b1893 392 local_irq_restore(flags);
fb05a379
BB
393
394 size -= sz;
395 pfn++;
af51a9f1 396 vaddr += sz;
fb05a379 397 offset = 0;
ef9b1893 398 }
af51a9f1
AD
399 } else if (dir == DMA_TO_DEVICE) {
400 memcpy(vaddr, phys_to_virt(orig_addr), size);
ef9b1893 401 } else {
af51a9f1 402 memcpy(phys_to_virt(orig_addr), vaddr, size);
ef9b1893 403 }
1b548f66
JF
404}
405
26a7e094 406#define slot_addr(start, idx) ((start) + ((idx) << IO_TLB_SHIFT))
648babb7 407
26a7e094
CH
408/*
409 * Carefully handle integer overflow which can occur when boundary_mask == ~0UL.
410 */
411static inline unsigned long get_max_slots(unsigned long boundary_mask)
412{
413 if (boundary_mask == ~0UL)
414 return 1UL << (BITS_PER_LONG - IO_TLB_SHIFT);
415 return nr_slots(boundary_mask + 1);
416}
681cc5cd 417
73f62095 418static unsigned int wrap_index(struct io_tlb_mem *mem, unsigned int index)
26a7e094 419{
73f62095 420 if (index >= mem->nslabs)
26a7e094
CH
421 return 0;
422 return index;
423}
eb605a57 424
26a7e094
CH
425/*
426 * Find a suitable number of IO TLB entries size that will fit this request and
427 * allocate a buffer from that IO TLB pool.
428 */
1f221a0d
CH
429static int find_slots(struct device *dev, phys_addr_t orig_addr,
430 size_t alloc_size)
26a7e094 431{
2d29960a 432 struct io_tlb_mem *mem = io_tlb_default_mem;
26a7e094
CH
433 unsigned long boundary_mask = dma_get_seg_boundary(dev);
434 dma_addr_t tbl_dma_addr =
73f62095 435 phys_to_dma_unencrypted(dev, mem->start) & boundary_mask;
26a7e094 436 unsigned long max_slots = get_max_slots(boundary_mask);
1f221a0d
CH
437 unsigned int iotlb_align_mask =
438 dma_get_min_align_mask(dev) & ~(IO_TLB_SIZE - 1);
439 unsigned int nslots = nr_slots(alloc_size), stride;
26a7e094
CH
440 unsigned int index, wrap, count = 0, i;
441 unsigned long flags;
a5ddde4a 442
26a7e094 443 BUG_ON(!nslots);
1da177e4
LT
444
445 /*
1f221a0d
CH
446 * For mappings with an alignment requirement don't bother looping to
447 * unaligned slots once we found an aligned one. For allocations of
448 * PAGE_SIZE or larger only look for page aligned allocations.
1da177e4 449 */
1f221a0d 450 stride = (iotlb_align_mask >> IO_TLB_SHIFT) + 1;
3fc1ca00 451 if (alloc_size >= PAGE_SIZE)
1f221a0d 452 stride = max(stride, stride << (PAGE_SHIFT - IO_TLB_SHIFT));
1da177e4 453
73f62095
CC
454 spin_lock_irqsave(&mem->lock, flags);
455 if (unlikely(nslots > mem->nslabs - mem->used))
60513ed0
DZ
456 goto not_found;
457
73f62095 458 index = wrap = wrap_index(mem, ALIGN(mem->index, stride));
a7133a15 459 do {
1f221a0d
CH
460 if ((slot_addr(tbl_dma_addr, index) & iotlb_align_mask) !=
461 (orig_addr & iotlb_align_mask)) {
73f62095 462 index = wrap_index(mem, index + 1);
1f221a0d
CH
463 continue;
464 }
465
a7133a15
AM
466 /*
467 * If we find a slot that indicates we have 'nslots' number of
468 * contiguous buffers, we allocate the buffers from that slot
469 * and mark the entries as '0' indicating unavailable.
470 */
26a7e094
CH
471 if (!iommu_is_span_boundary(index, nslots,
472 nr_slots(tbl_dma_addr),
473 max_slots)) {
2d29960a 474 if (mem->slots[index].list >= nslots)
26a7e094 475 goto found;
a7133a15 476 }
73f62095 477 index = wrap_index(mem, index + stride);
a7133a15
AM
478 } while (index != wrap);
479
480not_found:
73f62095 481 spin_unlock_irqrestore(&mem->lock, flags);
26a7e094
CH
482 return -1;
483
a7133a15 484found:
26a7e094 485 for (i = index; i < index + nslots; i++)
2d29960a 486 mem->slots[i].list = 0;
26a7e094
CH
487 for (i = index - 1;
488 io_tlb_offset(i) != IO_TLB_SEGSIZE - 1 &&
2d29960a
CH
489 mem->slots[i].list; i--)
490 mem->slots[i].list = ++count;
26a7e094
CH
491
492 /*
493 * Update the indices to avoid searching in the next round.
494 */
73f62095
CC
495 if (index + nslots < mem->nslabs)
496 mem->index = index + nslots;
26a7e094 497 else
73f62095
CC
498 mem->index = 0;
499 mem->used += nslots;
26a7e094 500
73f62095 501 spin_unlock_irqrestore(&mem->lock, flags);
26a7e094
CH
502 return index;
503}
504
505phys_addr_t swiotlb_tbl_map_single(struct device *dev, phys_addr_t orig_addr,
506 size_t mapping_size, size_t alloc_size,
507 enum dma_data_direction dir, unsigned long attrs)
508{
2d29960a 509 struct io_tlb_mem *mem = io_tlb_default_mem;
1f221a0d 510 unsigned int offset = swiotlb_align_offset(dev, orig_addr);
95b079d8
CC
511 unsigned int i;
512 int index;
26a7e094
CH
513 phys_addr_t tlb_addr;
514
2d29960a 515 if (!mem)
26a7e094
CH
516 panic("Can not allocate SWIOTLB buffer earlier and can't now provide you with the DMA bounce buffer");
517
518 if (mem_encrypt_active())
519 pr_warn_once("Memory encryption is active and system is using DMA bounce buffers\n");
520
521 if (mapping_size > alloc_size) {
522 dev_warn_once(dev, "Invalid sizes (mapping: %zd bytes, alloc: %zd bytes)",
523 mapping_size, alloc_size);
524 return (phys_addr_t)DMA_MAPPING_ERROR;
525 }
526
1f221a0d 527 index = find_slots(dev, orig_addr, alloc_size + offset);
26a7e094
CH
528 if (index == -1) {
529 if (!(attrs & DMA_ATTR_NO_WARN))
530 dev_warn_ratelimited(dev,
531 "swiotlb buffer is full (sz: %zd bytes), total %lu (slots), used %lu (slots)\n",
73f62095 532 alloc_size, mem->nslabs, mem->used);
26a7e094
CH
533 return (phys_addr_t)DMA_MAPPING_ERROR;
534 }
1da177e4
LT
535
536 /*
537 * Save away the mapping from the original address to the DMA address.
538 * This is needed when we sync the memory. Then we sync the buffer if
539 * needed.
540 */
daf9514f 541 for (i = 0; i < nr_slots(alloc_size + offset); i++) {
2d29960a
CH
542 mem->slots[index + i].orig_addr = slot_addr(orig_addr, i);
543 mem->slots[index + i].alloc_size =
544 alloc_size - (i << IO_TLB_SHIFT);
daf9514f 545 }
73f62095 546 tlb_addr = slot_addr(mem->start, index) + offset;
0443fa00
AD
547 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
548 (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL))
2bdba622 549 swiotlb_bounce(dev, tlb_addr, mapping_size, DMA_TO_DEVICE);
e05ed4d1 550 return tlb_addr;
1da177e4
LT
551}
552
553/*
d0c8ba40 554 * tlb_addr is the physical address of the bounce buffer to unmap.
1da177e4 555 */
61ca08c3 556void swiotlb_tbl_unmap_single(struct device *hwdev, phys_addr_t tlb_addr,
2973073a
CH
557 size_t mapping_size, enum dma_data_direction dir,
558 unsigned long attrs)
1da177e4 559{
2d29960a 560 struct io_tlb_mem *mem = io_tlb_default_mem;
1da177e4 561 unsigned long flags;
1f221a0d 562 unsigned int offset = swiotlb_align_offset(hwdev, tlb_addr);
73f62095 563 int index = (tlb_addr - offset - mem->start) >> IO_TLB_SHIFT;
2d29960a 564 int nslots = nr_slots(mem->slots[index].alloc_size + offset);
2bdba622 565 int count, i;
daf9514f 566
1da177e4
LT
567 /*
568 * First, sync the memory before unmapping the entry
569 */
2bdba622
CH
570 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
571 (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL))
572 swiotlb_bounce(hwdev, tlb_addr, mapping_size, DMA_FROM_DEVICE);
1da177e4
LT
573
574 /*
575 * Return the buffer to the free list by setting the corresponding
af901ca1 576 * entries to indicate the number of contiguous entries available.
1da177e4
LT
577 * While returning the entries to the free list, we merge the entries
578 * with slots below and above the pool being returned.
579 */
73f62095 580 spin_lock_irqsave(&mem->lock, flags);
ca10d0f8 581 if (index + nslots < ALIGN(index + 1, IO_TLB_SEGSIZE))
2d29960a 582 count = mem->slots[index + nslots].list;
ca10d0f8
CH
583 else
584 count = 0;
71602fe6 585
ca10d0f8
CH
586 /*
587 * Step 1: return the slots to the free list, merging the slots with
588 * superceeding slots
589 */
590 for (i = index + nslots - 1; i >= index; i--) {
2d29960a
CH
591 mem->slots[i].list = ++count;
592 mem->slots[i].orig_addr = INVALID_PHYS_ADDR;
593 mem->slots[i].alloc_size = 0;
1da177e4 594 }
ca10d0f8
CH
595
596 /*
597 * Step 2: merge the returned slots with the preceding slots, if
598 * available (non zero)
599 */
600 for (i = index - 1;
2d29960a 601 io_tlb_offset(i) != IO_TLB_SEGSIZE - 1 && mem->slots[i].list;
ca10d0f8 602 i--)
2d29960a 603 mem->slots[i].list = ++count;
73f62095
CC
604 mem->used -= nslots;
605 spin_unlock_irqrestore(&mem->lock, flags);
1da177e4
LT
606}
607
80808d27
CH
608void swiotlb_sync_single_for_device(struct device *dev, phys_addr_t tlb_addr,
609 size_t size, enum dma_data_direction dir)
1da177e4 610{
80808d27
CH
611 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)
612 swiotlb_bounce(dev, tlb_addr, size, DMA_TO_DEVICE);
613 else
614 BUG_ON(dir != DMA_FROM_DEVICE);
615}
616
617void swiotlb_sync_single_for_cpu(struct device *dev, phys_addr_t tlb_addr,
618 size_t size, enum dma_data_direction dir)
619{
620 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
621 swiotlb_bounce(dev, tlb_addr, size, DMA_FROM_DEVICE);
622 else
623 BUG_ON(dir != DMA_TO_DEVICE);
1da177e4
LT
624}
625
55897af6 626/*
4a47cbae 627 * Create a swiotlb mapping for the buffer at @paddr, and in case of DMAing
55897af6
CH
628 * to the device copy the data into it as well.
629 */
4a47cbae
CH
630dma_addr_t swiotlb_map(struct device *dev, phys_addr_t paddr, size_t size,
631 enum dma_data_direction dir, unsigned long attrs)
c4dae366 632{
4a47cbae
CH
633 phys_addr_t swiotlb_addr;
634 dma_addr_t dma_addr;
c4dae366 635
4a47cbae
CH
636 trace_swiotlb_bounced(dev, phys_to_dma(dev, paddr), size,
637 swiotlb_force);
c4dae366 638
fc0021aa
CH
639 swiotlb_addr = swiotlb_tbl_map_single(dev, paddr, size, size, dir,
640 attrs);
4a47cbae
CH
641 if (swiotlb_addr == (phys_addr_t)DMA_MAPPING_ERROR)
642 return DMA_MAPPING_ERROR;
c4dae366
CH
643
644 /* Ensure that the address returned is DMA'ble */
5ceda740 645 dma_addr = phys_to_dma_unencrypted(dev, swiotlb_addr);
4a47cbae 646 if (unlikely(!dma_capable(dev, dma_addr, size, true))) {
2973073a 647 swiotlb_tbl_unmap_single(dev, swiotlb_addr, size, dir,
c4dae366 648 attrs | DMA_ATTR_SKIP_CPU_SYNC);
4a47cbae
CH
649 dev_WARN_ONCE(dev, 1,
650 "swiotlb addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
651 &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
652 return DMA_MAPPING_ERROR;
a4a4330d
CH
653 }
654
4a47cbae
CH
655 if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
656 arch_sync_dma_for_device(swiotlb_addr, size, dir);
657 return dma_addr;
1da177e4
LT
658}
659
abe420bf
JR
660size_t swiotlb_max_mapping_size(struct device *dev)
661{
b5d7ccb7 662 return ((size_t)IO_TLB_SIZE) * IO_TLB_SEGSIZE;
abe420bf 663}
492366f7
JR
664
665bool is_swiotlb_active(void)
666{
2d29960a 667 return io_tlb_default_mem != NULL;
492366f7 668}
2cbc2776 669EXPORT_SYMBOL_GPL(is_swiotlb_active);
45ba8d5d 670
71602fe6
DZ
671#ifdef CONFIG_DEBUG_FS
672
673static int __init swiotlb_create_debugfs(void)
674{
2d29960a 675 struct io_tlb_mem *mem = io_tlb_default_mem;
71602fe6 676
2d29960a
CH
677 if (!mem)
678 return 0;
73f62095
CC
679 mem->debugfs = debugfs_create_dir("swiotlb", NULL);
680 debugfs_create_ulong("io_tlb_nslabs", 0400, mem->debugfs, &mem->nslabs);
681 debugfs_create_ulong("io_tlb_used", 0400, mem->debugfs, &mem->used);
71602fe6 682 return 0;
71602fe6
DZ
683}
684
685late_initcall(swiotlb_create_debugfs);
686
687#endif