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Commit | Line | Data |
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457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 LT |
2 | /* |
3 | * Dynamic DMA mapping support. | |
4 | * | |
563aaf06 | 5 | * This implementation is a fallback for platforms that do not support |
1da177e4 LT |
6 | * I/O TLBs (aka DMA address translation hardware). |
7 | * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com> | |
8 | * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com> | |
9 | * Copyright (C) 2000, 2003 Hewlett-Packard Co | |
10 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
11 | * | |
12 | * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API. | |
13 | * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid | |
14 | * unnecessary i-cache flushing. | |
569c8bf5 JL |
15 | * 04/07/.. ak Better overflow handling. Assorted fixes. |
16 | * 05/09/10 linville Add support for syncing ranges, support syncing for | |
17 | * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup. | |
fb05a379 | 18 | * 08/12/11 beckyb Add highmem support |
1da177e4 LT |
19 | */ |
20 | ||
7d63fb3a KC |
21 | #define pr_fmt(fmt) "software IO TLB: " fmt |
22 | ||
1da177e4 | 23 | #include <linux/cache.h> |
ea8c64ac | 24 | #include <linux/dma-direct.h> |
9f4df96b | 25 | #include <linux/dma-map-ops.h> |
1da177e4 | 26 | #include <linux/mm.h> |
8bc3bcc9 | 27 | #include <linux/export.h> |
1da177e4 LT |
28 | #include <linux/spinlock.h> |
29 | #include <linux/string.h> | |
0016fdee | 30 | #include <linux/swiotlb.h> |
fb05a379 | 31 | #include <linux/pfn.h> |
1da177e4 LT |
32 | #include <linux/types.h> |
33 | #include <linux/ctype.h> | |
ef9b1893 | 34 | #include <linux/highmem.h> |
5a0e3ad6 | 35 | #include <linux/gfp.h> |
84be456f | 36 | #include <linux/scatterlist.h> |
c7753208 | 37 | #include <linux/mem_encrypt.h> |
e7de6c7c | 38 | #include <linux/set_memory.h> |
71602fe6 DZ |
39 | #ifdef CONFIG_DEBUG_FS |
40 | #include <linux/debugfs.h> | |
41 | #endif | |
0b84e4f8 CC |
42 | #ifdef CONFIG_DMA_RESTRICTED_POOL |
43 | #include <linux/io.h> | |
44 | #include <linux/of.h> | |
45 | #include <linux/of_fdt.h> | |
46 | #include <linux/of_reserved_mem.h> | |
47 | #include <linux/slab.h> | |
48 | #endif | |
1da177e4 LT |
49 | |
50 | #include <asm/io.h> | |
1da177e4 LT |
51 | #include <asm/dma.h> |
52 | ||
53 | #include <linux/init.h> | |
57c8a661 | 54 | #include <linux/memblock.h> |
a8522509 | 55 | #include <linux/iommu-helper.h> |
1da177e4 | 56 | |
ce5be5a1 | 57 | #define CREATE_TRACE_POINTS |
2b2b614d ZK |
58 | #include <trace/events/swiotlb.h> |
59 | ||
0b9afede AW |
60 | #define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT)) |
61 | ||
62 | /* | |
63 | * Minimum IO TLB size to bother booting with. Systems with mainly | |
64 | * 64bit capable cards will only lightly use the swiotlb. If we can't | |
65 | * allocate a contiguous 1MB, we're probably in trouble anyway. | |
66 | */ | |
67 | #define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT) | |
68 | ||
73f62095 | 69 | #define INVALID_PHYS_ADDR (~(phys_addr_t)0) |
1da177e4 | 70 | |
73f62095 | 71 | enum swiotlb_force swiotlb_force; |
71602fe6 | 72 | |
463e862a | 73 | struct io_tlb_mem io_tlb_default_mem; |
1da177e4 | 74 | |
7453c549 KRW |
75 | /* |
76 | * Max segment that we can provide which (if pages are contingous) will | |
77 | * not be bounced (unless SWIOTLB_FORCE is set). | |
78 | */ | |
b51e6271 | 79 | static unsigned int max_segment; |
7453c549 | 80 | |
2d29960a CH |
81 | static unsigned long default_nslabs = IO_TLB_DEFAULT_SIZE >> IO_TLB_SHIFT; |
82 | ||
1da177e4 LT |
83 | static int __init |
84 | setup_io_tlb_npages(char *str) | |
85 | { | |
86 | if (isdigit(*str)) { | |
1da177e4 | 87 | /* avoid tail segment of size < IO_TLB_SEGSIZE */ |
2d29960a CH |
88 | default_nslabs = |
89 | ALIGN(simple_strtoul(str, &str, 0), IO_TLB_SEGSIZE); | |
1da177e4 LT |
90 | } |
91 | if (*str == ',') | |
92 | ++str; | |
2726bf3f | 93 | if (!strcmp(str, "force")) |
ae7871be | 94 | swiotlb_force = SWIOTLB_FORCE; |
2726bf3f | 95 | else if (!strcmp(str, "noforce")) |
fff5d992 | 96 | swiotlb_force = SWIOTLB_NO_FORCE; |
b18485e7 | 97 | |
c729de8f | 98 | return 0; |
1da177e4 | 99 | } |
c729de8f | 100 | early_param("swiotlb", setup_io_tlb_npages); |
1da177e4 | 101 | |
7453c549 KRW |
102 | unsigned int swiotlb_max_segment(void) |
103 | { | |
463e862a | 104 | return io_tlb_default_mem.nslabs ? max_segment : 0; |
7453c549 KRW |
105 | } |
106 | EXPORT_SYMBOL_GPL(swiotlb_max_segment); | |
107 | ||
108 | void swiotlb_set_max_segment(unsigned int val) | |
109 | { | |
110 | if (swiotlb_force == SWIOTLB_FORCE) | |
111 | max_segment = 1; | |
112 | else | |
113 | max_segment = rounddown(val, PAGE_SIZE); | |
114 | } | |
115 | ||
c729de8f YL |
116 | unsigned long swiotlb_size_or_default(void) |
117 | { | |
2d29960a | 118 | return default_nslabs << IO_TLB_SHIFT; |
c729de8f YL |
119 | } |
120 | ||
2d29960a | 121 | void __init swiotlb_adjust_size(unsigned long size) |
e998879d | 122 | { |
e998879d AK |
123 | /* |
124 | * If swiotlb parameter has not been specified, give a chance to | |
125 | * architectures such as those supporting memory encryption to | |
126 | * adjust/expand SWIOTLB size for their use. | |
127 | */ | |
dfc06b38 CH |
128 | if (default_nslabs != IO_TLB_DEFAULT_SIZE >> IO_TLB_SHIFT) |
129 | return; | |
2d29960a CH |
130 | size = ALIGN(size, IO_TLB_SIZE); |
131 | default_nslabs = ALIGN(size >> IO_TLB_SHIFT, IO_TLB_SEGSIZE); | |
132 | pr_info("SWIOTLB bounce buffer size adjusted to %luMB", size >> 20); | |
e998879d AK |
133 | } |
134 | ||
ad32e8cb | 135 | void swiotlb_print_info(void) |
2e5b2b86 | 136 | { |
463e862a | 137 | struct io_tlb_mem *mem = &io_tlb_default_mem; |
2e5b2b86 | 138 | |
463e862a | 139 | if (!mem->nslabs) { |
7d63fb3a | 140 | pr_warn("No low mem\n"); |
ac2cbab2 YL |
141 | return; |
142 | } | |
143 | ||
73f62095 | 144 | pr_info("mapped [mem %pa-%pa] (%luMB)\n", &mem->start, &mem->end, |
2d29960a | 145 | (mem->nslabs << IO_TLB_SHIFT) >> 20); |
2e5b2b86 IC |
146 | } |
147 | ||
c7fbeca7 CH |
148 | static inline unsigned long io_tlb_offset(unsigned long val) |
149 | { | |
150 | return val & (IO_TLB_SEGSIZE - 1); | |
151 | } | |
152 | ||
c32a77fd CH |
153 | static inline unsigned long nr_slots(u64 val) |
154 | { | |
155 | return DIV_ROUND_UP(val, IO_TLB_SIZE); | |
156 | } | |
157 | ||
c7753208 TL |
158 | /* |
159 | * Early SWIOTLB allocation may be too early to allow an architecture to | |
160 | * perform the desired operations. This function allows the architecture to | |
161 | * call SWIOTLB when the operations are possible. It needs to be called | |
162 | * before the SWIOTLB memory is used. | |
163 | */ | |
164 | void __init swiotlb_update_mem_attributes(void) | |
165 | { | |
463e862a | 166 | struct io_tlb_mem *mem = &io_tlb_default_mem; |
c7753208 TL |
167 | void *vaddr; |
168 | unsigned long bytes; | |
169 | ||
463e862a | 170 | if (!mem->nslabs || mem->late_alloc) |
c7753208 | 171 | return; |
73f62095 CC |
172 | vaddr = phys_to_virt(mem->start); |
173 | bytes = PAGE_ALIGN(mem->nslabs << IO_TLB_SHIFT); | |
e7de6c7c | 174 | set_memory_decrypted((unsigned long)vaddr, bytes >> PAGE_SHIFT); |
c7753208 | 175 | memset(vaddr, 0, bytes); |
c7753208 TL |
176 | } |
177 | ||
0a65579c CC |
178 | static void swiotlb_init_io_tlb_mem(struct io_tlb_mem *mem, phys_addr_t start, |
179 | unsigned long nslabs, bool late_alloc) | |
1da177e4 | 180 | { |
0a65579c | 181 | void *vaddr = phys_to_virt(start); |
2d29960a | 182 | unsigned long bytes = nslabs << IO_TLB_SHIFT, i; |
0a65579c CC |
183 | |
184 | mem->nslabs = nslabs; | |
185 | mem->start = start; | |
186 | mem->end = mem->start + bytes; | |
187 | mem->index = 0; | |
188 | mem->late_alloc = late_alloc; | |
903cd0f3 CC |
189 | |
190 | if (swiotlb_force == SWIOTLB_FORCE) | |
191 | mem->force_bounce = true; | |
192 | ||
0a65579c CC |
193 | spin_lock_init(&mem->lock); |
194 | for (i = 0; i < mem->nslabs; i++) { | |
195 | mem->slots[i].list = IO_TLB_SEGSIZE - io_tlb_offset(i); | |
196 | mem->slots[i].orig_addr = INVALID_PHYS_ADDR; | |
197 | mem->slots[i].alloc_size = 0; | |
198 | } | |
199 | memset(vaddr, 0, bytes); | |
200 | } | |
201 | ||
202 | int __init swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose) | |
203 | { | |
463e862a | 204 | struct io_tlb_mem *mem = &io_tlb_default_mem; |
a0bf842e | 205 | size_t alloc_size; |
1da177e4 | 206 | |
2726bf3f FF |
207 | if (swiotlb_force == SWIOTLB_NO_FORCE) |
208 | return 0; | |
209 | ||
5d0538b2 | 210 | /* protect against double initialization */ |
463e862a | 211 | if (WARN_ON_ONCE(mem->nslabs)) |
5d0538b2 CH |
212 | return -ENOMEM; |
213 | ||
463e862a WD |
214 | alloc_size = PAGE_ALIGN(array_size(sizeof(*mem->slots), nslabs)); |
215 | mem->slots = memblock_alloc(alloc_size, PAGE_SIZE); | |
216 | if (!mem->slots) | |
2d29960a CH |
217 | panic("%s: Failed to allocate %zu bytes align=0x%lx\n", |
218 | __func__, alloc_size, PAGE_SIZE); | |
0a65579c CC |
219 | |
220 | swiotlb_init_io_tlb_mem(mem, __pa(tlb), nslabs, false); | |
1da177e4 | 221 | |
ad32e8cb FT |
222 | if (verbose) |
223 | swiotlb_print_info(); | |
73f62095 | 224 | swiotlb_set_max_segment(mem->nslabs << IO_TLB_SHIFT); |
ac2cbab2 | 225 | return 0; |
1da177e4 LT |
226 | } |
227 | ||
abbceff7 FT |
228 | /* |
229 | * Statically reserve bounce buffer space and initialize bounce buffer data | |
230 | * structures for the software IO TLB used to implement the DMA API. | |
231 | */ | |
ac2cbab2 YL |
232 | void __init |
233 | swiotlb_init(int verbose) | |
abbceff7 | 234 | { |
2d29960a CH |
235 | size_t bytes = PAGE_ALIGN(default_nslabs << IO_TLB_SHIFT); |
236 | void *tlb; | |
abbceff7 | 237 | |
2726bf3f FF |
238 | if (swiotlb_force == SWIOTLB_NO_FORCE) |
239 | return; | |
240 | ||
ac2cbab2 | 241 | /* Get IO TLB memory from the low pages */ |
2d29960a CH |
242 | tlb = memblock_alloc_low(bytes, PAGE_SIZE); |
243 | if (!tlb) | |
244 | goto fail; | |
245 | if (swiotlb_init_with_tbl(tlb, default_nslabs, verbose)) | |
246 | goto fail_free_mem; | |
247 | return; | |
248 | ||
249 | fail_free_mem: | |
250 | memblock_free_early(__pa(tlb), bytes); | |
251 | fail: | |
7d63fb3a | 252 | pr_warn("Cannot allocate buffer"); |
1da177e4 LT |
253 | } |
254 | ||
0b9afede AW |
255 | /* |
256 | * Systems with larger DMA zones (those that don't support ISA) can | |
257 | * initialize the swiotlb later using the slab allocator if needed. | |
258 | * This should be just like above, but with some error catching. | |
259 | */ | |
260 | int | |
563aaf06 | 261 | swiotlb_late_init_with_default_size(size_t default_size) |
0b9afede | 262 | { |
2d29960a CH |
263 | unsigned long nslabs = |
264 | ALIGN(default_size >> IO_TLB_SHIFT, IO_TLB_SEGSIZE); | |
265 | unsigned long bytes; | |
ff7204a7 | 266 | unsigned char *vstart = NULL; |
0b9afede | 267 | unsigned int order; |
74838b75 | 268 | int rc = 0; |
0b9afede | 269 | |
2726bf3f FF |
270 | if (swiotlb_force == SWIOTLB_NO_FORCE) |
271 | return 0; | |
272 | ||
0b9afede AW |
273 | /* |
274 | * Get IO TLB memory from the low pages | |
275 | */ | |
2d29960a CH |
276 | order = get_order(nslabs << IO_TLB_SHIFT); |
277 | nslabs = SLABS_PER_PAGE << order; | |
278 | bytes = nslabs << IO_TLB_SHIFT; | |
0b9afede AW |
279 | |
280 | while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) { | |
ff7204a7 AD |
281 | vstart = (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN, |
282 | order); | |
283 | if (vstart) | |
0b9afede AW |
284 | break; |
285 | order--; | |
286 | } | |
287 | ||
2d29960a | 288 | if (!vstart) |
74838b75 | 289 | return -ENOMEM; |
2d29960a | 290 | |
563aaf06 | 291 | if (order != get_order(bytes)) { |
7d63fb3a KC |
292 | pr_warn("only able to allocate %ld MB\n", |
293 | (PAGE_SIZE << order) >> 20); | |
2d29960a | 294 | nslabs = SLABS_PER_PAGE << order; |
0b9afede | 295 | } |
2d29960a | 296 | rc = swiotlb_late_init_with_tbl(vstart, nslabs); |
74838b75 | 297 | if (rc) |
ff7204a7 | 298 | free_pages((unsigned long)vstart, order); |
7453c549 | 299 | |
74838b75 KRW |
300 | return rc; |
301 | } | |
302 | ||
303 | int | |
304 | swiotlb_late_init_with_tbl(char *tlb, unsigned long nslabs) | |
305 | { | |
463e862a | 306 | struct io_tlb_mem *mem = &io_tlb_default_mem; |
0a65579c | 307 | unsigned long bytes = nslabs << IO_TLB_SHIFT; |
2726bf3f FF |
308 | |
309 | if (swiotlb_force == SWIOTLB_NO_FORCE) | |
310 | return 0; | |
74838b75 | 311 | |
5d0538b2 | 312 | /* protect against double initialization */ |
463e862a | 313 | if (WARN_ON_ONCE(mem->nslabs)) |
5d0538b2 CH |
314 | return -ENOMEM; |
315 | ||
463e862a WD |
316 | mem->slots = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
317 | get_order(array_size(sizeof(*mem->slots), nslabs))); | |
318 | if (!mem->slots) | |
2d29960a | 319 | return -ENOMEM; |
74838b75 | 320 | |
e7de6c7c | 321 | set_memory_decrypted((unsigned long)tlb, bytes >> PAGE_SHIFT); |
0a65579c | 322 | swiotlb_init_io_tlb_mem(mem, virt_to_phys(tlb), nslabs, true); |
0b9afede | 323 | |
ad32e8cb | 324 | swiotlb_print_info(); |
73f62095 | 325 | swiotlb_set_max_segment(mem->nslabs << IO_TLB_SHIFT); |
0b9afede | 326 | return 0; |
0b9afede AW |
327 | } |
328 | ||
7f2c8bbd | 329 | void __init swiotlb_exit(void) |
5740afdb | 330 | { |
463e862a | 331 | struct io_tlb_mem *mem = &io_tlb_default_mem; |
ad6c0028 WD |
332 | unsigned long tbl_vaddr; |
333 | size_t tbl_size, slots_size; | |
73f62095 | 334 | |
463e862a | 335 | if (!mem->nslabs) |
5740afdb FT |
336 | return; |
337 | ||
1efd3fc0 | 338 | pr_info("tearing down default memory pool\n"); |
ad6c0028 WD |
339 | tbl_vaddr = (unsigned long)phys_to_virt(mem->start); |
340 | tbl_size = PAGE_ALIGN(mem->end - mem->start); | |
341 | slots_size = PAGE_ALIGN(array_size(sizeof(*mem->slots), mem->nslabs)); | |
342 | ||
343 | set_memory_encrypted(tbl_vaddr, tbl_size >> PAGE_SHIFT); | |
344 | if (mem->late_alloc) { | |
345 | free_pages(tbl_vaddr, get_order(tbl_size)); | |
346 | free_pages((unsigned long)mem->slots, get_order(slots_size)); | |
347 | } else { | |
348 | memblock_free_late(mem->start, tbl_size); | |
349 | memblock_free_late(__pa(mem->slots), slots_size); | |
350 | } | |
351 | ||
463e862a | 352 | memset(mem, 0, sizeof(*mem)); |
5740afdb FT |
353 | } |
354 | ||
5f89468e BL |
355 | /* |
356 | * Return the offset into a iotlb slot required to keep the device happy. | |
357 | */ | |
358 | static unsigned int swiotlb_align_offset(struct device *dev, u64 addr) | |
359 | { | |
360 | return addr & dma_get_min_align_mask(dev) & (IO_TLB_SIZE - 1); | |
361 | } | |
362 | ||
fb05a379 | 363 | /* |
6442ca2a | 364 | * Bounce: copy the swiotlb buffer from or back to the original dma location |
fb05a379 | 365 | */ |
2bdba622 CH |
366 | static void swiotlb_bounce(struct device *dev, phys_addr_t tlb_addr, size_t size, |
367 | enum dma_data_direction dir) | |
fb05a379 | 368 | { |
69031f50 | 369 | struct io_tlb_mem *mem = dev->dma_io_tlb_mem; |
73f62095 | 370 | int index = (tlb_addr - mem->start) >> IO_TLB_SHIFT; |
2d29960a CH |
371 | phys_addr_t orig_addr = mem->slots[index].orig_addr; |
372 | size_t alloc_size = mem->slots[index].alloc_size; | |
af51a9f1 AD |
373 | unsigned long pfn = PFN_DOWN(orig_addr); |
374 | unsigned char *vaddr = phys_to_virt(tlb_addr); | |
868c9ddc | 375 | unsigned int tlb_offset, orig_addr_offset; |
fb05a379 | 376 | |
2bdba622 CH |
377 | if (orig_addr == INVALID_PHYS_ADDR) |
378 | return; | |
379 | ||
868c9ddc DM |
380 | tlb_offset = tlb_addr & (IO_TLB_SIZE - 1); |
381 | orig_addr_offset = swiotlb_align_offset(dev, orig_addr); | |
382 | if (tlb_offset < orig_addr_offset) { | |
383 | dev_WARN_ONCE(dev, 1, | |
384 | "Access before mapping start detected. orig offset %u, requested offset %u.\n", | |
385 | orig_addr_offset, tlb_offset); | |
386 | return; | |
387 | } | |
388 | ||
389 | tlb_offset -= orig_addr_offset; | |
390 | if (tlb_offset > alloc_size) { | |
391 | dev_WARN_ONCE(dev, 1, | |
392 | "Buffer overflow detected. Allocation size: %zu. Mapping size: %zu+%u.\n", | |
393 | alloc_size, size, tlb_offset); | |
394 | return; | |
395 | } | |
5f89468e BL |
396 | |
397 | orig_addr += tlb_offset; | |
398 | alloc_size -= tlb_offset; | |
399 | ||
2bdba622 CH |
400 | if (size > alloc_size) { |
401 | dev_WARN_ONCE(dev, 1, | |
402 | "Buffer overflow detected. Allocation size: %zu. Mapping size: %zu.\n", | |
403 | alloc_size, size); | |
404 | size = alloc_size; | |
405 | } | |
406 | ||
fb05a379 BB |
407 | if (PageHighMem(pfn_to_page(pfn))) { |
408 | /* The buffer does not have a mapping. Map it in and copy */ | |
af51a9f1 | 409 | unsigned int offset = orig_addr & ~PAGE_MASK; |
fb05a379 BB |
410 | char *buffer; |
411 | unsigned int sz = 0; | |
412 | unsigned long flags; | |
413 | ||
414 | while (size) { | |
67131ad0 | 415 | sz = min_t(size_t, PAGE_SIZE - offset, size); |
fb05a379 BB |
416 | |
417 | local_irq_save(flags); | |
c3eede8e | 418 | buffer = kmap_atomic(pfn_to_page(pfn)); |
fb05a379 | 419 | if (dir == DMA_TO_DEVICE) |
af51a9f1 | 420 | memcpy(vaddr, buffer + offset, sz); |
ef9b1893 | 421 | else |
af51a9f1 | 422 | memcpy(buffer + offset, vaddr, sz); |
c3eede8e | 423 | kunmap_atomic(buffer); |
ef9b1893 | 424 | local_irq_restore(flags); |
fb05a379 BB |
425 | |
426 | size -= sz; | |
427 | pfn++; | |
af51a9f1 | 428 | vaddr += sz; |
fb05a379 | 429 | offset = 0; |
ef9b1893 | 430 | } |
af51a9f1 AD |
431 | } else if (dir == DMA_TO_DEVICE) { |
432 | memcpy(vaddr, phys_to_virt(orig_addr), size); | |
ef9b1893 | 433 | } else { |
af51a9f1 | 434 | memcpy(phys_to_virt(orig_addr), vaddr, size); |
ef9b1893 | 435 | } |
1b548f66 JF |
436 | } |
437 | ||
26a7e094 | 438 | #define slot_addr(start, idx) ((start) + ((idx) << IO_TLB_SHIFT)) |
648babb7 | 439 | |
26a7e094 CH |
440 | /* |
441 | * Carefully handle integer overflow which can occur when boundary_mask == ~0UL. | |
442 | */ | |
443 | static inline unsigned long get_max_slots(unsigned long boundary_mask) | |
444 | { | |
445 | if (boundary_mask == ~0UL) | |
446 | return 1UL << (BITS_PER_LONG - IO_TLB_SHIFT); | |
447 | return nr_slots(boundary_mask + 1); | |
448 | } | |
681cc5cd | 449 | |
73f62095 | 450 | static unsigned int wrap_index(struct io_tlb_mem *mem, unsigned int index) |
26a7e094 | 451 | { |
73f62095 | 452 | if (index >= mem->nslabs) |
26a7e094 CH |
453 | return 0; |
454 | return index; | |
455 | } | |
eb605a57 | 456 | |
26a7e094 CH |
457 | /* |
458 | * Find a suitable number of IO TLB entries size that will fit this request and | |
459 | * allocate a buffer from that IO TLB pool. | |
460 | */ | |
36f7b2f3 CC |
461 | static int swiotlb_find_slots(struct device *dev, phys_addr_t orig_addr, |
462 | size_t alloc_size) | |
26a7e094 | 463 | { |
69031f50 | 464 | struct io_tlb_mem *mem = dev->dma_io_tlb_mem; |
26a7e094 CH |
465 | unsigned long boundary_mask = dma_get_seg_boundary(dev); |
466 | dma_addr_t tbl_dma_addr = | |
73f62095 | 467 | phys_to_dma_unencrypted(dev, mem->start) & boundary_mask; |
26a7e094 | 468 | unsigned long max_slots = get_max_slots(boundary_mask); |
1f221a0d CH |
469 | unsigned int iotlb_align_mask = |
470 | dma_get_min_align_mask(dev) & ~(IO_TLB_SIZE - 1); | |
471 | unsigned int nslots = nr_slots(alloc_size), stride; | |
26a7e094 | 472 | unsigned int index, wrap, count = 0, i; |
36f7b2f3 | 473 | unsigned int offset = swiotlb_align_offset(dev, orig_addr); |
26a7e094 | 474 | unsigned long flags; |
a5ddde4a | 475 | |
26a7e094 | 476 | BUG_ON(!nslots); |
1da177e4 LT |
477 | |
478 | /* | |
1f221a0d CH |
479 | * For mappings with an alignment requirement don't bother looping to |
480 | * unaligned slots once we found an aligned one. For allocations of | |
481 | * PAGE_SIZE or larger only look for page aligned allocations. | |
1da177e4 | 482 | */ |
1f221a0d | 483 | stride = (iotlb_align_mask >> IO_TLB_SHIFT) + 1; |
3fc1ca00 | 484 | if (alloc_size >= PAGE_SIZE) |
1f221a0d | 485 | stride = max(stride, stride << (PAGE_SHIFT - IO_TLB_SHIFT)); |
1da177e4 | 486 | |
73f62095 CC |
487 | spin_lock_irqsave(&mem->lock, flags); |
488 | if (unlikely(nslots > mem->nslabs - mem->used)) | |
60513ed0 DZ |
489 | goto not_found; |
490 | ||
73f62095 | 491 | index = wrap = wrap_index(mem, ALIGN(mem->index, stride)); |
a7133a15 | 492 | do { |
f4111e39 CC |
493 | if (orig_addr && |
494 | (slot_addr(tbl_dma_addr, index) & iotlb_align_mask) != | |
495 | (orig_addr & iotlb_align_mask)) { | |
73f62095 | 496 | index = wrap_index(mem, index + 1); |
1f221a0d CH |
497 | continue; |
498 | } | |
499 | ||
a7133a15 AM |
500 | /* |
501 | * If we find a slot that indicates we have 'nslots' number of | |
502 | * contiguous buffers, we allocate the buffers from that slot | |
503 | * and mark the entries as '0' indicating unavailable. | |
504 | */ | |
26a7e094 CH |
505 | if (!iommu_is_span_boundary(index, nslots, |
506 | nr_slots(tbl_dma_addr), | |
507 | max_slots)) { | |
2d29960a | 508 | if (mem->slots[index].list >= nslots) |
26a7e094 | 509 | goto found; |
a7133a15 | 510 | } |
73f62095 | 511 | index = wrap_index(mem, index + stride); |
a7133a15 AM |
512 | } while (index != wrap); |
513 | ||
514 | not_found: | |
73f62095 | 515 | spin_unlock_irqrestore(&mem->lock, flags); |
26a7e094 CH |
516 | return -1; |
517 | ||
a7133a15 | 518 | found: |
36f7b2f3 | 519 | for (i = index; i < index + nslots; i++) { |
2d29960a | 520 | mem->slots[i].list = 0; |
36f7b2f3 CC |
521 | mem->slots[i].alloc_size = |
522 | alloc_size - (offset + ((i - index) << IO_TLB_SHIFT)); | |
523 | } | |
26a7e094 CH |
524 | for (i = index - 1; |
525 | io_tlb_offset(i) != IO_TLB_SEGSIZE - 1 && | |
2d29960a CH |
526 | mem->slots[i].list; i--) |
527 | mem->slots[i].list = ++count; | |
26a7e094 CH |
528 | |
529 | /* | |
530 | * Update the indices to avoid searching in the next round. | |
531 | */ | |
73f62095 CC |
532 | if (index + nslots < mem->nslabs) |
533 | mem->index = index + nslots; | |
26a7e094 | 534 | else |
73f62095 CC |
535 | mem->index = 0; |
536 | mem->used += nslots; | |
26a7e094 | 537 | |
73f62095 | 538 | spin_unlock_irqrestore(&mem->lock, flags); |
26a7e094 CH |
539 | return index; |
540 | } | |
541 | ||
542 | phys_addr_t swiotlb_tbl_map_single(struct device *dev, phys_addr_t orig_addr, | |
543 | size_t mapping_size, size_t alloc_size, | |
544 | enum dma_data_direction dir, unsigned long attrs) | |
545 | { | |
69031f50 | 546 | struct io_tlb_mem *mem = dev->dma_io_tlb_mem; |
1f221a0d | 547 | unsigned int offset = swiotlb_align_offset(dev, orig_addr); |
95b079d8 CC |
548 | unsigned int i; |
549 | int index; | |
26a7e094 CH |
550 | phys_addr_t tlb_addr; |
551 | ||
2d29960a | 552 | if (!mem) |
26a7e094 CH |
553 | panic("Can not allocate SWIOTLB buffer earlier and can't now provide you with the DMA bounce buffer"); |
554 | ||
555 | if (mem_encrypt_active()) | |
556 | pr_warn_once("Memory encryption is active and system is using DMA bounce buffers\n"); | |
557 | ||
558 | if (mapping_size > alloc_size) { | |
559 | dev_warn_once(dev, "Invalid sizes (mapping: %zd bytes, alloc: %zd bytes)", | |
560 | mapping_size, alloc_size); | |
561 | return (phys_addr_t)DMA_MAPPING_ERROR; | |
562 | } | |
563 | ||
36f7b2f3 | 564 | index = swiotlb_find_slots(dev, orig_addr, alloc_size + offset); |
26a7e094 CH |
565 | if (index == -1) { |
566 | if (!(attrs & DMA_ATTR_NO_WARN)) | |
567 | dev_warn_ratelimited(dev, | |
568 | "swiotlb buffer is full (sz: %zd bytes), total %lu (slots), used %lu (slots)\n", | |
73f62095 | 569 | alloc_size, mem->nslabs, mem->used); |
26a7e094 CH |
570 | return (phys_addr_t)DMA_MAPPING_ERROR; |
571 | } | |
1da177e4 LT |
572 | |
573 | /* | |
574 | * Save away the mapping from the original address to the DMA address. | |
575 | * This is needed when we sync the memory. Then we sync the buffer if | |
576 | * needed. | |
577 | */ | |
36f7b2f3 | 578 | for (i = 0; i < nr_slots(alloc_size + offset); i++) |
2d29960a | 579 | mem->slots[index + i].orig_addr = slot_addr(orig_addr, i); |
73f62095 | 580 | tlb_addr = slot_addr(mem->start, index) + offset; |
6a63c57a LT |
581 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) && |
582 | (!(attrs & DMA_ATTR_OVERWRITE) || dir == DMA_TO_DEVICE || | |
583 | dir == DMA_BIDIRECTIONAL)) | |
584 | swiotlb_bounce(dev, tlb_addr, mapping_size, DMA_TO_DEVICE); | |
e05ed4d1 | 585 | return tlb_addr; |
1da177e4 LT |
586 | } |
587 | ||
70347877 | 588 | static void swiotlb_release_slots(struct device *dev, phys_addr_t tlb_addr) |
1da177e4 | 589 | { |
70347877 | 590 | struct io_tlb_mem *mem = dev->dma_io_tlb_mem; |
1da177e4 | 591 | unsigned long flags; |
70347877 | 592 | unsigned int offset = swiotlb_align_offset(dev, tlb_addr); |
73f62095 | 593 | int index = (tlb_addr - offset - mem->start) >> IO_TLB_SHIFT; |
2d29960a | 594 | int nslots = nr_slots(mem->slots[index].alloc_size + offset); |
2bdba622 | 595 | int count, i; |
daf9514f | 596 | |
1da177e4 LT |
597 | /* |
598 | * Return the buffer to the free list by setting the corresponding | |
af901ca1 | 599 | * entries to indicate the number of contiguous entries available. |
1da177e4 LT |
600 | * While returning the entries to the free list, we merge the entries |
601 | * with slots below and above the pool being returned. | |
602 | */ | |
73f62095 | 603 | spin_lock_irqsave(&mem->lock, flags); |
ca10d0f8 | 604 | if (index + nslots < ALIGN(index + 1, IO_TLB_SEGSIZE)) |
2d29960a | 605 | count = mem->slots[index + nslots].list; |
ca10d0f8 CH |
606 | else |
607 | count = 0; | |
71602fe6 | 608 | |
ca10d0f8 CH |
609 | /* |
610 | * Step 1: return the slots to the free list, merging the slots with | |
611 | * superceeding slots | |
612 | */ | |
613 | for (i = index + nslots - 1; i >= index; i--) { | |
2d29960a CH |
614 | mem->slots[i].list = ++count; |
615 | mem->slots[i].orig_addr = INVALID_PHYS_ADDR; | |
616 | mem->slots[i].alloc_size = 0; | |
1da177e4 | 617 | } |
ca10d0f8 CH |
618 | |
619 | /* | |
620 | * Step 2: merge the returned slots with the preceding slots, if | |
621 | * available (non zero) | |
622 | */ | |
623 | for (i = index - 1; | |
2d29960a | 624 | io_tlb_offset(i) != IO_TLB_SEGSIZE - 1 && mem->slots[i].list; |
ca10d0f8 | 625 | i--) |
2d29960a | 626 | mem->slots[i].list = ++count; |
73f62095 CC |
627 | mem->used -= nslots; |
628 | spin_unlock_irqrestore(&mem->lock, flags); | |
1da177e4 LT |
629 | } |
630 | ||
70347877 CC |
631 | /* |
632 | * tlb_addr is the physical address of the bounce buffer to unmap. | |
633 | */ | |
634 | void swiotlb_tbl_unmap_single(struct device *dev, phys_addr_t tlb_addr, | |
635 | size_t mapping_size, enum dma_data_direction dir, | |
636 | unsigned long attrs) | |
637 | { | |
638 | /* | |
639 | * First, sync the memory before unmapping the entry | |
640 | */ | |
641 | if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) && | |
642 | (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
643 | swiotlb_bounce(dev, tlb_addr, mapping_size, DMA_FROM_DEVICE); | |
644 | ||
645 | swiotlb_release_slots(dev, tlb_addr); | |
646 | } | |
647 | ||
80808d27 CH |
648 | void swiotlb_sync_single_for_device(struct device *dev, phys_addr_t tlb_addr, |
649 | size_t size, enum dma_data_direction dir) | |
1da177e4 | 650 | { |
6a63c57a LT |
651 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) |
652 | swiotlb_bounce(dev, tlb_addr, size, DMA_TO_DEVICE); | |
653 | else | |
654 | BUG_ON(dir != DMA_FROM_DEVICE); | |
80808d27 CH |
655 | } |
656 | ||
657 | void swiotlb_sync_single_for_cpu(struct device *dev, phys_addr_t tlb_addr, | |
658 | size_t size, enum dma_data_direction dir) | |
659 | { | |
660 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) | |
661 | swiotlb_bounce(dev, tlb_addr, size, DMA_FROM_DEVICE); | |
662 | else | |
663 | BUG_ON(dir != DMA_TO_DEVICE); | |
1da177e4 LT |
664 | } |
665 | ||
55897af6 | 666 | /* |
4a47cbae | 667 | * Create a swiotlb mapping for the buffer at @paddr, and in case of DMAing |
55897af6 CH |
668 | * to the device copy the data into it as well. |
669 | */ | |
4a47cbae CH |
670 | dma_addr_t swiotlb_map(struct device *dev, phys_addr_t paddr, size_t size, |
671 | enum dma_data_direction dir, unsigned long attrs) | |
c4dae366 | 672 | { |
4a47cbae CH |
673 | phys_addr_t swiotlb_addr; |
674 | dma_addr_t dma_addr; | |
c4dae366 | 675 | |
4a47cbae CH |
676 | trace_swiotlb_bounced(dev, phys_to_dma(dev, paddr), size, |
677 | swiotlb_force); | |
c4dae366 | 678 | |
fc0021aa CH |
679 | swiotlb_addr = swiotlb_tbl_map_single(dev, paddr, size, size, dir, |
680 | attrs); | |
4a47cbae CH |
681 | if (swiotlb_addr == (phys_addr_t)DMA_MAPPING_ERROR) |
682 | return DMA_MAPPING_ERROR; | |
c4dae366 CH |
683 | |
684 | /* Ensure that the address returned is DMA'ble */ | |
5ceda740 | 685 | dma_addr = phys_to_dma_unencrypted(dev, swiotlb_addr); |
4a47cbae | 686 | if (unlikely(!dma_capable(dev, dma_addr, size, true))) { |
2973073a | 687 | swiotlb_tbl_unmap_single(dev, swiotlb_addr, size, dir, |
c4dae366 | 688 | attrs | DMA_ATTR_SKIP_CPU_SYNC); |
4a47cbae CH |
689 | dev_WARN_ONCE(dev, 1, |
690 | "swiotlb addr %pad+%zu overflow (mask %llx, bus limit %llx).\n", | |
691 | &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit); | |
692 | return DMA_MAPPING_ERROR; | |
a4a4330d CH |
693 | } |
694 | ||
4a47cbae CH |
695 | if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) |
696 | arch_sync_dma_for_device(swiotlb_addr, size, dir); | |
697 | return dma_addr; | |
1da177e4 LT |
698 | } |
699 | ||
abe420bf JR |
700 | size_t swiotlb_max_mapping_size(struct device *dev) |
701 | { | |
b5d7ccb7 | 702 | return ((size_t)IO_TLB_SIZE) * IO_TLB_SEGSIZE; |
abe420bf | 703 | } |
492366f7 | 704 | |
6f2beb26 | 705 | bool is_swiotlb_active(struct device *dev) |
492366f7 | 706 | { |
463e862a WD |
707 | struct io_tlb_mem *mem = dev->dma_io_tlb_mem; |
708 | ||
709 | return mem && mem->nslabs; | |
492366f7 | 710 | } |
2cbc2776 | 711 | EXPORT_SYMBOL_GPL(is_swiotlb_active); |
45ba8d5d | 712 | |
71602fe6 | 713 | #ifdef CONFIG_DEBUG_FS |
6e675a1c | 714 | static struct dentry *debugfs_dir; |
71602fe6 | 715 | |
6e675a1c | 716 | static void swiotlb_create_debugfs_files(struct io_tlb_mem *mem) |
71602fe6 | 717 | { |
73f62095 CC |
718 | debugfs_create_ulong("io_tlb_nslabs", 0400, mem->debugfs, &mem->nslabs); |
719 | debugfs_create_ulong("io_tlb_used", 0400, mem->debugfs, &mem->used); | |
6e675a1c CC |
720 | } |
721 | ||
722 | static int __init swiotlb_create_default_debugfs(void) | |
723 | { | |
463e862a | 724 | struct io_tlb_mem *mem = &io_tlb_default_mem; |
6e675a1c CC |
725 | |
726 | debugfs_dir = debugfs_create_dir("swiotlb", NULL); | |
463e862a | 727 | if (mem->nslabs) { |
6e675a1c CC |
728 | mem->debugfs = debugfs_dir; |
729 | swiotlb_create_debugfs_files(mem); | |
730 | } | |
71602fe6 | 731 | return 0; |
71602fe6 DZ |
732 | } |
733 | ||
6e675a1c | 734 | late_initcall(swiotlb_create_default_debugfs); |
71602fe6 DZ |
735 | |
736 | #endif | |
f4111e39 CC |
737 | |
738 | #ifdef CONFIG_DMA_RESTRICTED_POOL | |
09a4a79d CC |
739 | |
740 | #ifdef CONFIG_DEBUG_FS | |
741 | static void rmem_swiotlb_debugfs_init(struct reserved_mem *rmem) | |
742 | { | |
743 | struct io_tlb_mem *mem = rmem->priv; | |
744 | ||
745 | mem->debugfs = debugfs_create_dir(rmem->name, debugfs_dir); | |
746 | swiotlb_create_debugfs_files(mem); | |
747 | } | |
748 | #else | |
749 | static void rmem_swiotlb_debugfs_init(struct reserved_mem *rmem) | |
750 | { | |
751 | } | |
752 | #endif | |
753 | ||
f4111e39 CC |
754 | struct page *swiotlb_alloc(struct device *dev, size_t size) |
755 | { | |
756 | struct io_tlb_mem *mem = dev->dma_io_tlb_mem; | |
757 | phys_addr_t tlb_addr; | |
758 | int index; | |
759 | ||
760 | if (!mem) | |
761 | return NULL; | |
762 | ||
763 | index = swiotlb_find_slots(dev, 0, size); | |
764 | if (index == -1) | |
765 | return NULL; | |
766 | ||
767 | tlb_addr = slot_addr(mem->start, index); | |
768 | ||
769 | return pfn_to_page(PFN_DOWN(tlb_addr)); | |
770 | } | |
771 | ||
772 | bool swiotlb_free(struct device *dev, struct page *page, size_t size) | |
773 | { | |
774 | phys_addr_t tlb_addr = page_to_phys(page); | |
775 | ||
776 | if (!is_swiotlb_buffer(dev, tlb_addr)) | |
777 | return false; | |
778 | ||
779 | swiotlb_release_slots(dev, tlb_addr); | |
780 | ||
781 | return true; | |
782 | } | |
783 | ||
0b84e4f8 CC |
784 | static int rmem_swiotlb_device_init(struct reserved_mem *rmem, |
785 | struct device *dev) | |
786 | { | |
787 | struct io_tlb_mem *mem = rmem->priv; | |
788 | unsigned long nslabs = rmem->size >> IO_TLB_SHIFT; | |
789 | ||
790 | /* | |
791 | * Since multiple devices can share the same pool, the private data, | |
792 | * io_tlb_mem struct, will be initialized by the first device attached | |
793 | * to it. | |
794 | */ | |
795 | if (!mem) { | |
463e862a | 796 | mem = kzalloc(sizeof(*mem), GFP_KERNEL); |
0b84e4f8 CC |
797 | if (!mem) |
798 | return -ENOMEM; | |
799 | ||
463e862a WD |
800 | mem->slots = kzalloc(array_size(sizeof(*mem->slots), nslabs), |
801 | GFP_KERNEL); | |
802 | if (!mem->slots) { | |
803 | kfree(mem); | |
804 | return -ENOMEM; | |
805 | } | |
806 | ||
0b84e4f8 CC |
807 | set_memory_decrypted((unsigned long)phys_to_virt(rmem->base), |
808 | rmem->size >> PAGE_SHIFT); | |
809 | swiotlb_init_io_tlb_mem(mem, rmem->base, nslabs, false); | |
810 | mem->force_bounce = true; | |
811 | mem->for_alloc = true; | |
812 | ||
813 | rmem->priv = mem; | |
814 | ||
09a4a79d | 815 | rmem_swiotlb_debugfs_init(rmem); |
0b84e4f8 CC |
816 | } |
817 | ||
818 | dev->dma_io_tlb_mem = mem; | |
819 | ||
820 | return 0; | |
821 | } | |
822 | ||
823 | static void rmem_swiotlb_device_release(struct reserved_mem *rmem, | |
824 | struct device *dev) | |
825 | { | |
463e862a | 826 | dev->dma_io_tlb_mem = &io_tlb_default_mem; |
0b84e4f8 CC |
827 | } |
828 | ||
829 | static const struct reserved_mem_ops rmem_swiotlb_ops = { | |
830 | .device_init = rmem_swiotlb_device_init, | |
831 | .device_release = rmem_swiotlb_device_release, | |
832 | }; | |
833 | ||
834 | static int __init rmem_swiotlb_setup(struct reserved_mem *rmem) | |
835 | { | |
836 | unsigned long node = rmem->fdt_node; | |
837 | ||
838 | if (of_get_flat_dt_prop(node, "reusable", NULL) || | |
839 | of_get_flat_dt_prop(node, "linux,cma-default", NULL) || | |
840 | of_get_flat_dt_prop(node, "linux,dma-default", NULL) || | |
841 | of_get_flat_dt_prop(node, "no-map", NULL)) | |
842 | return -EINVAL; | |
843 | ||
844 | if (PageHighMem(pfn_to_page(PHYS_PFN(rmem->base)))) { | |
845 | pr_err("Restricted DMA pool must be accessible within the linear mapping."); | |
846 | return -EINVAL; | |
847 | } | |
848 | ||
849 | rmem->ops = &rmem_swiotlb_ops; | |
850 | pr_info("Reserved memory: created restricted DMA pool at %pa, size %ld MiB\n", | |
851 | &rmem->base, (unsigned long)rmem->size / SZ_1M); | |
852 | return 0; | |
853 | } | |
854 | ||
855 | RESERVEDMEM_OF_DECLARE(dma, "restricted-dma-pool", rmem_swiotlb_setup); | |
f4111e39 | 856 | #endif /* CONFIG_DMA_RESTRICTED_POOL */ |