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CommitLineData
dd87eb3a
TG
1/*
2 * linux/kernel/irq/chip.c
3 *
4 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
5 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 *
7 * This file contains the core interrupt handling code, for irq-chip
8 * based architectures.
9 *
10 * Detailed information is available in Documentation/DocBook/genericirq
11 */
12
13#include <linux/irq.h>
7fe3730d 14#include <linux/msi.h>
dd87eb3a
TG
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/kernel_stat.h>
18
f069686e
SR
19#include <trace/events/irq.h>
20
dd87eb3a
TG
21#include "internals.h"
22
23/**
a0cd9ca2 24 * irq_set_chip - set the irq chip for an irq
dd87eb3a
TG
25 * @irq: irq number
26 * @chip: pointer to irq chip description structure
27 */
a0cd9ca2 28int irq_set_chip(unsigned int irq, struct irq_chip *chip)
dd87eb3a 29{
dd87eb3a 30 unsigned long flags;
31d9d9b6 31 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 32
02725e74 33 if (!desc)
dd87eb3a 34 return -EINVAL;
dd87eb3a
TG
35
36 if (!chip)
37 chip = &no_irq_chip;
38
6b8ff312 39 desc->irq_data.chip = chip;
02725e74 40 irq_put_desc_unlock(desc, flags);
d72274e5
DD
41 /*
42 * For !CONFIG_SPARSE_IRQ make the irq show up in
43 * allocated_irqs. For the CONFIG_SPARSE_IRQ case, it is
44 * already marked, and this call is harmless.
45 */
46 irq_reserve_irq(irq);
dd87eb3a
TG
47 return 0;
48}
a0cd9ca2 49EXPORT_SYMBOL(irq_set_chip);
dd87eb3a
TG
50
51/**
a0cd9ca2 52 * irq_set_type - set the irq trigger type for an irq
dd87eb3a 53 * @irq: irq number
0c5d1eb7 54 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
dd87eb3a 55 */
a0cd9ca2 56int irq_set_irq_type(unsigned int irq, unsigned int type)
dd87eb3a 57{
dd87eb3a 58 unsigned long flags;
31d9d9b6 59 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
02725e74 60 int ret = 0;
dd87eb3a 61
02725e74
TG
62 if (!desc)
63 return -EINVAL;
dd87eb3a 64
f2b662da 65 type &= IRQ_TYPE_SENSE_MASK;
a09b659c 66 ret = __irq_set_trigger(desc, irq, type);
02725e74 67 irq_put_desc_busunlock(desc, flags);
dd87eb3a
TG
68 return ret;
69}
a0cd9ca2 70EXPORT_SYMBOL(irq_set_irq_type);
dd87eb3a
TG
71
72/**
a0cd9ca2 73 * irq_set_handler_data - set irq handler data for an irq
dd87eb3a
TG
74 * @irq: Interrupt number
75 * @data: Pointer to interrupt specific data
76 *
77 * Set the hardware irq controller data for an irq
78 */
a0cd9ca2 79int irq_set_handler_data(unsigned int irq, void *data)
dd87eb3a 80{
dd87eb3a 81 unsigned long flags;
31d9d9b6 82 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 83
02725e74 84 if (!desc)
dd87eb3a 85 return -EINVAL;
6b8ff312 86 desc->irq_data.handler_data = data;
02725e74 87 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
88 return 0;
89}
a0cd9ca2 90EXPORT_SYMBOL(irq_set_handler_data);
dd87eb3a 91
5b912c10 92/**
a0cd9ca2 93 * irq_set_msi_desc - set MSI descriptor data for an irq
5b912c10 94 * @irq: Interrupt number
472900b8 95 * @entry: Pointer to MSI descriptor data
5b912c10 96 *
24b26d42 97 * Set the MSI descriptor entry for an irq
5b912c10 98 */
a0cd9ca2 99int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
5b912c10 100{
5b912c10 101 unsigned long flags;
31d9d9b6 102 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
5b912c10 103
02725e74 104 if (!desc)
5b912c10 105 return -EINVAL;
6b8ff312 106 desc->irq_data.msi_desc = entry;
7fe3730d
ME
107 if (entry)
108 entry->irq = irq;
02725e74 109 irq_put_desc_unlock(desc, flags);
5b912c10
EB
110 return 0;
111}
112
dd87eb3a 113/**
a0cd9ca2 114 * irq_set_chip_data - set irq chip data for an irq
dd87eb3a
TG
115 * @irq: Interrupt number
116 * @data: Pointer to chip specific data
117 *
118 * Set the hardware irq chip data for an irq
119 */
a0cd9ca2 120int irq_set_chip_data(unsigned int irq, void *data)
dd87eb3a 121{
dd87eb3a 122 unsigned long flags;
31d9d9b6 123 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 124
02725e74 125 if (!desc)
dd87eb3a 126 return -EINVAL;
6b8ff312 127 desc->irq_data.chip_data = data;
02725e74 128 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
129 return 0;
130}
a0cd9ca2 131EXPORT_SYMBOL(irq_set_chip_data);
dd87eb3a 132
f303a6dd
TG
133struct irq_data *irq_get_irq_data(unsigned int irq)
134{
135 struct irq_desc *desc = irq_to_desc(irq);
136
137 return desc ? &desc->irq_data : NULL;
138}
139EXPORT_SYMBOL_GPL(irq_get_irq_data);
140
c1594b77
TG
141static void irq_state_clr_disabled(struct irq_desc *desc)
142{
801a0e9a 143 irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
144}
145
146static void irq_state_set_disabled(struct irq_desc *desc)
147{
801a0e9a 148 irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
149}
150
6e40262e
TG
151static void irq_state_clr_masked(struct irq_desc *desc)
152{
32f4125e 153 irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
154}
155
156static void irq_state_set_masked(struct irq_desc *desc)
157{
32f4125e 158 irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
159}
160
b4bc724e 161int irq_startup(struct irq_desc *desc, bool resend)
46999238 162{
b4bc724e
TG
163 int ret = 0;
164
c1594b77 165 irq_state_clr_disabled(desc);
46999238
TG
166 desc->depth = 0;
167
3aae994f 168 if (desc->irq_data.chip->irq_startup) {
b4bc724e 169 ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
6e40262e 170 irq_state_clr_masked(desc);
b4bc724e
TG
171 } else {
172 irq_enable(desc);
3aae994f 173 }
b4bc724e
TG
174 if (resend)
175 check_irq_resend(desc, desc->irq_data.irq);
176 return ret;
46999238
TG
177}
178
179void irq_shutdown(struct irq_desc *desc)
180{
c1594b77 181 irq_state_set_disabled(desc);
46999238 182 desc->depth = 1;
50f7c032
TG
183 if (desc->irq_data.chip->irq_shutdown)
184 desc->irq_data.chip->irq_shutdown(&desc->irq_data);
ed585a65 185 else if (desc->irq_data.chip->irq_disable)
50f7c032
TG
186 desc->irq_data.chip->irq_disable(&desc->irq_data);
187 else
188 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 189 irq_state_set_masked(desc);
46999238
TG
190}
191
87923470
TG
192void irq_enable(struct irq_desc *desc)
193{
c1594b77 194 irq_state_clr_disabled(desc);
50f7c032
TG
195 if (desc->irq_data.chip->irq_enable)
196 desc->irq_data.chip->irq_enable(&desc->irq_data);
197 else
198 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 199 irq_state_clr_masked(desc);
dd87eb3a
TG
200}
201
50f7c032 202void irq_disable(struct irq_desc *desc)
89d694b9 203{
c1594b77 204 irq_state_set_disabled(desc);
50f7c032
TG
205 if (desc->irq_data.chip->irq_disable) {
206 desc->irq_data.chip->irq_disable(&desc->irq_data);
a61d8258 207 irq_state_set_masked(desc);
50f7c032 208 }
89d694b9
TG
209}
210
31d9d9b6
MZ
211void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu)
212{
213 if (desc->irq_data.chip->irq_enable)
214 desc->irq_data.chip->irq_enable(&desc->irq_data);
215 else
216 desc->irq_data.chip->irq_unmask(&desc->irq_data);
217 cpumask_set_cpu(cpu, desc->percpu_enabled);
218}
219
220void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu)
221{
222 if (desc->irq_data.chip->irq_disable)
223 desc->irq_data.chip->irq_disable(&desc->irq_data);
224 else
225 desc->irq_data.chip->irq_mask(&desc->irq_data);
226 cpumask_clear_cpu(cpu, desc->percpu_enabled);
227}
228
9205e31d 229static inline void mask_ack_irq(struct irq_desc *desc)
dd87eb3a 230{
9205e31d
TG
231 if (desc->irq_data.chip->irq_mask_ack)
232 desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
dd87eb3a 233 else {
e2c0f8ff 234 desc->irq_data.chip->irq_mask(&desc->irq_data);
22a49163
TG
235 if (desc->irq_data.chip->irq_ack)
236 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 237 }
6e40262e 238 irq_state_set_masked(desc);
0b1adaa0
TG
239}
240
d4d5e089 241void mask_irq(struct irq_desc *desc)
0b1adaa0 242{
e2c0f8ff
TG
243 if (desc->irq_data.chip->irq_mask) {
244 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 245 irq_state_set_masked(desc);
0b1adaa0
TG
246 }
247}
248
d4d5e089 249void unmask_irq(struct irq_desc *desc)
0b1adaa0 250{
0eda58b7
TG
251 if (desc->irq_data.chip->irq_unmask) {
252 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 253 irq_state_clr_masked(desc);
0b1adaa0 254 }
dd87eb3a
TG
255}
256
399b5da2
TG
257/*
258 * handle_nested_irq - Handle a nested irq from a irq thread
259 * @irq: the interrupt number
260 *
261 * Handle interrupts which are nested into a threaded interrupt
262 * handler. The handler function is called inside the calling
263 * threads context.
264 */
265void handle_nested_irq(unsigned int irq)
266{
267 struct irq_desc *desc = irq_to_desc(irq);
268 struct irqaction *action;
269 irqreturn_t action_ret;
270
271 might_sleep();
272
239007b8 273 raw_spin_lock_irq(&desc->lock);
399b5da2
TG
274
275 kstat_incr_irqs_this_cpu(irq, desc);
276
277 action = desc->action;
23812b9d
NJ
278 if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) {
279 desc->istate |= IRQS_PENDING;
399b5da2 280 goto out_unlock;
23812b9d 281 }
399b5da2 282
32f4125e 283 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
239007b8 284 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
285
286 action_ret = action->thread_fn(action->irq, action->dev_id);
287 if (!noirqdebug)
288 note_interrupt(irq, desc, action_ret);
289
239007b8 290 raw_spin_lock_irq(&desc->lock);
32f4125e 291 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
399b5da2
TG
292
293out_unlock:
239007b8 294 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
295}
296EXPORT_SYMBOL_GPL(handle_nested_irq);
297
fe200ae4
TG
298static bool irq_check_poll(struct irq_desc *desc)
299{
6954b75b 300 if (!(desc->istate & IRQS_POLL_INPROGRESS))
fe200ae4
TG
301 return false;
302 return irq_wait_for_poll(desc);
303}
304
dd87eb3a
TG
305/**
306 * handle_simple_irq - Simple and software-decoded IRQs.
307 * @irq: the interrupt number
308 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
309 *
310 * Simple interrupts are either sent from a demultiplexing interrupt
311 * handler or come from hardware, where no interrupt hardware control
312 * is necessary.
313 *
314 * Note: The caller is expected to handle the ack, clear, mask and
315 * unmask issues if necessary.
316 */
7ad5b3a5 317void
7d12e780 318handle_simple_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 319{
239007b8 320 raw_spin_lock(&desc->lock);
dd87eb3a 321
32f4125e 322 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
323 if (!irq_check_poll(desc))
324 goto out_unlock;
325
163ef309 326 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 327 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 328
23812b9d
NJ
329 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
330 desc->istate |= IRQS_PENDING;
dd87eb3a 331 goto out_unlock;
23812b9d 332 }
dd87eb3a 333
107781e7 334 handle_irq_event(desc);
dd87eb3a 335
dd87eb3a 336out_unlock:
239007b8 337 raw_spin_unlock(&desc->lock);
dd87eb3a 338}
edf76f83 339EXPORT_SYMBOL_GPL(handle_simple_irq);
dd87eb3a 340
ac563761
TG
341/*
342 * Called unconditionally from handle_level_irq() and only for oneshot
343 * interrupts from handle_fasteoi_irq()
344 */
345static void cond_unmask_irq(struct irq_desc *desc)
346{
347 /*
348 * We need to unmask in the following cases:
349 * - Standard level irq (IRQF_ONESHOT is not set)
350 * - Oneshot irq which did not wake the thread (caused by a
351 * spurious interrupt or a primary handler handling it
352 * completely).
353 */
354 if (!irqd_irq_disabled(&desc->irq_data) &&
355 irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot)
356 unmask_irq(desc);
357}
358
dd87eb3a
TG
359/**
360 * handle_level_irq - Level type irq handler
361 * @irq: the interrupt number
362 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
363 *
364 * Level type interrupts are active as long as the hardware line has
365 * the active level. This may require to mask the interrupt and unmask
366 * it after the associated handler has acknowledged the device, so the
367 * interrupt line is back to inactive.
368 */
7ad5b3a5 369void
7d12e780 370handle_level_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 371{
239007b8 372 raw_spin_lock(&desc->lock);
9205e31d 373 mask_ack_irq(desc);
dd87eb3a 374
32f4125e 375 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
376 if (!irq_check_poll(desc))
377 goto out_unlock;
378
163ef309 379 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 380 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
381
382 /*
383 * If its disabled or no action available
384 * keep it masked and get out of here
385 */
d4dc0f90
TG
386 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
387 desc->istate |= IRQS_PENDING;
86998aa6 388 goto out_unlock;
d4dc0f90 389 }
dd87eb3a 390
1529866c 391 handle_irq_event(desc);
b25c340c 392
ac563761
TG
393 cond_unmask_irq(desc);
394
86998aa6 395out_unlock:
239007b8 396 raw_spin_unlock(&desc->lock);
dd87eb3a 397}
14819ea1 398EXPORT_SYMBOL_GPL(handle_level_irq);
dd87eb3a 399
78129576
TG
400#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
401static inline void preflow_handler(struct irq_desc *desc)
402{
403 if (desc->preflow_handler)
404 desc->preflow_handler(&desc->irq_data);
405}
406#else
407static inline void preflow_handler(struct irq_desc *desc) { }
408#endif
409
dd87eb3a 410/**
47c2a3aa 411 * handle_fasteoi_irq - irq handler for transparent controllers
dd87eb3a
TG
412 * @irq: the interrupt number
413 * @desc: the interrupt description structure for this irq
dd87eb3a 414 *
47c2a3aa 415 * Only a single callback will be issued to the chip: an ->eoi()
dd87eb3a
TG
416 * call when the interrupt has been serviced. This enables support
417 * for modern forms of interrupt handlers, which handle the flow
418 * details in hardware, transparently.
419 */
7ad5b3a5 420void
7d12e780 421handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 422{
239007b8 423 raw_spin_lock(&desc->lock);
dd87eb3a 424
32f4125e 425 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
426 if (!irq_check_poll(desc))
427 goto out;
dd87eb3a 428
163ef309 429 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 430 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
431
432 /*
433 * If its disabled or no action available
76d21601 434 * then mask it and get out of here:
dd87eb3a 435 */
32f4125e 436 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
2a0d6fb3 437 desc->istate |= IRQS_PENDING;
e2c0f8ff 438 mask_irq(desc);
dd87eb3a 439 goto out;
98bb244b 440 }
c69e3758
TG
441
442 if (desc->istate & IRQS_ONESHOT)
443 mask_irq(desc);
444
78129576 445 preflow_handler(desc);
a7ae4de5 446 handle_irq_event(desc);
77694b40 447
ac563761
TG
448 if (desc->istate & IRQS_ONESHOT)
449 cond_unmask_irq(desc);
450
77694b40 451out_eoi:
0c5c1557 452 desc->irq_data.chip->irq_eoi(&desc->irq_data);
77694b40 453out_unlock:
239007b8 454 raw_spin_unlock(&desc->lock);
77694b40
TG
455 return;
456out:
457 if (!(desc->irq_data.chip->flags & IRQCHIP_EOI_IF_HANDLED))
458 goto out_eoi;
459 goto out_unlock;
dd87eb3a
TG
460}
461
462/**
463 * handle_edge_irq - edge type IRQ handler
464 * @irq: the interrupt number
465 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
466 *
467 * Interrupt occures on the falling and/or rising edge of a hardware
25985edc 468 * signal. The occurrence is latched into the irq controller hardware
dd87eb3a
TG
469 * and must be acked in order to be reenabled. After the ack another
470 * interrupt can happen on the same source even before the first one
dfff0615 471 * is handled by the associated event handler. If this happens it
dd87eb3a
TG
472 * might be necessary to disable (mask) the interrupt depending on the
473 * controller hardware. This requires to reenable the interrupt inside
474 * of the loop which handles the interrupts which have arrived while
475 * the handler was running. If all pending interrupts are handled, the
476 * loop is left.
477 */
7ad5b3a5 478void
7d12e780 479handle_edge_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 480{
239007b8 481 raw_spin_lock(&desc->lock);
dd87eb3a 482
163ef309 483 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
484 /*
485 * If we're currently running this IRQ, or its disabled,
486 * we shouldn't process the IRQ. Mark it pending, handle
487 * the necessary masking and go out
488 */
32f4125e
TG
489 if (unlikely(irqd_irq_disabled(&desc->irq_data) ||
490 irqd_irq_inprogress(&desc->irq_data) || !desc->action)) {
fe200ae4 491 if (!irq_check_poll(desc)) {
2a0d6fb3 492 desc->istate |= IRQS_PENDING;
fe200ae4
TG
493 mask_ack_irq(desc);
494 goto out_unlock;
495 }
dd87eb3a 496 }
d6c88a50 497 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
498
499 /* Start handling the irq */
22a49163 500 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 501
dd87eb3a 502 do {
a60a5dc2 503 if (unlikely(!desc->action)) {
e2c0f8ff 504 mask_irq(desc);
dd87eb3a
TG
505 goto out_unlock;
506 }
507
508 /*
509 * When another irq arrived while we were handling
510 * one, we could have masked the irq.
511 * Renable it, if it was not disabled in meantime.
512 */
2a0d6fb3 513 if (unlikely(desc->istate & IRQS_PENDING)) {
32f4125e
TG
514 if (!irqd_irq_disabled(&desc->irq_data) &&
515 irqd_irq_masked(&desc->irq_data))
c1594b77 516 unmask_irq(desc);
dd87eb3a
TG
517 }
518
a60a5dc2 519 handle_irq_event(desc);
dd87eb3a 520
2a0d6fb3 521 } while ((desc->istate & IRQS_PENDING) &&
32f4125e 522 !irqd_irq_disabled(&desc->irq_data));
dd87eb3a 523
dd87eb3a 524out_unlock:
239007b8 525 raw_spin_unlock(&desc->lock);
dd87eb3a 526}
3911ff30 527EXPORT_SYMBOL(handle_edge_irq);
dd87eb3a 528
0521c8fb
TG
529#ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
530/**
531 * handle_edge_eoi_irq - edge eoi type IRQ handler
532 * @irq: the interrupt number
533 * @desc: the interrupt description structure for this irq
534 *
535 * Similar as the above handle_edge_irq, but using eoi and w/o the
536 * mask/unmask logic.
537 */
538void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc)
539{
540 struct irq_chip *chip = irq_desc_get_chip(desc);
541
542 raw_spin_lock(&desc->lock);
543
544 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
545 /*
546 * If we're currently running this IRQ, or its disabled,
547 * we shouldn't process the IRQ. Mark it pending, handle
548 * the necessary masking and go out
549 */
550 if (unlikely(irqd_irq_disabled(&desc->irq_data) ||
551 irqd_irq_inprogress(&desc->irq_data) || !desc->action)) {
552 if (!irq_check_poll(desc)) {
553 desc->istate |= IRQS_PENDING;
554 goto out_eoi;
555 }
556 }
557 kstat_incr_irqs_this_cpu(irq, desc);
558
559 do {
560 if (unlikely(!desc->action))
561 goto out_eoi;
562
563 handle_irq_event(desc);
564
565 } while ((desc->istate & IRQS_PENDING) &&
566 !irqd_irq_disabled(&desc->irq_data));
567
ac0e0447 568out_eoi:
0521c8fb
TG
569 chip->irq_eoi(&desc->irq_data);
570 raw_spin_unlock(&desc->lock);
571}
572#endif
573
dd87eb3a 574/**
24b26d42 575 * handle_percpu_irq - Per CPU local irq handler
dd87eb3a
TG
576 * @irq: the interrupt number
577 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
578 *
579 * Per CPU interrupts on SMP machines without locking requirements
580 */
7ad5b3a5 581void
7d12e780 582handle_percpu_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 583{
35e857cb 584 struct irq_chip *chip = irq_desc_get_chip(desc);
dd87eb3a 585
d6c88a50 586 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 587
849f061c
TG
588 if (chip->irq_ack)
589 chip->irq_ack(&desc->irq_data);
dd87eb3a 590
849f061c 591 handle_irq_event_percpu(desc, desc->action);
dd87eb3a 592
849f061c
TG
593 if (chip->irq_eoi)
594 chip->irq_eoi(&desc->irq_data);
dd87eb3a
TG
595}
596
31d9d9b6
MZ
597/**
598 * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
599 * @irq: the interrupt number
600 * @desc: the interrupt description structure for this irq
601 *
602 * Per CPU interrupts on SMP machines without locking requirements. Same as
603 * handle_percpu_irq() above but with the following extras:
604 *
605 * action->percpu_dev_id is a pointer to percpu variables which
606 * contain the real device id for the cpu on which this handler is
607 * called
608 */
609void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc)
610{
611 struct irq_chip *chip = irq_desc_get_chip(desc);
612 struct irqaction *action = desc->action;
613 void *dev_id = __this_cpu_ptr(action->percpu_dev_id);
614 irqreturn_t res;
615
616 kstat_incr_irqs_this_cpu(irq, desc);
617
618 if (chip->irq_ack)
619 chip->irq_ack(&desc->irq_data);
620
621 trace_irq_handler_entry(irq, action);
622 res = action->handler(irq, dev_id);
623 trace_irq_handler_exit(irq, action, res);
624
625 if (chip->irq_eoi)
626 chip->irq_eoi(&desc->irq_data);
627}
628
dd87eb3a 629void
3836ca08 630__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
a460e745 631 const char *name)
dd87eb3a 632{
dd87eb3a 633 unsigned long flags;
31d9d9b6 634 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
dd87eb3a 635
02725e74 636 if (!desc)
dd87eb3a 637 return;
dd87eb3a 638
091738a2 639 if (!handle) {
dd87eb3a 640 handle = handle_bad_irq;
091738a2
TG
641 } else {
642 if (WARN_ON(desc->irq_data.chip == &no_irq_chip))
02725e74 643 goto out;
f8b5473f 644 }
dd87eb3a 645
dd87eb3a
TG
646 /* Uninstall? */
647 if (handle == handle_bad_irq) {
6b8ff312 648 if (desc->irq_data.chip != &no_irq_chip)
9205e31d 649 mask_ack_irq(desc);
801a0e9a 650 irq_state_set_disabled(desc);
dd87eb3a
TG
651 desc->depth = 1;
652 }
653 desc->handle_irq = handle;
a460e745 654 desc->name = name;
dd87eb3a
TG
655
656 if (handle != handle_bad_irq && is_chained) {
1ccb4e61
TG
657 irq_settings_set_noprobe(desc);
658 irq_settings_set_norequest(desc);
7f1b1244 659 irq_settings_set_nothread(desc);
b4bc724e 660 irq_startup(desc, true);
dd87eb3a 661 }
02725e74
TG
662out:
663 irq_put_desc_busunlock(desc, flags);
dd87eb3a 664}
3836ca08 665EXPORT_SYMBOL_GPL(__irq_set_handler);
dd87eb3a
TG
666
667void
3836ca08 668irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
a460e745 669 irq_flow_handler_t handle, const char *name)
dd87eb3a 670{
35e857cb 671 irq_set_chip(irq, chip);
3836ca08 672 __irq_set_handler(irq, handle, 0, name);
dd87eb3a 673}
b3ae66f2 674EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name);
46f4f8f6 675
44247184 676void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
46f4f8f6 677{
46f4f8f6 678 unsigned long flags;
31d9d9b6 679 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
46f4f8f6 680
44247184 681 if (!desc)
46f4f8f6 682 return;
a005677b
TG
683 irq_settings_clr_and_set(desc, clr, set);
684
876dbd4c 685 irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
e1ef8241 686 IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
a005677b
TG
687 if (irq_settings_has_no_balance_set(desc))
688 irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
689 if (irq_settings_is_per_cpu(desc))
690 irqd_set(&desc->irq_data, IRQD_PER_CPU);
e1ef8241
TG
691 if (irq_settings_can_move_pcntxt(desc))
692 irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
0ef5ca1e
TG
693 if (irq_settings_is_level(desc))
694 irqd_set(&desc->irq_data, IRQD_LEVEL);
a005677b 695
876dbd4c
TG
696 irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc));
697
02725e74 698 irq_put_desc_unlock(desc, flags);
46f4f8f6 699}
edf76f83 700EXPORT_SYMBOL_GPL(irq_modify_status);
0fdb4b25
DD
701
702/**
703 * irq_cpu_online - Invoke all irq_cpu_online functions.
704 *
705 * Iterate through all irqs and invoke the chip.irq_cpu_online()
706 * for each.
707 */
708void irq_cpu_online(void)
709{
710 struct irq_desc *desc;
711 struct irq_chip *chip;
712 unsigned long flags;
713 unsigned int irq;
714
715 for_each_active_irq(irq) {
716 desc = irq_to_desc(irq);
717 if (!desc)
718 continue;
719
720 raw_spin_lock_irqsave(&desc->lock, flags);
721
722 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
723 if (chip && chip->irq_cpu_online &&
724 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 725 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
726 chip->irq_cpu_online(&desc->irq_data);
727
728 raw_spin_unlock_irqrestore(&desc->lock, flags);
729 }
730}
731
732/**
733 * irq_cpu_offline - Invoke all irq_cpu_offline functions.
734 *
735 * Iterate through all irqs and invoke the chip.irq_cpu_offline()
736 * for each.
737 */
738void irq_cpu_offline(void)
739{
740 struct irq_desc *desc;
741 struct irq_chip *chip;
742 unsigned long flags;
743 unsigned int irq;
744
745 for_each_active_irq(irq) {
746 desc = irq_to_desc(irq);
747 if (!desc)
748 continue;
749
750 raw_spin_lock_irqsave(&desc->lock, flags);
751
752 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
753 if (chip && chip->irq_cpu_offline &&
754 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 755 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
756 chip->irq_cpu_offline(&desc->irq_data);
757
758 raw_spin_unlock_irqrestore(&desc->lock, flags);
759 }
760}