]>
Commit | Line | Data |
---|---|---|
dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
18 | ||
f069686e SR |
19 | #include <trace/events/irq.h> |
20 | ||
dd87eb3a TG |
21 | #include "internals.h" |
22 | ||
23 | /** | |
a0cd9ca2 | 24 | * irq_set_chip - set the irq chip for an irq |
dd87eb3a TG |
25 | * @irq: irq number |
26 | * @chip: pointer to irq chip description structure | |
27 | */ | |
a0cd9ca2 | 28 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) |
dd87eb3a | 29 | { |
dd87eb3a | 30 | unsigned long flags; |
31d9d9b6 | 31 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
dd87eb3a | 32 | |
02725e74 | 33 | if (!desc) |
dd87eb3a | 34 | return -EINVAL; |
dd87eb3a TG |
35 | |
36 | if (!chip) | |
37 | chip = &no_irq_chip; | |
38 | ||
6b8ff312 | 39 | desc->irq_data.chip = chip; |
02725e74 | 40 | irq_put_desc_unlock(desc, flags); |
d72274e5 DD |
41 | /* |
42 | * For !CONFIG_SPARSE_IRQ make the irq show up in | |
43 | * allocated_irqs. For the CONFIG_SPARSE_IRQ case, it is | |
44 | * already marked, and this call is harmless. | |
45 | */ | |
46 | irq_reserve_irq(irq); | |
dd87eb3a TG |
47 | return 0; |
48 | } | |
a0cd9ca2 | 49 | EXPORT_SYMBOL(irq_set_chip); |
dd87eb3a TG |
50 | |
51 | /** | |
a0cd9ca2 | 52 | * irq_set_type - set the irq trigger type for an irq |
dd87eb3a | 53 | * @irq: irq number |
0c5d1eb7 | 54 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a | 55 | */ |
a0cd9ca2 | 56 | int irq_set_irq_type(unsigned int irq, unsigned int type) |
dd87eb3a | 57 | { |
dd87eb3a | 58 | unsigned long flags; |
31d9d9b6 | 59 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
02725e74 | 60 | int ret = 0; |
dd87eb3a | 61 | |
02725e74 TG |
62 | if (!desc) |
63 | return -EINVAL; | |
dd87eb3a | 64 | |
f2b662da | 65 | type &= IRQ_TYPE_SENSE_MASK; |
a09b659c | 66 | ret = __irq_set_trigger(desc, irq, type); |
02725e74 | 67 | irq_put_desc_busunlock(desc, flags); |
dd87eb3a TG |
68 | return ret; |
69 | } | |
a0cd9ca2 | 70 | EXPORT_SYMBOL(irq_set_irq_type); |
dd87eb3a TG |
71 | |
72 | /** | |
a0cd9ca2 | 73 | * irq_set_handler_data - set irq handler data for an irq |
dd87eb3a TG |
74 | * @irq: Interrupt number |
75 | * @data: Pointer to interrupt specific data | |
76 | * | |
77 | * Set the hardware irq controller data for an irq | |
78 | */ | |
a0cd9ca2 | 79 | int irq_set_handler_data(unsigned int irq, void *data) |
dd87eb3a | 80 | { |
dd87eb3a | 81 | unsigned long flags; |
31d9d9b6 | 82 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
dd87eb3a | 83 | |
02725e74 | 84 | if (!desc) |
dd87eb3a | 85 | return -EINVAL; |
6b8ff312 | 86 | desc->irq_data.handler_data = data; |
02725e74 | 87 | irq_put_desc_unlock(desc, flags); |
dd87eb3a TG |
88 | return 0; |
89 | } | |
a0cd9ca2 | 90 | EXPORT_SYMBOL(irq_set_handler_data); |
dd87eb3a | 91 | |
5b912c10 | 92 | /** |
51906e77 AG |
93 | * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset |
94 | * @irq_base: Interrupt number base | |
95 | * @irq_offset: Interrupt number offset | |
96 | * @entry: Pointer to MSI descriptor data | |
5b912c10 | 97 | * |
51906e77 | 98 | * Set the MSI descriptor entry for an irq at offset |
5b912c10 | 99 | */ |
51906e77 AG |
100 | int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, |
101 | struct msi_desc *entry) | |
5b912c10 | 102 | { |
5b912c10 | 103 | unsigned long flags; |
51906e77 | 104 | struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
5b912c10 | 105 | |
02725e74 | 106 | if (!desc) |
5b912c10 | 107 | return -EINVAL; |
6b8ff312 | 108 | desc->irq_data.msi_desc = entry; |
51906e77 AG |
109 | if (entry && !irq_offset) |
110 | entry->irq = irq_base; | |
02725e74 | 111 | irq_put_desc_unlock(desc, flags); |
5b912c10 EB |
112 | return 0; |
113 | } | |
114 | ||
51906e77 AG |
115 | /** |
116 | * irq_set_msi_desc - set MSI descriptor data for an irq | |
117 | * @irq: Interrupt number | |
118 | * @entry: Pointer to MSI descriptor data | |
119 | * | |
120 | * Set the MSI descriptor entry for an irq | |
121 | */ | |
122 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) | |
123 | { | |
124 | return irq_set_msi_desc_off(irq, 0, entry); | |
125 | } | |
126 | ||
dd87eb3a | 127 | /** |
a0cd9ca2 | 128 | * irq_set_chip_data - set irq chip data for an irq |
dd87eb3a TG |
129 | * @irq: Interrupt number |
130 | * @data: Pointer to chip specific data | |
131 | * | |
132 | * Set the hardware irq chip data for an irq | |
133 | */ | |
a0cd9ca2 | 134 | int irq_set_chip_data(unsigned int irq, void *data) |
dd87eb3a | 135 | { |
dd87eb3a | 136 | unsigned long flags; |
31d9d9b6 | 137 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
dd87eb3a | 138 | |
02725e74 | 139 | if (!desc) |
dd87eb3a | 140 | return -EINVAL; |
6b8ff312 | 141 | desc->irq_data.chip_data = data; |
02725e74 | 142 | irq_put_desc_unlock(desc, flags); |
dd87eb3a TG |
143 | return 0; |
144 | } | |
a0cd9ca2 | 145 | EXPORT_SYMBOL(irq_set_chip_data); |
dd87eb3a | 146 | |
f303a6dd TG |
147 | struct irq_data *irq_get_irq_data(unsigned int irq) |
148 | { | |
149 | struct irq_desc *desc = irq_to_desc(irq); | |
150 | ||
151 | return desc ? &desc->irq_data : NULL; | |
152 | } | |
153 | EXPORT_SYMBOL_GPL(irq_get_irq_data); | |
154 | ||
c1594b77 TG |
155 | static void irq_state_clr_disabled(struct irq_desc *desc) |
156 | { | |
801a0e9a | 157 | irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED); |
c1594b77 TG |
158 | } |
159 | ||
160 | static void irq_state_set_disabled(struct irq_desc *desc) | |
161 | { | |
801a0e9a | 162 | irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); |
c1594b77 TG |
163 | } |
164 | ||
6e40262e TG |
165 | static void irq_state_clr_masked(struct irq_desc *desc) |
166 | { | |
32f4125e | 167 | irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED); |
6e40262e TG |
168 | } |
169 | ||
170 | static void irq_state_set_masked(struct irq_desc *desc) | |
171 | { | |
32f4125e | 172 | irqd_set(&desc->irq_data, IRQD_IRQ_MASKED); |
6e40262e TG |
173 | } |
174 | ||
b4bc724e | 175 | int irq_startup(struct irq_desc *desc, bool resend) |
46999238 | 176 | { |
b4bc724e TG |
177 | int ret = 0; |
178 | ||
c1594b77 | 179 | irq_state_clr_disabled(desc); |
46999238 TG |
180 | desc->depth = 0; |
181 | ||
3aae994f | 182 | if (desc->irq_data.chip->irq_startup) { |
b4bc724e | 183 | ret = desc->irq_data.chip->irq_startup(&desc->irq_data); |
6e40262e | 184 | irq_state_clr_masked(desc); |
b4bc724e TG |
185 | } else { |
186 | irq_enable(desc); | |
3aae994f | 187 | } |
b4bc724e TG |
188 | if (resend) |
189 | check_irq_resend(desc, desc->irq_data.irq); | |
190 | return ret; | |
46999238 TG |
191 | } |
192 | ||
193 | void irq_shutdown(struct irq_desc *desc) | |
194 | { | |
c1594b77 | 195 | irq_state_set_disabled(desc); |
46999238 | 196 | desc->depth = 1; |
50f7c032 TG |
197 | if (desc->irq_data.chip->irq_shutdown) |
198 | desc->irq_data.chip->irq_shutdown(&desc->irq_data); | |
ed585a65 | 199 | else if (desc->irq_data.chip->irq_disable) |
50f7c032 TG |
200 | desc->irq_data.chip->irq_disable(&desc->irq_data); |
201 | else | |
202 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
6e40262e | 203 | irq_state_set_masked(desc); |
46999238 TG |
204 | } |
205 | ||
87923470 TG |
206 | void irq_enable(struct irq_desc *desc) |
207 | { | |
c1594b77 | 208 | irq_state_clr_disabled(desc); |
50f7c032 TG |
209 | if (desc->irq_data.chip->irq_enable) |
210 | desc->irq_data.chip->irq_enable(&desc->irq_data); | |
211 | else | |
212 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
6e40262e | 213 | irq_state_clr_masked(desc); |
dd87eb3a TG |
214 | } |
215 | ||
d671a605 | 216 | /** |
f788e7bf | 217 | * irq_disable - Mark interrupt disabled |
d671a605 AF |
218 | * @desc: irq descriptor which should be disabled |
219 | * | |
220 | * If the chip does not implement the irq_disable callback, we | |
221 | * use a lazy disable approach. That means we mark the interrupt | |
222 | * disabled, but leave the hardware unmasked. That's an | |
223 | * optimization because we avoid the hardware access for the | |
224 | * common case where no interrupt happens after we marked it | |
225 | * disabled. If an interrupt happens, then the interrupt flow | |
226 | * handler masks the line at the hardware level and marks it | |
227 | * pending. | |
228 | */ | |
50f7c032 | 229 | void irq_disable(struct irq_desc *desc) |
89d694b9 | 230 | { |
c1594b77 | 231 | irq_state_set_disabled(desc); |
50f7c032 TG |
232 | if (desc->irq_data.chip->irq_disable) { |
233 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
a61d8258 | 234 | irq_state_set_masked(desc); |
50f7c032 | 235 | } |
89d694b9 TG |
236 | } |
237 | ||
31d9d9b6 MZ |
238 | void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu) |
239 | { | |
240 | if (desc->irq_data.chip->irq_enable) | |
241 | desc->irq_data.chip->irq_enable(&desc->irq_data); | |
242 | else | |
243 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
244 | cpumask_set_cpu(cpu, desc->percpu_enabled); | |
245 | } | |
246 | ||
247 | void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu) | |
248 | { | |
249 | if (desc->irq_data.chip->irq_disable) | |
250 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
251 | else | |
252 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
253 | cpumask_clear_cpu(cpu, desc->percpu_enabled); | |
254 | } | |
255 | ||
9205e31d | 256 | static inline void mask_ack_irq(struct irq_desc *desc) |
dd87eb3a | 257 | { |
9205e31d TG |
258 | if (desc->irq_data.chip->irq_mask_ack) |
259 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | |
dd87eb3a | 260 | else { |
e2c0f8ff | 261 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
22a49163 TG |
262 | if (desc->irq_data.chip->irq_ack) |
263 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 264 | } |
6e40262e | 265 | irq_state_set_masked(desc); |
0b1adaa0 TG |
266 | } |
267 | ||
d4d5e089 | 268 | void mask_irq(struct irq_desc *desc) |
0b1adaa0 | 269 | { |
e2c0f8ff TG |
270 | if (desc->irq_data.chip->irq_mask) { |
271 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
6e40262e | 272 | irq_state_set_masked(desc); |
0b1adaa0 TG |
273 | } |
274 | } | |
275 | ||
d4d5e089 | 276 | void unmask_irq(struct irq_desc *desc) |
0b1adaa0 | 277 | { |
0eda58b7 TG |
278 | if (desc->irq_data.chip->irq_unmask) { |
279 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
6e40262e | 280 | irq_state_clr_masked(desc); |
0b1adaa0 | 281 | } |
dd87eb3a TG |
282 | } |
283 | ||
328a4978 TG |
284 | void unmask_threaded_irq(struct irq_desc *desc) |
285 | { | |
286 | struct irq_chip *chip = desc->irq_data.chip; | |
287 | ||
288 | if (chip->flags & IRQCHIP_EOI_THREADED) | |
289 | chip->irq_eoi(&desc->irq_data); | |
290 | ||
291 | if (chip->irq_unmask) { | |
292 | chip->irq_unmask(&desc->irq_data); | |
293 | irq_state_clr_masked(desc); | |
294 | } | |
295 | } | |
296 | ||
399b5da2 TG |
297 | /* |
298 | * handle_nested_irq - Handle a nested irq from a irq thread | |
299 | * @irq: the interrupt number | |
300 | * | |
301 | * Handle interrupts which are nested into a threaded interrupt | |
302 | * handler. The handler function is called inside the calling | |
303 | * threads context. | |
304 | */ | |
305 | void handle_nested_irq(unsigned int irq) | |
306 | { | |
307 | struct irq_desc *desc = irq_to_desc(irq); | |
308 | struct irqaction *action; | |
309 | irqreturn_t action_ret; | |
310 | ||
311 | might_sleep(); | |
312 | ||
239007b8 | 313 | raw_spin_lock_irq(&desc->lock); |
399b5da2 | 314 | |
293a7a0a | 315 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
399b5da2 TG |
316 | kstat_incr_irqs_this_cpu(irq, desc); |
317 | ||
318 | action = desc->action; | |
23812b9d NJ |
319 | if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) { |
320 | desc->istate |= IRQS_PENDING; | |
399b5da2 | 321 | goto out_unlock; |
23812b9d | 322 | } |
399b5da2 | 323 | |
32f4125e | 324 | irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
239007b8 | 325 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
326 | |
327 | action_ret = action->thread_fn(action->irq, action->dev_id); | |
328 | if (!noirqdebug) | |
329 | note_interrupt(irq, desc, action_ret); | |
330 | ||
239007b8 | 331 | raw_spin_lock_irq(&desc->lock); |
32f4125e | 332 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
399b5da2 TG |
333 | |
334 | out_unlock: | |
239007b8 | 335 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
336 | } |
337 | EXPORT_SYMBOL_GPL(handle_nested_irq); | |
338 | ||
fe200ae4 TG |
339 | static bool irq_check_poll(struct irq_desc *desc) |
340 | { | |
6954b75b | 341 | if (!(desc->istate & IRQS_POLL_INPROGRESS)) |
fe200ae4 TG |
342 | return false; |
343 | return irq_wait_for_poll(desc); | |
344 | } | |
345 | ||
dd87eb3a TG |
346 | /** |
347 | * handle_simple_irq - Simple and software-decoded IRQs. | |
348 | * @irq: the interrupt number | |
349 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
350 | * |
351 | * Simple interrupts are either sent from a demultiplexing interrupt | |
352 | * handler or come from hardware, where no interrupt hardware control | |
353 | * is necessary. | |
354 | * | |
355 | * Note: The caller is expected to handle the ack, clear, mask and | |
356 | * unmask issues if necessary. | |
357 | */ | |
7ad5b3a5 | 358 | void |
7d12e780 | 359 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 360 | { |
239007b8 | 361 | raw_spin_lock(&desc->lock); |
dd87eb3a | 362 | |
32f4125e | 363 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) |
fe200ae4 TG |
364 | if (!irq_check_poll(desc)) |
365 | goto out_unlock; | |
366 | ||
163ef309 | 367 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
d6c88a50 | 368 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a | 369 | |
23812b9d NJ |
370 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
371 | desc->istate |= IRQS_PENDING; | |
dd87eb3a | 372 | goto out_unlock; |
23812b9d | 373 | } |
dd87eb3a | 374 | |
107781e7 | 375 | handle_irq_event(desc); |
dd87eb3a | 376 | |
dd87eb3a | 377 | out_unlock: |
239007b8 | 378 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 379 | } |
edf76f83 | 380 | EXPORT_SYMBOL_GPL(handle_simple_irq); |
dd87eb3a | 381 | |
ac563761 TG |
382 | /* |
383 | * Called unconditionally from handle_level_irq() and only for oneshot | |
384 | * interrupts from handle_fasteoi_irq() | |
385 | */ | |
386 | static void cond_unmask_irq(struct irq_desc *desc) | |
387 | { | |
388 | /* | |
389 | * We need to unmask in the following cases: | |
390 | * - Standard level irq (IRQF_ONESHOT is not set) | |
391 | * - Oneshot irq which did not wake the thread (caused by a | |
392 | * spurious interrupt or a primary handler handling it | |
393 | * completely). | |
394 | */ | |
395 | if (!irqd_irq_disabled(&desc->irq_data) && | |
396 | irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) | |
397 | unmask_irq(desc); | |
398 | } | |
399 | ||
dd87eb3a TG |
400 | /** |
401 | * handle_level_irq - Level type irq handler | |
402 | * @irq: the interrupt number | |
403 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
404 | * |
405 | * Level type interrupts are active as long as the hardware line has | |
406 | * the active level. This may require to mask the interrupt and unmask | |
407 | * it after the associated handler has acknowledged the device, so the | |
408 | * interrupt line is back to inactive. | |
409 | */ | |
7ad5b3a5 | 410 | void |
7d12e780 | 411 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 412 | { |
239007b8 | 413 | raw_spin_lock(&desc->lock); |
9205e31d | 414 | mask_ack_irq(desc); |
dd87eb3a | 415 | |
32f4125e | 416 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) |
fe200ae4 TG |
417 | if (!irq_check_poll(desc)) |
418 | goto out_unlock; | |
419 | ||
163ef309 | 420 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
d6c88a50 | 421 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
422 | |
423 | /* | |
424 | * If its disabled or no action available | |
425 | * keep it masked and get out of here | |
426 | */ | |
d4dc0f90 TG |
427 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
428 | desc->istate |= IRQS_PENDING; | |
86998aa6 | 429 | goto out_unlock; |
d4dc0f90 | 430 | } |
dd87eb3a | 431 | |
1529866c | 432 | handle_irq_event(desc); |
b25c340c | 433 | |
ac563761 TG |
434 | cond_unmask_irq(desc); |
435 | ||
86998aa6 | 436 | out_unlock: |
239007b8 | 437 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 438 | } |
14819ea1 | 439 | EXPORT_SYMBOL_GPL(handle_level_irq); |
dd87eb3a | 440 | |
78129576 TG |
441 | #ifdef CONFIG_IRQ_PREFLOW_FASTEOI |
442 | static inline void preflow_handler(struct irq_desc *desc) | |
443 | { | |
444 | if (desc->preflow_handler) | |
445 | desc->preflow_handler(&desc->irq_data); | |
446 | } | |
447 | #else | |
448 | static inline void preflow_handler(struct irq_desc *desc) { } | |
449 | #endif | |
450 | ||
328a4978 TG |
451 | static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip) |
452 | { | |
453 | if (!(desc->istate & IRQS_ONESHOT)) { | |
454 | chip->irq_eoi(&desc->irq_data); | |
455 | return; | |
456 | } | |
457 | /* | |
458 | * We need to unmask in the following cases: | |
459 | * - Oneshot irq which did not wake the thread (caused by a | |
460 | * spurious interrupt or a primary handler handling it | |
461 | * completely). | |
462 | */ | |
463 | if (!irqd_irq_disabled(&desc->irq_data) && | |
464 | irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) { | |
465 | chip->irq_eoi(&desc->irq_data); | |
466 | unmask_irq(desc); | |
467 | } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) { | |
468 | chip->irq_eoi(&desc->irq_data); | |
469 | } | |
470 | } | |
471 | ||
dd87eb3a | 472 | /** |
47c2a3aa | 473 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
474 | * @irq: the interrupt number |
475 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 476 | * |
47c2a3aa | 477 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
478 | * call when the interrupt has been serviced. This enables support |
479 | * for modern forms of interrupt handlers, which handle the flow | |
480 | * details in hardware, transparently. | |
481 | */ | |
7ad5b3a5 | 482 | void |
7d12e780 | 483 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 484 | { |
328a4978 TG |
485 | struct irq_chip *chip = desc->irq_data.chip; |
486 | ||
239007b8 | 487 | raw_spin_lock(&desc->lock); |
dd87eb3a | 488 | |
32f4125e | 489 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) |
fe200ae4 TG |
490 | if (!irq_check_poll(desc)) |
491 | goto out; | |
dd87eb3a | 492 | |
163ef309 | 493 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
d6c88a50 | 494 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
495 | |
496 | /* | |
497 | * If its disabled or no action available | |
76d21601 | 498 | * then mask it and get out of here: |
dd87eb3a | 499 | */ |
32f4125e | 500 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
2a0d6fb3 | 501 | desc->istate |= IRQS_PENDING; |
e2c0f8ff | 502 | mask_irq(desc); |
dd87eb3a | 503 | goto out; |
98bb244b | 504 | } |
c69e3758 TG |
505 | |
506 | if (desc->istate & IRQS_ONESHOT) | |
507 | mask_irq(desc); | |
508 | ||
78129576 | 509 | preflow_handler(desc); |
a7ae4de5 | 510 | handle_irq_event(desc); |
77694b40 | 511 | |
328a4978 | 512 | cond_unmask_eoi_irq(desc, chip); |
ac563761 | 513 | |
239007b8 | 514 | raw_spin_unlock(&desc->lock); |
77694b40 TG |
515 | return; |
516 | out: | |
328a4978 TG |
517 | if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED)) |
518 | chip->irq_eoi(&desc->irq_data); | |
519 | raw_spin_unlock(&desc->lock); | |
dd87eb3a TG |
520 | } |
521 | ||
522 | /** | |
523 | * handle_edge_irq - edge type IRQ handler | |
524 | * @irq: the interrupt number | |
525 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
526 | * |
527 | * Interrupt occures on the falling and/or rising edge of a hardware | |
25985edc | 528 | * signal. The occurrence is latched into the irq controller hardware |
dd87eb3a TG |
529 | * and must be acked in order to be reenabled. After the ack another |
530 | * interrupt can happen on the same source even before the first one | |
dfff0615 | 531 | * is handled by the associated event handler. If this happens it |
dd87eb3a TG |
532 | * might be necessary to disable (mask) the interrupt depending on the |
533 | * controller hardware. This requires to reenable the interrupt inside | |
534 | * of the loop which handles the interrupts which have arrived while | |
535 | * the handler was running. If all pending interrupts are handled, the | |
536 | * loop is left. | |
537 | */ | |
7ad5b3a5 | 538 | void |
7d12e780 | 539 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 540 | { |
239007b8 | 541 | raw_spin_lock(&desc->lock); |
dd87eb3a | 542 | |
163ef309 | 543 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
dd87eb3a TG |
544 | /* |
545 | * If we're currently running this IRQ, or its disabled, | |
546 | * we shouldn't process the IRQ. Mark it pending, handle | |
547 | * the necessary masking and go out | |
548 | */ | |
32f4125e TG |
549 | if (unlikely(irqd_irq_disabled(&desc->irq_data) || |
550 | irqd_irq_inprogress(&desc->irq_data) || !desc->action)) { | |
fe200ae4 | 551 | if (!irq_check_poll(desc)) { |
2a0d6fb3 | 552 | desc->istate |= IRQS_PENDING; |
fe200ae4 TG |
553 | mask_ack_irq(desc); |
554 | goto out_unlock; | |
555 | } | |
dd87eb3a | 556 | } |
d6c88a50 | 557 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
558 | |
559 | /* Start handling the irq */ | |
22a49163 | 560 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
dd87eb3a | 561 | |
dd87eb3a | 562 | do { |
a60a5dc2 | 563 | if (unlikely(!desc->action)) { |
e2c0f8ff | 564 | mask_irq(desc); |
dd87eb3a TG |
565 | goto out_unlock; |
566 | } | |
567 | ||
568 | /* | |
569 | * When another irq arrived while we were handling | |
570 | * one, we could have masked the irq. | |
571 | * Renable it, if it was not disabled in meantime. | |
572 | */ | |
2a0d6fb3 | 573 | if (unlikely(desc->istate & IRQS_PENDING)) { |
32f4125e TG |
574 | if (!irqd_irq_disabled(&desc->irq_data) && |
575 | irqd_irq_masked(&desc->irq_data)) | |
c1594b77 | 576 | unmask_irq(desc); |
dd87eb3a TG |
577 | } |
578 | ||
a60a5dc2 | 579 | handle_irq_event(desc); |
dd87eb3a | 580 | |
2a0d6fb3 | 581 | } while ((desc->istate & IRQS_PENDING) && |
32f4125e | 582 | !irqd_irq_disabled(&desc->irq_data)); |
dd87eb3a | 583 | |
dd87eb3a | 584 | out_unlock: |
239007b8 | 585 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 586 | } |
3911ff30 | 587 | EXPORT_SYMBOL(handle_edge_irq); |
dd87eb3a | 588 | |
0521c8fb TG |
589 | #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER |
590 | /** | |
591 | * handle_edge_eoi_irq - edge eoi type IRQ handler | |
592 | * @irq: the interrupt number | |
593 | * @desc: the interrupt description structure for this irq | |
594 | * | |
595 | * Similar as the above handle_edge_irq, but using eoi and w/o the | |
596 | * mask/unmask logic. | |
597 | */ | |
598 | void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc) | |
599 | { | |
600 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
601 | ||
602 | raw_spin_lock(&desc->lock); | |
603 | ||
604 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | |
605 | /* | |
606 | * If we're currently running this IRQ, or its disabled, | |
607 | * we shouldn't process the IRQ. Mark it pending, handle | |
608 | * the necessary masking and go out | |
609 | */ | |
610 | if (unlikely(irqd_irq_disabled(&desc->irq_data) || | |
611 | irqd_irq_inprogress(&desc->irq_data) || !desc->action)) { | |
612 | if (!irq_check_poll(desc)) { | |
613 | desc->istate |= IRQS_PENDING; | |
614 | goto out_eoi; | |
615 | } | |
616 | } | |
617 | kstat_incr_irqs_this_cpu(irq, desc); | |
618 | ||
619 | do { | |
620 | if (unlikely(!desc->action)) | |
621 | goto out_eoi; | |
622 | ||
623 | handle_irq_event(desc); | |
624 | ||
625 | } while ((desc->istate & IRQS_PENDING) && | |
626 | !irqd_irq_disabled(&desc->irq_data)); | |
627 | ||
ac0e0447 | 628 | out_eoi: |
0521c8fb TG |
629 | chip->irq_eoi(&desc->irq_data); |
630 | raw_spin_unlock(&desc->lock); | |
631 | } | |
632 | #endif | |
633 | ||
dd87eb3a | 634 | /** |
24b26d42 | 635 | * handle_percpu_irq - Per CPU local irq handler |
dd87eb3a TG |
636 | * @irq: the interrupt number |
637 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
638 | * |
639 | * Per CPU interrupts on SMP machines without locking requirements | |
640 | */ | |
7ad5b3a5 | 641 | void |
7d12e780 | 642 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 643 | { |
35e857cb | 644 | struct irq_chip *chip = irq_desc_get_chip(desc); |
dd87eb3a | 645 | |
d6c88a50 | 646 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a | 647 | |
849f061c TG |
648 | if (chip->irq_ack) |
649 | chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 650 | |
849f061c | 651 | handle_irq_event_percpu(desc, desc->action); |
dd87eb3a | 652 | |
849f061c TG |
653 | if (chip->irq_eoi) |
654 | chip->irq_eoi(&desc->irq_data); | |
dd87eb3a TG |
655 | } |
656 | ||
31d9d9b6 MZ |
657 | /** |
658 | * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids | |
659 | * @irq: the interrupt number | |
660 | * @desc: the interrupt description structure for this irq | |
661 | * | |
662 | * Per CPU interrupts on SMP machines without locking requirements. Same as | |
663 | * handle_percpu_irq() above but with the following extras: | |
664 | * | |
665 | * action->percpu_dev_id is a pointer to percpu variables which | |
666 | * contain the real device id for the cpu on which this handler is | |
667 | * called | |
668 | */ | |
669 | void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc) | |
670 | { | |
671 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
672 | struct irqaction *action = desc->action; | |
673 | void *dev_id = __this_cpu_ptr(action->percpu_dev_id); | |
674 | irqreturn_t res; | |
675 | ||
676 | kstat_incr_irqs_this_cpu(irq, desc); | |
677 | ||
678 | if (chip->irq_ack) | |
679 | chip->irq_ack(&desc->irq_data); | |
680 | ||
681 | trace_irq_handler_entry(irq, action); | |
682 | res = action->handler(irq, dev_id); | |
683 | trace_irq_handler_exit(irq, action, res); | |
684 | ||
685 | if (chip->irq_eoi) | |
686 | chip->irq_eoi(&desc->irq_data); | |
687 | } | |
688 | ||
dd87eb3a | 689 | void |
3836ca08 | 690 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
a460e745 | 691 | const char *name) |
dd87eb3a | 692 | { |
dd87eb3a | 693 | unsigned long flags; |
31d9d9b6 | 694 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0); |
dd87eb3a | 695 | |
02725e74 | 696 | if (!desc) |
dd87eb3a | 697 | return; |
dd87eb3a | 698 | |
091738a2 | 699 | if (!handle) { |
dd87eb3a | 700 | handle = handle_bad_irq; |
091738a2 TG |
701 | } else { |
702 | if (WARN_ON(desc->irq_data.chip == &no_irq_chip)) | |
02725e74 | 703 | goto out; |
f8b5473f | 704 | } |
dd87eb3a | 705 | |
dd87eb3a TG |
706 | /* Uninstall? */ |
707 | if (handle == handle_bad_irq) { | |
6b8ff312 | 708 | if (desc->irq_data.chip != &no_irq_chip) |
9205e31d | 709 | mask_ack_irq(desc); |
801a0e9a | 710 | irq_state_set_disabled(desc); |
dd87eb3a TG |
711 | desc->depth = 1; |
712 | } | |
713 | desc->handle_irq = handle; | |
a460e745 | 714 | desc->name = name; |
dd87eb3a TG |
715 | |
716 | if (handle != handle_bad_irq && is_chained) { | |
1ccb4e61 TG |
717 | irq_settings_set_noprobe(desc); |
718 | irq_settings_set_norequest(desc); | |
7f1b1244 | 719 | irq_settings_set_nothread(desc); |
b4bc724e | 720 | irq_startup(desc, true); |
dd87eb3a | 721 | } |
02725e74 TG |
722 | out: |
723 | irq_put_desc_busunlock(desc, flags); | |
dd87eb3a | 724 | } |
3836ca08 | 725 | EXPORT_SYMBOL_GPL(__irq_set_handler); |
dd87eb3a TG |
726 | |
727 | void | |
3836ca08 | 728 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 | 729 | irq_flow_handler_t handle, const char *name) |
dd87eb3a | 730 | { |
35e857cb | 731 | irq_set_chip(irq, chip); |
3836ca08 | 732 | __irq_set_handler(irq, handle, 0, name); |
dd87eb3a | 733 | } |
b3ae66f2 | 734 | EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name); |
46f4f8f6 | 735 | |
44247184 | 736 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
46f4f8f6 | 737 | { |
46f4f8f6 | 738 | unsigned long flags; |
31d9d9b6 | 739 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
46f4f8f6 | 740 | |
44247184 | 741 | if (!desc) |
46f4f8f6 | 742 | return; |
a005677b TG |
743 | irq_settings_clr_and_set(desc, clr, set); |
744 | ||
876dbd4c | 745 | irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | |
e1ef8241 | 746 | IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); |
a005677b TG |
747 | if (irq_settings_has_no_balance_set(desc)) |
748 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | |
749 | if (irq_settings_is_per_cpu(desc)) | |
750 | irqd_set(&desc->irq_data, IRQD_PER_CPU); | |
e1ef8241 TG |
751 | if (irq_settings_can_move_pcntxt(desc)) |
752 | irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); | |
0ef5ca1e TG |
753 | if (irq_settings_is_level(desc)) |
754 | irqd_set(&desc->irq_data, IRQD_LEVEL); | |
a005677b | 755 | |
876dbd4c TG |
756 | irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); |
757 | ||
02725e74 | 758 | irq_put_desc_unlock(desc, flags); |
46f4f8f6 | 759 | } |
edf76f83 | 760 | EXPORT_SYMBOL_GPL(irq_modify_status); |
0fdb4b25 DD |
761 | |
762 | /** | |
763 | * irq_cpu_online - Invoke all irq_cpu_online functions. | |
764 | * | |
765 | * Iterate through all irqs and invoke the chip.irq_cpu_online() | |
766 | * for each. | |
767 | */ | |
768 | void irq_cpu_online(void) | |
769 | { | |
770 | struct irq_desc *desc; | |
771 | struct irq_chip *chip; | |
772 | unsigned long flags; | |
773 | unsigned int irq; | |
774 | ||
775 | for_each_active_irq(irq) { | |
776 | desc = irq_to_desc(irq); | |
777 | if (!desc) | |
778 | continue; | |
779 | ||
780 | raw_spin_lock_irqsave(&desc->lock, flags); | |
781 | ||
782 | chip = irq_data_get_irq_chip(&desc->irq_data); | |
b3d42232 TG |
783 | if (chip && chip->irq_cpu_online && |
784 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | |
32f4125e | 785 | !irqd_irq_disabled(&desc->irq_data))) |
0fdb4b25 DD |
786 | chip->irq_cpu_online(&desc->irq_data); |
787 | ||
788 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
789 | } | |
790 | } | |
791 | ||
792 | /** | |
793 | * irq_cpu_offline - Invoke all irq_cpu_offline functions. | |
794 | * | |
795 | * Iterate through all irqs and invoke the chip.irq_cpu_offline() | |
796 | * for each. | |
797 | */ | |
798 | void irq_cpu_offline(void) | |
799 | { | |
800 | struct irq_desc *desc; | |
801 | struct irq_chip *chip; | |
802 | unsigned long flags; | |
803 | unsigned int irq; | |
804 | ||
805 | for_each_active_irq(irq) { | |
806 | desc = irq_to_desc(irq); | |
807 | if (!desc) | |
808 | continue; | |
809 | ||
810 | raw_spin_lock_irqsave(&desc->lock, flags); | |
811 | ||
812 | chip = irq_data_get_irq_chip(&desc->irq_data); | |
b3d42232 TG |
813 | if (chip && chip->irq_cpu_offline && |
814 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | |
32f4125e | 815 | !irqd_irq_disabled(&desc->irq_data))) |
0fdb4b25 DD |
816 | chip->irq_cpu_offline(&desc->irq_data); |
817 | ||
818 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
819 | } | |
820 | } |