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CommitLineData
52a65ff5 1// SPDX-License-Identifier: GPL-2.0
dd87eb3a 2/*
dd87eb3a
TG
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
5 *
99bfce5d
TG
6 * This file contains the core interrupt handling code, for irq-chip based
7 * architectures. Detailed information is available in
8 * Documentation/core-api/genericirq.rst
dd87eb3a
TG
9 */
10
11#include <linux/irq.h>
7fe3730d 12#include <linux/msi.h>
dd87eb3a
TG
13#include <linux/module.h>
14#include <linux/interrupt.h>
15#include <linux/kernel_stat.h>
f8264e34 16#include <linux/irqdomain.h>
dd87eb3a 17
f069686e
SR
18#include <trace/events/irq.h>
19
dd87eb3a
TG
20#include "internals.h"
21
e509bd7d
MW
22static irqreturn_t bad_chained_irq(int irq, void *dev_id)
23{
24 WARN_ONCE(1, "Chained irq %d should not call an action\n", irq);
25 return IRQ_NONE;
26}
27
28/*
29 * Chained handlers should never call action on their IRQ. This default
30 * action will emit warning if such thing happens.
31 */
32struct irqaction chained_action = {
33 .handler = bad_chained_irq,
34};
35
dd87eb3a 36/**
a0cd9ca2 37 * irq_set_chip - set the irq chip for an irq
dd87eb3a
TG
38 * @irq: irq number
39 * @chip: pointer to irq chip description structure
40 */
a0cd9ca2 41int irq_set_chip(unsigned int irq, struct irq_chip *chip)
dd87eb3a 42{
dd87eb3a 43 unsigned long flags;
31d9d9b6 44 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 45
02725e74 46 if (!desc)
dd87eb3a 47 return -EINVAL;
dd87eb3a
TG
48
49 if (!chip)
50 chip = &no_irq_chip;
51
6b8ff312 52 desc->irq_data.chip = chip;
02725e74 53 irq_put_desc_unlock(desc, flags);
d72274e5
DD
54 /*
55 * For !CONFIG_SPARSE_IRQ make the irq show up in
f63b6a05 56 * allocated_irqs.
d72274e5 57 */
f63b6a05 58 irq_mark_irq(irq);
dd87eb3a
TG
59 return 0;
60}
a0cd9ca2 61EXPORT_SYMBOL(irq_set_chip);
dd87eb3a
TG
62
63/**
8c67d247 64 * irq_set_irq_type - set the irq trigger type for an irq
dd87eb3a 65 * @irq: irq number
0c5d1eb7 66 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
dd87eb3a 67 */
a0cd9ca2 68int irq_set_irq_type(unsigned int irq, unsigned int type)
dd87eb3a 69{
dd87eb3a 70 unsigned long flags;
31d9d9b6 71 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
02725e74 72 int ret = 0;
dd87eb3a 73
02725e74
TG
74 if (!desc)
75 return -EINVAL;
dd87eb3a 76
a1ff541a 77 ret = __irq_set_trigger(desc, type);
02725e74 78 irq_put_desc_busunlock(desc, flags);
dd87eb3a
TG
79 return ret;
80}
a0cd9ca2 81EXPORT_SYMBOL(irq_set_irq_type);
dd87eb3a
TG
82
83/**
a0cd9ca2 84 * irq_set_handler_data - set irq handler data for an irq
dd87eb3a
TG
85 * @irq: Interrupt number
86 * @data: Pointer to interrupt specific data
87 *
88 * Set the hardware irq controller data for an irq
89 */
a0cd9ca2 90int irq_set_handler_data(unsigned int irq, void *data)
dd87eb3a 91{
dd87eb3a 92 unsigned long flags;
31d9d9b6 93 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 94
02725e74 95 if (!desc)
dd87eb3a 96 return -EINVAL;
af7080e0 97 desc->irq_common_data.handler_data = data;
02725e74 98 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
99 return 0;
100}
a0cd9ca2 101EXPORT_SYMBOL(irq_set_handler_data);
dd87eb3a 102
5b912c10 103/**
51906e77
AG
104 * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset
105 * @irq_base: Interrupt number base
106 * @irq_offset: Interrupt number offset
107 * @entry: Pointer to MSI descriptor data
5b912c10 108 *
51906e77 109 * Set the MSI descriptor entry for an irq at offset
5b912c10 110 */
51906e77
AG
111int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
112 struct msi_desc *entry)
5b912c10 113{
5b912c10 114 unsigned long flags;
51906e77 115 struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
5b912c10 116
02725e74 117 if (!desc)
5b912c10 118 return -EINVAL;
b237721c 119 desc->irq_common_data.msi_desc = entry;
51906e77
AG
120 if (entry && !irq_offset)
121 entry->irq = irq_base;
02725e74 122 irq_put_desc_unlock(desc, flags);
5b912c10
EB
123 return 0;
124}
125
51906e77
AG
126/**
127 * irq_set_msi_desc - set MSI descriptor data for an irq
128 * @irq: Interrupt number
129 * @entry: Pointer to MSI descriptor data
130 *
131 * Set the MSI descriptor entry for an irq
132 */
133int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
134{
135 return irq_set_msi_desc_off(irq, 0, entry);
136}
137
dd87eb3a 138/**
a0cd9ca2 139 * irq_set_chip_data - set irq chip data for an irq
dd87eb3a
TG
140 * @irq: Interrupt number
141 * @data: Pointer to chip specific data
142 *
143 * Set the hardware irq chip data for an irq
144 */
a0cd9ca2 145int irq_set_chip_data(unsigned int irq, void *data)
dd87eb3a 146{
dd87eb3a 147 unsigned long flags;
31d9d9b6 148 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 149
02725e74 150 if (!desc)
dd87eb3a 151 return -EINVAL;
6b8ff312 152 desc->irq_data.chip_data = data;
02725e74 153 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
154 return 0;
155}
a0cd9ca2 156EXPORT_SYMBOL(irq_set_chip_data);
dd87eb3a 157
f303a6dd
TG
158struct irq_data *irq_get_irq_data(unsigned int irq)
159{
160 struct irq_desc *desc = irq_to_desc(irq);
161
162 return desc ? &desc->irq_data : NULL;
163}
164EXPORT_SYMBOL_GPL(irq_get_irq_data);
165
c1594b77
TG
166static void irq_state_clr_disabled(struct irq_desc *desc)
167{
801a0e9a 168 irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
169}
170
6e40262e
TG
171static void irq_state_clr_masked(struct irq_desc *desc)
172{
32f4125e 173 irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
174}
175
201d7f47
TG
176static void irq_state_clr_started(struct irq_desc *desc)
177{
178 irqd_clear(&desc->irq_data, IRQD_IRQ_STARTED);
179}
180
181static void irq_state_set_started(struct irq_desc *desc)
182{
183 irqd_set(&desc->irq_data, IRQD_IRQ_STARTED);
184}
185
761ea388
TG
186enum {
187 IRQ_STARTUP_NORMAL,
188 IRQ_STARTUP_MANAGED,
189 IRQ_STARTUP_ABORT,
190};
191
192#ifdef CONFIG_SMP
193static int
194__irq_startup_managed(struct irq_desc *desc, struct cpumask *aff, bool force)
195{
196 struct irq_data *d = irq_desc_get_irq_data(desc);
197
198 if (!irqd_affinity_is_managed(d))
199 return IRQ_STARTUP_NORMAL;
200
201 irqd_clr_managed_shutdown(d);
202
9cb067ef 203 if (cpumask_any_and(aff, cpu_online_mask) >= nr_cpu_ids) {
761ea388
TG
204 /*
205 * Catch code which fiddles with enable_irq() on a managed
206 * and potentially shutdown IRQ. Chained interrupt
207 * installment or irq auto probing should not happen on
c942cee4 208 * managed irqs either.
761ea388
TG
209 */
210 if (WARN_ON_ONCE(force))
c942cee4 211 return IRQ_STARTUP_ABORT;
761ea388
TG
212 /*
213 * The interrupt was requested, but there is no online CPU
214 * in it's affinity mask. Put it into managed shutdown
215 * state and let the cpu hotplug mechanism start it up once
216 * a CPU in the mask becomes available.
217 */
761ea388
TG
218 return IRQ_STARTUP_ABORT;
219 }
bb9b428a
TG
220 /*
221 * Managed interrupts have reserved resources, so this should not
222 * happen.
223 */
42e1cc2d 224 if (WARN_ON(irq_domain_activate_irq(d, false)))
bb9b428a 225 return IRQ_STARTUP_ABORT;
761ea388
TG
226 return IRQ_STARTUP_MANAGED;
227}
228#else
2372a519 229static __always_inline int
761ea388
TG
230__irq_startup_managed(struct irq_desc *desc, struct cpumask *aff, bool force)
231{
232 return IRQ_STARTUP_NORMAL;
233}
234#endif
235
708d174b
TG
236static int __irq_startup(struct irq_desc *desc)
237{
238 struct irq_data *d = irq_desc_get_irq_data(desc);
239 int ret = 0;
240
c942cee4
TG
241 /* Warn if this interrupt is not activated but try nevertheless */
242 WARN_ON_ONCE(!irqd_is_activated(d));
243
708d174b
TG
244 if (d->chip->irq_startup) {
245 ret = d->chip->irq_startup(d);
246 irq_state_clr_disabled(desc);
247 irq_state_clr_masked(desc);
248 } else {
249 irq_enable(desc);
250 }
251 irq_state_set_started(desc);
252 return ret;
253}
254
4cde9c6b 255int irq_startup(struct irq_desc *desc, bool resend, bool force)
46999238 256{
761ea388
TG
257 struct irq_data *d = irq_desc_get_irq_data(desc);
258 struct cpumask *aff = irq_data_get_affinity_mask(d);
b4bc724e
TG
259 int ret = 0;
260
46999238
TG
261 desc->depth = 0;
262
761ea388 263 if (irqd_is_started(d)) {
b4bc724e 264 irq_enable(desc);
201d7f47 265 } else {
761ea388
TG
266 switch (__irq_startup_managed(desc, aff, force)) {
267 case IRQ_STARTUP_NORMAL:
268 ret = __irq_startup(desc);
269 irq_setup_affinity(desc);
270 break;
271 case IRQ_STARTUP_MANAGED:
e43b3b58 272 irq_do_set_affinity(d, aff, false);
761ea388 273 ret = __irq_startup(desc);
761ea388
TG
274 break;
275 case IRQ_STARTUP_ABORT:
c942cee4 276 irqd_set_managed_shutdown(d);
761ea388
TG
277 return 0;
278 }
3aae994f 279 }
b4bc724e 280 if (resend)
acd26bcf 281 check_irq_resend(desc, false);
201d7f47 282
b4bc724e 283 return ret;
46999238
TG
284}
285
c942cee4
TG
286int irq_activate(struct irq_desc *desc)
287{
288 struct irq_data *d = irq_desc_get_irq_data(desc);
289
290 if (!irqd_affinity_is_managed(d))
42e1cc2d 291 return irq_domain_activate_irq(d, false);
c942cee4
TG
292 return 0;
293}
294
1beaeacd 295int irq_activate_and_startup(struct irq_desc *desc, bool resend)
c942cee4
TG
296{
297 if (WARN_ON(irq_activate(desc)))
1beaeacd
TG
298 return 0;
299 return irq_startup(desc, resend, IRQ_START_FORCE);
c942cee4
TG
300}
301
201d7f47
TG
302static void __irq_disable(struct irq_desc *desc, bool mask);
303
46999238
TG
304void irq_shutdown(struct irq_desc *desc)
305{
201d7f47
TG
306 if (irqd_is_started(&desc->irq_data)) {
307 desc->depth = 1;
308 if (desc->irq_data.chip->irq_shutdown) {
309 desc->irq_data.chip->irq_shutdown(&desc->irq_data);
310 irq_state_set_disabled(desc);
311 irq_state_set_masked(desc);
312 } else {
313 __irq_disable(desc, true);
314 }
315 irq_state_clr_started(desc);
316 }
4001d8e8
TG
317}
318
319
320void irq_shutdown_and_deactivate(struct irq_desc *desc)
321{
322 irq_shutdown(desc);
201d7f47
TG
323 /*
324 * This must be called even if the interrupt was never started up,
325 * because the activation can happen before the interrupt is
326 * available for request/startup. It has it's own state tracking so
327 * it's safe to call it unconditionally.
328 */
f8264e34 329 irq_domain_deactivate_irq(&desc->irq_data);
46999238
TG
330}
331
87923470
TG
332void irq_enable(struct irq_desc *desc)
333{
bf22ff45
JC
334 if (!irqd_irq_disabled(&desc->irq_data)) {
335 unmask_irq(desc);
336 } else {
337 irq_state_clr_disabled(desc);
338 if (desc->irq_data.chip->irq_enable) {
339 desc->irq_data.chip->irq_enable(&desc->irq_data);
340 irq_state_clr_masked(desc);
341 } else {
342 unmask_irq(desc);
343 }
344 }
dd87eb3a
TG
345}
346
201d7f47
TG
347static void __irq_disable(struct irq_desc *desc, bool mask)
348{
bf22ff45
JC
349 if (irqd_irq_disabled(&desc->irq_data)) {
350 if (mask)
351 mask_irq(desc);
352 } else {
353 irq_state_set_disabled(desc);
354 if (desc->irq_data.chip->irq_disable) {
355 desc->irq_data.chip->irq_disable(&desc->irq_data);
356 irq_state_set_masked(desc);
357 } else if (mask) {
358 mask_irq(desc);
359 }
201d7f47
TG
360 }
361}
362
d671a605 363/**
f788e7bf 364 * irq_disable - Mark interrupt disabled
d671a605
AF
365 * @desc: irq descriptor which should be disabled
366 *
367 * If the chip does not implement the irq_disable callback, we
368 * use a lazy disable approach. That means we mark the interrupt
369 * disabled, but leave the hardware unmasked. That's an
370 * optimization because we avoid the hardware access for the
371 * common case where no interrupt happens after we marked it
372 * disabled. If an interrupt happens, then the interrupt flow
373 * handler masks the line at the hardware level and marks it
374 * pending.
e9849777
TG
375 *
376 * If the interrupt chip does not implement the irq_disable callback,
377 * a driver can disable the lazy approach for a particular irq line by
378 * calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can
379 * be used for devices which cannot disable the interrupt at the
380 * device level under certain circumstances and have to use
381 * disable_irq[_nosync] instead.
d671a605 382 */
50f7c032 383void irq_disable(struct irq_desc *desc)
89d694b9 384{
201d7f47 385 __irq_disable(desc, irq_settings_disable_unlazy(desc));
89d694b9
TG
386}
387
31d9d9b6
MZ
388void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu)
389{
390 if (desc->irq_data.chip->irq_enable)
391 desc->irq_data.chip->irq_enable(&desc->irq_data);
392 else
393 desc->irq_data.chip->irq_unmask(&desc->irq_data);
394 cpumask_set_cpu(cpu, desc->percpu_enabled);
395}
396
397void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu)
398{
399 if (desc->irq_data.chip->irq_disable)
400 desc->irq_data.chip->irq_disable(&desc->irq_data);
401 else
402 desc->irq_data.chip->irq_mask(&desc->irq_data);
403 cpumask_clear_cpu(cpu, desc->percpu_enabled);
404}
405
9205e31d 406static inline void mask_ack_irq(struct irq_desc *desc)
dd87eb3a 407{
bf22ff45 408 if (desc->irq_data.chip->irq_mask_ack) {
9205e31d 409 desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
bf22ff45
JC
410 irq_state_set_masked(desc);
411 } else {
412 mask_irq(desc);
22a49163
TG
413 if (desc->irq_data.chip->irq_ack)
414 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 415 }
0b1adaa0
TG
416}
417
d4d5e089 418void mask_irq(struct irq_desc *desc)
0b1adaa0 419{
bf22ff45
JC
420 if (irqd_irq_masked(&desc->irq_data))
421 return;
422
e2c0f8ff
TG
423 if (desc->irq_data.chip->irq_mask) {
424 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 425 irq_state_set_masked(desc);
0b1adaa0
TG
426 }
427}
428
d4d5e089 429void unmask_irq(struct irq_desc *desc)
0b1adaa0 430{
bf22ff45
JC
431 if (!irqd_irq_masked(&desc->irq_data))
432 return;
433
0eda58b7
TG
434 if (desc->irq_data.chip->irq_unmask) {
435 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 436 irq_state_clr_masked(desc);
0b1adaa0 437 }
dd87eb3a
TG
438}
439
328a4978
TG
440void unmask_threaded_irq(struct irq_desc *desc)
441{
442 struct irq_chip *chip = desc->irq_data.chip;
443
444 if (chip->flags & IRQCHIP_EOI_THREADED)
445 chip->irq_eoi(&desc->irq_data);
446
bf22ff45 447 unmask_irq(desc);
328a4978
TG
448}
449
399b5da2
TG
450/*
451 * handle_nested_irq - Handle a nested irq from a irq thread
452 * @irq: the interrupt number
453 *
454 * Handle interrupts which are nested into a threaded interrupt
455 * handler. The handler function is called inside the calling
456 * threads context.
457 */
458void handle_nested_irq(unsigned int irq)
459{
460 struct irq_desc *desc = irq_to_desc(irq);
461 struct irqaction *action;
462 irqreturn_t action_ret;
463
464 might_sleep();
465
239007b8 466 raw_spin_lock_irq(&desc->lock);
399b5da2 467
293a7a0a 468 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
399b5da2
TG
469
470 action = desc->action;
23812b9d
NJ
471 if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) {
472 desc->istate |= IRQS_PENDING;
399b5da2 473 goto out_unlock;
23812b9d 474 }
399b5da2 475
a946e8c7 476 kstat_incr_irqs_this_cpu(desc);
32f4125e 477 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
239007b8 478 raw_spin_unlock_irq(&desc->lock);
399b5da2 479
45e52022
CK
480 action_ret = IRQ_NONE;
481 for_each_action_of_desc(desc, action)
482 action_ret |= action->thread_fn(action->irq, action->dev_id);
483
399b5da2 484 if (!noirqdebug)
0dcdbc97 485 note_interrupt(desc, action_ret);
399b5da2 486
239007b8 487 raw_spin_lock_irq(&desc->lock);
32f4125e 488 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
399b5da2
TG
489
490out_unlock:
239007b8 491 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
492}
493EXPORT_SYMBOL_GPL(handle_nested_irq);
494
fe200ae4
TG
495static bool irq_check_poll(struct irq_desc *desc)
496{
6954b75b 497 if (!(desc->istate & IRQS_POLL_INPROGRESS))
fe200ae4
TG
498 return false;
499 return irq_wait_for_poll(desc);
500}
501
c7bd3ec0
TG
502static bool irq_may_run(struct irq_desc *desc)
503{
9ce7a258
TG
504 unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED;
505
506 /*
507 * If the interrupt is not in progress and is not an armed
508 * wakeup interrupt, proceed.
509 */
510 if (!irqd_has_set(&desc->irq_data, mask))
c7bd3ec0 511 return true;
9ce7a258
TG
512
513 /*
514 * If the interrupt is an armed wakeup source, mark it pending
515 * and suspended, disable it and notify the pm core about the
516 * event.
517 */
518 if (irq_pm_check_wakeup(desc))
519 return false;
520
521 /*
522 * Handle a potential concurrent poll on a different core.
523 */
c7bd3ec0
TG
524 return irq_check_poll(desc);
525}
526
dd87eb3a
TG
527/**
528 * handle_simple_irq - Simple and software-decoded IRQs.
dd87eb3a 529 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
530 *
531 * Simple interrupts are either sent from a demultiplexing interrupt
532 * handler or come from hardware, where no interrupt hardware control
533 * is necessary.
534 *
535 * Note: The caller is expected to handle the ack, clear, mask and
536 * unmask issues if necessary.
537 */
bd0b9ac4 538void handle_simple_irq(struct irq_desc *desc)
dd87eb3a 539{
239007b8 540 raw_spin_lock(&desc->lock);
dd87eb3a 541
c7bd3ec0
TG
542 if (!irq_may_run(desc))
543 goto out_unlock;
fe200ae4 544
163ef309 545 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a 546
23812b9d
NJ
547 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
548 desc->istate |= IRQS_PENDING;
dd87eb3a 549 goto out_unlock;
23812b9d 550 }
dd87eb3a 551
a946e8c7 552 kstat_incr_irqs_this_cpu(desc);
107781e7 553 handle_irq_event(desc);
dd87eb3a 554
dd87eb3a 555out_unlock:
239007b8 556 raw_spin_unlock(&desc->lock);
dd87eb3a 557}
edf76f83 558EXPORT_SYMBOL_GPL(handle_simple_irq);
dd87eb3a 559
edd14cfe
KB
560/**
561 * handle_untracked_irq - Simple and software-decoded IRQs.
562 * @desc: the interrupt description structure for this irq
563 *
564 * Untracked interrupts are sent from a demultiplexing interrupt
565 * handler when the demultiplexer does not know which device it its
566 * multiplexed irq domain generated the interrupt. IRQ's handled
567 * through here are not subjected to stats tracking, randomness, or
568 * spurious interrupt detection.
569 *
570 * Note: Like handle_simple_irq, the caller is expected to handle
571 * the ack, clear, mask and unmask issues if necessary.
572 */
573void handle_untracked_irq(struct irq_desc *desc)
574{
575 unsigned int flags = 0;
576
577 raw_spin_lock(&desc->lock);
578
579 if (!irq_may_run(desc))
580 goto out_unlock;
581
582 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
583
584 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
585 desc->istate |= IRQS_PENDING;
586 goto out_unlock;
587 }
588
589 desc->istate &= ~IRQS_PENDING;
590 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
591 raw_spin_unlock(&desc->lock);
592
593 __handle_irq_event_percpu(desc, &flags);
594
595 raw_spin_lock(&desc->lock);
596 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
597
598out_unlock:
599 raw_spin_unlock(&desc->lock);
600}
601EXPORT_SYMBOL_GPL(handle_untracked_irq);
602
ac563761
TG
603/*
604 * Called unconditionally from handle_level_irq() and only for oneshot
605 * interrupts from handle_fasteoi_irq()
606 */
607static void cond_unmask_irq(struct irq_desc *desc)
608{
609 /*
610 * We need to unmask in the following cases:
611 * - Standard level irq (IRQF_ONESHOT is not set)
612 * - Oneshot irq which did not wake the thread (caused by a
613 * spurious interrupt or a primary handler handling it
614 * completely).
615 */
616 if (!irqd_irq_disabled(&desc->irq_data) &&
617 irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot)
618 unmask_irq(desc);
619}
620
dd87eb3a
TG
621/**
622 * handle_level_irq - Level type irq handler
dd87eb3a 623 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
624 *
625 * Level type interrupts are active as long as the hardware line has
626 * the active level. This may require to mask the interrupt and unmask
627 * it after the associated handler has acknowledged the device, so the
628 * interrupt line is back to inactive.
629 */
bd0b9ac4 630void handle_level_irq(struct irq_desc *desc)
dd87eb3a 631{
239007b8 632 raw_spin_lock(&desc->lock);
9205e31d 633 mask_ack_irq(desc);
dd87eb3a 634
c7bd3ec0
TG
635 if (!irq_may_run(desc))
636 goto out_unlock;
fe200ae4 637
163ef309 638 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
639
640 /*
641 * If its disabled or no action available
642 * keep it masked and get out of here
643 */
d4dc0f90
TG
644 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
645 desc->istate |= IRQS_PENDING;
86998aa6 646 goto out_unlock;
d4dc0f90 647 }
dd87eb3a 648
a946e8c7 649 kstat_incr_irqs_this_cpu(desc);
1529866c 650 handle_irq_event(desc);
b25c340c 651
ac563761
TG
652 cond_unmask_irq(desc);
653
86998aa6 654out_unlock:
239007b8 655 raw_spin_unlock(&desc->lock);
dd87eb3a 656}
14819ea1 657EXPORT_SYMBOL_GPL(handle_level_irq);
dd87eb3a 658
328a4978
TG
659static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
660{
661 if (!(desc->istate & IRQS_ONESHOT)) {
662 chip->irq_eoi(&desc->irq_data);
663 return;
664 }
665 /*
666 * We need to unmask in the following cases:
667 * - Oneshot irq which did not wake the thread (caused by a
668 * spurious interrupt or a primary handler handling it
669 * completely).
670 */
671 if (!irqd_irq_disabled(&desc->irq_data) &&
672 irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) {
673 chip->irq_eoi(&desc->irq_data);
674 unmask_irq(desc);
675 } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) {
676 chip->irq_eoi(&desc->irq_data);
677 }
678}
679
dd87eb3a 680/**
47c2a3aa 681 * handle_fasteoi_irq - irq handler for transparent controllers
dd87eb3a 682 * @desc: the interrupt description structure for this irq
dd87eb3a 683 *
47c2a3aa 684 * Only a single callback will be issued to the chip: an ->eoi()
dd87eb3a
TG
685 * call when the interrupt has been serviced. This enables support
686 * for modern forms of interrupt handlers, which handle the flow
687 * details in hardware, transparently.
688 */
bd0b9ac4 689void handle_fasteoi_irq(struct irq_desc *desc)
dd87eb3a 690{
328a4978
TG
691 struct irq_chip *chip = desc->irq_data.chip;
692
239007b8 693 raw_spin_lock(&desc->lock);
dd87eb3a 694
c7bd3ec0
TG
695 if (!irq_may_run(desc))
696 goto out;
dd87eb3a 697
163ef309 698 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
699
700 /*
701 * If its disabled or no action available
76d21601 702 * then mask it and get out of here:
dd87eb3a 703 */
32f4125e 704 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
2a0d6fb3 705 desc->istate |= IRQS_PENDING;
e2c0f8ff 706 mask_irq(desc);
dd87eb3a 707 goto out;
98bb244b 708 }
c69e3758 709
a946e8c7 710 kstat_incr_irqs_this_cpu(desc);
c69e3758
TG
711 if (desc->istate & IRQS_ONESHOT)
712 mask_irq(desc);
713
a7ae4de5 714 handle_irq_event(desc);
77694b40 715
328a4978 716 cond_unmask_eoi_irq(desc, chip);
ac563761 717
239007b8 718 raw_spin_unlock(&desc->lock);
77694b40
TG
719 return;
720out:
328a4978
TG
721 if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
722 chip->irq_eoi(&desc->irq_data);
723 raw_spin_unlock(&desc->lock);
dd87eb3a 724}
7cad45ee 725EXPORT_SYMBOL_GPL(handle_fasteoi_irq);
dd87eb3a 726
2dcf1fbc
JT
727/**
728 * handle_fasteoi_nmi - irq handler for NMI interrupt lines
729 * @desc: the interrupt description structure for this irq
730 *
731 * A simple NMI-safe handler, considering the restrictions
732 * from request_nmi.
733 *
734 * Only a single callback will be issued to the chip: an ->eoi()
735 * call when the interrupt has been serviced. This enables support
736 * for modern forms of interrupt handlers, which handle the flow
737 * details in hardware, transparently.
738 */
739void handle_fasteoi_nmi(struct irq_desc *desc)
740{
741 struct irq_chip *chip = irq_desc_get_chip(desc);
742 struct irqaction *action = desc->action;
743 unsigned int irq = irq_desc_get_irq(desc);
744 irqreturn_t res;
745
c09cb129
ST
746 __kstat_incr_irqs_this_cpu(desc);
747
2dcf1fbc
JT
748 trace_irq_handler_entry(irq, action);
749 /*
750 * NMIs cannot be shared, there is only one action.
751 */
752 res = action->handler(irq, action->dev_id);
753 trace_irq_handler_exit(irq, action, res);
754
755 if (chip->irq_eoi)
756 chip->irq_eoi(&desc->irq_data);
757}
758EXPORT_SYMBOL_GPL(handle_fasteoi_nmi);
759
dd87eb3a
TG
760/**
761 * handle_edge_irq - edge type IRQ handler
dd87eb3a 762 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
763 *
764 * Interrupt occures on the falling and/or rising edge of a hardware
25985edc 765 * signal. The occurrence is latched into the irq controller hardware
dd87eb3a
TG
766 * and must be acked in order to be reenabled. After the ack another
767 * interrupt can happen on the same source even before the first one
dfff0615 768 * is handled by the associated event handler. If this happens it
dd87eb3a
TG
769 * might be necessary to disable (mask) the interrupt depending on the
770 * controller hardware. This requires to reenable the interrupt inside
771 * of the loop which handles the interrupts which have arrived while
772 * the handler was running. If all pending interrupts are handled, the
773 * loop is left.
774 */
bd0b9ac4 775void handle_edge_irq(struct irq_desc *desc)
dd87eb3a 776{
239007b8 777 raw_spin_lock(&desc->lock);
dd87eb3a 778
163ef309 779 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
c3d7acd0 780
c7bd3ec0
TG
781 if (!irq_may_run(desc)) {
782 desc->istate |= IRQS_PENDING;
783 mask_ack_irq(desc);
784 goto out_unlock;
dd87eb3a 785 }
c3d7acd0 786
dd87eb3a 787 /*
c3d7acd0
TG
788 * If its disabled or no action available then mask it and get
789 * out of here.
dd87eb3a 790 */
c3d7acd0
TG
791 if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
792 desc->istate |= IRQS_PENDING;
793 mask_ack_irq(desc);
794 goto out_unlock;
dd87eb3a 795 }
c3d7acd0 796
b51bf95c 797 kstat_incr_irqs_this_cpu(desc);
dd87eb3a
TG
798
799 /* Start handling the irq */
22a49163 800 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 801
dd87eb3a 802 do {
a60a5dc2 803 if (unlikely(!desc->action)) {
e2c0f8ff 804 mask_irq(desc);
dd87eb3a
TG
805 goto out_unlock;
806 }
807
808 /*
809 * When another irq arrived while we were handling
810 * one, we could have masked the irq.
811 * Renable it, if it was not disabled in meantime.
812 */
2a0d6fb3 813 if (unlikely(desc->istate & IRQS_PENDING)) {
32f4125e
TG
814 if (!irqd_irq_disabled(&desc->irq_data) &&
815 irqd_irq_masked(&desc->irq_data))
c1594b77 816 unmask_irq(desc);
dd87eb3a
TG
817 }
818
a60a5dc2 819 handle_irq_event(desc);
dd87eb3a 820
2a0d6fb3 821 } while ((desc->istate & IRQS_PENDING) &&
32f4125e 822 !irqd_irq_disabled(&desc->irq_data));
dd87eb3a 823
dd87eb3a 824out_unlock:
239007b8 825 raw_spin_unlock(&desc->lock);
dd87eb3a 826}
3911ff30 827EXPORT_SYMBOL(handle_edge_irq);
dd87eb3a 828
0521c8fb
TG
829#ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
830/**
831 * handle_edge_eoi_irq - edge eoi type IRQ handler
0521c8fb
TG
832 * @desc: the interrupt description structure for this irq
833 *
834 * Similar as the above handle_edge_irq, but using eoi and w/o the
835 * mask/unmask logic.
836 */
bd0b9ac4 837void handle_edge_eoi_irq(struct irq_desc *desc)
0521c8fb
TG
838{
839 struct irq_chip *chip = irq_desc_get_chip(desc);
840
841 raw_spin_lock(&desc->lock);
842
843 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
c3d7acd0 844
c7bd3ec0
TG
845 if (!irq_may_run(desc)) {
846 desc->istate |= IRQS_PENDING;
847 goto out_eoi;
0521c8fb 848 }
c3d7acd0 849
0521c8fb 850 /*
c3d7acd0
TG
851 * If its disabled or no action available then mask it and get
852 * out of here.
0521c8fb 853 */
c3d7acd0
TG
854 if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
855 desc->istate |= IRQS_PENDING;
856 goto out_eoi;
0521c8fb 857 }
c3d7acd0 858
b51bf95c 859 kstat_incr_irqs_this_cpu(desc);
0521c8fb
TG
860
861 do {
862 if (unlikely(!desc->action))
863 goto out_eoi;
864
865 handle_irq_event(desc);
866
867 } while ((desc->istate & IRQS_PENDING) &&
868 !irqd_irq_disabled(&desc->irq_data));
869
ac0e0447 870out_eoi:
0521c8fb
TG
871 chip->irq_eoi(&desc->irq_data);
872 raw_spin_unlock(&desc->lock);
873}
874#endif
875
dd87eb3a 876/**
24b26d42 877 * handle_percpu_irq - Per CPU local irq handler
dd87eb3a 878 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
879 *
880 * Per CPU interrupts on SMP machines without locking requirements
881 */
bd0b9ac4 882void handle_percpu_irq(struct irq_desc *desc)
dd87eb3a 883{
35e857cb 884 struct irq_chip *chip = irq_desc_get_chip(desc);
dd87eb3a 885
1136b072
TG
886 /*
887 * PER CPU interrupts are not serialized. Do not touch
888 * desc->tot_count.
889 */
890 __kstat_incr_irqs_this_cpu(desc);
dd87eb3a 891
849f061c
TG
892 if (chip->irq_ack)
893 chip->irq_ack(&desc->irq_data);
dd87eb3a 894
71f64340 895 handle_irq_event_percpu(desc);
dd87eb3a 896
849f061c
TG
897 if (chip->irq_eoi)
898 chip->irq_eoi(&desc->irq_data);
dd87eb3a
TG
899}
900
31d9d9b6
MZ
901/**
902 * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
31d9d9b6
MZ
903 * @desc: the interrupt description structure for this irq
904 *
905 * Per CPU interrupts on SMP machines without locking requirements. Same as
906 * handle_percpu_irq() above but with the following extras:
907 *
908 * action->percpu_dev_id is a pointer to percpu variables which
909 * contain the real device id for the cpu on which this handler is
910 * called
911 */
bd0b9ac4 912void handle_percpu_devid_irq(struct irq_desc *desc)
31d9d9b6
MZ
913{
914 struct irq_chip *chip = irq_desc_get_chip(desc);
915 struct irqaction *action = desc->action;
bd0b9ac4 916 unsigned int irq = irq_desc_get_irq(desc);
31d9d9b6
MZ
917 irqreturn_t res;
918
1136b072
TG
919 /*
920 * PER CPU interrupts are not serialized. Do not touch
921 * desc->tot_count.
922 */
923 __kstat_incr_irqs_this_cpu(desc);
31d9d9b6
MZ
924
925 if (chip->irq_ack)
926 chip->irq_ack(&desc->irq_data);
927
fc590c22
TG
928 if (likely(action)) {
929 trace_irq_handler_entry(irq, action);
930 res = action->handler(irq, raw_cpu_ptr(action->percpu_dev_id));
931 trace_irq_handler_exit(irq, action, res);
932 } else {
933 unsigned int cpu = smp_processor_id();
934 bool enabled = cpumask_test_cpu(cpu, desc->percpu_enabled);
935
936 if (enabled)
937 irq_percpu_disable(desc, cpu);
938
939 pr_err_once("Spurious%s percpu IRQ%u on CPU%u\n",
940 enabled ? " and unmasked" : "", irq, cpu);
941 }
31d9d9b6
MZ
942
943 if (chip->irq_eoi)
944 chip->irq_eoi(&desc->irq_data);
945}
946
2dcf1fbc
JT
947/**
948 * handle_percpu_devid_fasteoi_nmi - Per CPU local NMI handler with per cpu
949 * dev ids
950 * @desc: the interrupt description structure for this irq
951 *
952 * Similar to handle_fasteoi_nmi, but handling the dev_id cookie
953 * as a percpu pointer.
954 */
955void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc)
956{
957 struct irq_chip *chip = irq_desc_get_chip(desc);
958 struct irqaction *action = desc->action;
959 unsigned int irq = irq_desc_get_irq(desc);
960 irqreturn_t res;
961
c09cb129
ST
962 __kstat_incr_irqs_this_cpu(desc);
963
2dcf1fbc
JT
964 trace_irq_handler_entry(irq, action);
965 res = action->handler(irq, raw_cpu_ptr(action->percpu_dev_id));
966 trace_irq_handler_exit(irq, action, res);
967
968 if (chip->irq_eoi)
969 chip->irq_eoi(&desc->irq_data);
970}
971
b8129a1f 972static void
3b0f95be
RK
973__irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle,
974 int is_chained, const char *name)
dd87eb3a 975{
091738a2 976 if (!handle) {
dd87eb3a 977 handle = handle_bad_irq;
091738a2 978 } else {
f86eff22
MZ
979 struct irq_data *irq_data = &desc->irq_data;
980#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
981 /*
982 * With hierarchical domains we might run into a
983 * situation where the outermost chip is not yet set
984 * up, but the inner chips are there. Instead of
985 * bailing we install the handler, but obviously we
986 * cannot enable/startup the interrupt at this point.
987 */
988 while (irq_data) {
989 if (irq_data->chip != &no_irq_chip)
990 break;
991 /*
992 * Bail out if the outer chip is not set up
c5f48c0a 993 * and the interrupt supposed to be started
f86eff22
MZ
994 * right away.
995 */
996 if (WARN_ON(is_chained))
3b0f95be 997 return;
f86eff22
MZ
998 /* Try the parent */
999 irq_data = irq_data->parent_data;
1000 }
1001#endif
1002 if (WARN_ON(!irq_data || irq_data->chip == &no_irq_chip))
3b0f95be 1003 return;
f8b5473f 1004 }
dd87eb3a 1005
dd87eb3a
TG
1006 /* Uninstall? */
1007 if (handle == handle_bad_irq) {
6b8ff312 1008 if (desc->irq_data.chip != &no_irq_chip)
9205e31d 1009 mask_ack_irq(desc);
801a0e9a 1010 irq_state_set_disabled(desc);
e509bd7d
MW
1011 if (is_chained)
1012 desc->action = NULL;
dd87eb3a
TG
1013 desc->depth = 1;
1014 }
1015 desc->handle_irq = handle;
a460e745 1016 desc->name = name;
dd87eb3a
TG
1017
1018 if (handle != handle_bad_irq && is_chained) {
1984e075
MZ
1019 unsigned int type = irqd_get_trigger_type(&desc->irq_data);
1020
1e12c4a9
MZ
1021 /*
1022 * We're about to start this interrupt immediately,
1023 * hence the need to set the trigger configuration.
1024 * But the .set_type callback may have overridden the
1025 * flow handler, ignoring that we're dealing with a
1026 * chained interrupt. Reset it immediately because we
1027 * do know better.
1028 */
1984e075
MZ
1029 if (type != IRQ_TYPE_NONE) {
1030 __irq_set_trigger(desc, type);
1031 desc->handle_irq = handle;
1032 }
1e12c4a9 1033
1ccb4e61
TG
1034 irq_settings_set_noprobe(desc);
1035 irq_settings_set_norequest(desc);
7f1b1244 1036 irq_settings_set_nothread(desc);
e509bd7d 1037 desc->action = &chained_action;
c942cee4 1038 irq_activate_and_startup(desc, IRQ_RESEND);
dd87eb3a 1039 }
3b0f95be
RK
1040}
1041
1042void
1043__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
1044 const char *name)
1045{
1046 unsigned long flags;
1047 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
1048
1049 if (!desc)
1050 return;
1051
1052 __irq_do_set_handler(desc, handle, is_chained, name);
02725e74 1053 irq_put_desc_busunlock(desc, flags);
dd87eb3a 1054}
3836ca08 1055EXPORT_SYMBOL_GPL(__irq_set_handler);
dd87eb3a 1056
3b0f95be
RK
1057void
1058irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
1059 void *data)
1060{
1061 unsigned long flags;
1062 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
1063
1064 if (!desc)
1065 return;
1066
af7080e0 1067 desc->irq_common_data.handler_data = data;
2c4569ca 1068 __irq_do_set_handler(desc, handle, 1, NULL);
3b0f95be
RK
1069
1070 irq_put_desc_busunlock(desc, flags);
1071}
1072EXPORT_SYMBOL_GPL(irq_set_chained_handler_and_data);
1073
dd87eb3a 1074void
3836ca08 1075irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
a460e745 1076 irq_flow_handler_t handle, const char *name)
dd87eb3a 1077{
35e857cb 1078 irq_set_chip(irq, chip);
3836ca08 1079 __irq_set_handler(irq, handle, 0, name);
dd87eb3a 1080}
b3ae66f2 1081EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name);
46f4f8f6 1082
44247184 1083void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
46f4f8f6 1084{
e8f24189 1085 unsigned long flags, trigger, tmp;
31d9d9b6 1086 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
46f4f8f6 1087
44247184 1088 if (!desc)
46f4f8f6 1089 return;
04c848d3
TG
1090
1091 /*
1092 * Warn when a driver sets the no autoenable flag on an already
1093 * active interrupt.
1094 */
1095 WARN_ON_ONCE(!desc->depth && (set & _IRQ_NOAUTOEN));
1096
a005677b
TG
1097 irq_settings_clr_and_set(desc, clr, set);
1098
e8f24189
MZ
1099 trigger = irqd_get_trigger_type(&desc->irq_data);
1100
876dbd4c 1101 irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
e1ef8241 1102 IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
a005677b
TG
1103 if (irq_settings_has_no_balance_set(desc))
1104 irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
1105 if (irq_settings_is_per_cpu(desc))
1106 irqd_set(&desc->irq_data, IRQD_PER_CPU);
e1ef8241
TG
1107 if (irq_settings_can_move_pcntxt(desc))
1108 irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
0ef5ca1e
TG
1109 if (irq_settings_is_level(desc))
1110 irqd_set(&desc->irq_data, IRQD_LEVEL);
a005677b 1111
e8f24189
MZ
1112 tmp = irq_settings_get_trigger_mask(desc);
1113 if (tmp != IRQ_TYPE_NONE)
1114 trigger = tmp;
1115
1116 irqd_set(&desc->irq_data, trigger);
876dbd4c 1117
02725e74 1118 irq_put_desc_unlock(desc, flags);
46f4f8f6 1119}
edf76f83 1120EXPORT_SYMBOL_GPL(irq_modify_status);
0fdb4b25
DD
1121
1122/**
1123 * irq_cpu_online - Invoke all irq_cpu_online functions.
1124 *
1125 * Iterate through all irqs and invoke the chip.irq_cpu_online()
1126 * for each.
1127 */
1128void irq_cpu_online(void)
1129{
1130 struct irq_desc *desc;
1131 struct irq_chip *chip;
1132 unsigned long flags;
1133 unsigned int irq;
1134
1135 for_each_active_irq(irq) {
1136 desc = irq_to_desc(irq);
1137 if (!desc)
1138 continue;
1139
1140 raw_spin_lock_irqsave(&desc->lock, flags);
1141
1142 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
1143 if (chip && chip->irq_cpu_online &&
1144 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 1145 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
1146 chip->irq_cpu_online(&desc->irq_data);
1147
1148 raw_spin_unlock_irqrestore(&desc->lock, flags);
1149 }
1150}
1151
1152/**
1153 * irq_cpu_offline - Invoke all irq_cpu_offline functions.
1154 *
1155 * Iterate through all irqs and invoke the chip.irq_cpu_offline()
1156 * for each.
1157 */
1158void irq_cpu_offline(void)
1159{
1160 struct irq_desc *desc;
1161 struct irq_chip *chip;
1162 unsigned long flags;
1163 unsigned int irq;
1164
1165 for_each_active_irq(irq) {
1166 desc = irq_to_desc(irq);
1167 if (!desc)
1168 continue;
1169
1170 raw_spin_lock_irqsave(&desc->lock, flags);
1171
1172 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
1173 if (chip && chip->irq_cpu_offline &&
1174 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 1175 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
1176 chip->irq_cpu_offline(&desc->irq_data);
1177
1178 raw_spin_unlock_irqrestore(&desc->lock, flags);
1179 }
1180}
85f08c17
JL
1181
1182#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
7703b08c
DD
1183
1184#ifdef CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS
1185/**
1186 * handle_fasteoi_ack_irq - irq handler for edge hierarchy
1187 * stacked on transparent controllers
1188 *
1189 * @desc: the interrupt description structure for this irq
1190 *
1191 * Like handle_fasteoi_irq(), but for use with hierarchy where
1192 * the irq_chip also needs to have its ->irq_ack() function
1193 * called.
1194 */
1195void handle_fasteoi_ack_irq(struct irq_desc *desc)
1196{
1197 struct irq_chip *chip = desc->irq_data.chip;
1198
1199 raw_spin_lock(&desc->lock);
1200
1201 if (!irq_may_run(desc))
1202 goto out;
1203
1204 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
1205
1206 /*
1207 * If its disabled or no action available
1208 * then mask it and get out of here:
1209 */
1210 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
1211 desc->istate |= IRQS_PENDING;
1212 mask_irq(desc);
1213 goto out;
1214 }
1215
1216 kstat_incr_irqs_this_cpu(desc);
1217 if (desc->istate & IRQS_ONESHOT)
1218 mask_irq(desc);
1219
1220 /* Start handling the irq */
1221 desc->irq_data.chip->irq_ack(&desc->irq_data);
1222
7703b08c
DD
1223 handle_irq_event(desc);
1224
1225 cond_unmask_eoi_irq(desc, chip);
1226
1227 raw_spin_unlock(&desc->lock);
1228 return;
1229out:
1230 if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
1231 chip->irq_eoi(&desc->irq_data);
1232 raw_spin_unlock(&desc->lock);
1233}
1234EXPORT_SYMBOL_GPL(handle_fasteoi_ack_irq);
1235
1236/**
1237 * handle_fasteoi_mask_irq - irq handler for level hierarchy
1238 * stacked on transparent controllers
1239 *
1240 * @desc: the interrupt description structure for this irq
1241 *
1242 * Like handle_fasteoi_irq(), but for use with hierarchy where
1243 * the irq_chip also needs to have its ->irq_mask_ack() function
1244 * called.
1245 */
1246void handle_fasteoi_mask_irq(struct irq_desc *desc)
1247{
1248 struct irq_chip *chip = desc->irq_data.chip;
1249
1250 raw_spin_lock(&desc->lock);
1251 mask_ack_irq(desc);
1252
1253 if (!irq_may_run(desc))
1254 goto out;
1255
1256 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
1257
1258 /*
1259 * If its disabled or no action available
1260 * then mask it and get out of here:
1261 */
1262 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
1263 desc->istate |= IRQS_PENDING;
1264 mask_irq(desc);
1265 goto out;
1266 }
1267
1268 kstat_incr_irqs_this_cpu(desc);
1269 if (desc->istate & IRQS_ONESHOT)
1270 mask_irq(desc);
1271
7703b08c
DD
1272 handle_irq_event(desc);
1273
1274 cond_unmask_eoi_irq(desc, chip);
1275
1276 raw_spin_unlock(&desc->lock);
1277 return;
1278out:
1279 if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
1280 chip->irq_eoi(&desc->irq_data);
1281 raw_spin_unlock(&desc->lock);
1282}
1283EXPORT_SYMBOL_GPL(handle_fasteoi_mask_irq);
1284
1285#endif /* CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS */
1286
4a169a95
MS
1287/**
1288 * irq_chip_set_parent_state - set the state of a parent interrupt.
1289 *
1290 * @data: Pointer to interrupt specific data
1291 * @which: State to be restored (one of IRQCHIP_STATE_*)
1292 * @val: Value corresponding to @which
1293 *
1294 * Conditional success, if the underlying irqchip does not implement it.
1295 */
1296int irq_chip_set_parent_state(struct irq_data *data,
1297 enum irqchip_irq_state which,
1298 bool val)
1299{
1300 data = data->parent_data;
1301
1302 if (!data || !data->chip->irq_set_irqchip_state)
1303 return 0;
1304
1305 return data->chip->irq_set_irqchip_state(data, which, val);
1306}
1307EXPORT_SYMBOL_GPL(irq_chip_set_parent_state);
1308
1309/**
1310 * irq_chip_get_parent_state - get the state of a parent interrupt.
1311 *
1312 * @data: Pointer to interrupt specific data
1313 * @which: one of IRQCHIP_STATE_* the caller wants to know
1314 * @state: a pointer to a boolean where the state is to be stored
1315 *
1316 * Conditional success, if the underlying irqchip does not implement it.
1317 */
1318int irq_chip_get_parent_state(struct irq_data *data,
1319 enum irqchip_irq_state which,
1320 bool *state)
1321{
1322 data = data->parent_data;
1323
1324 if (!data || !data->chip->irq_get_irqchip_state)
1325 return 0;
1326
1327 return data->chip->irq_get_irqchip_state(data, which, state);
1328}
1329EXPORT_SYMBOL_GPL(irq_chip_get_parent_state);
1330
3cfeffc2
SA
1331/**
1332 * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if
1333 * NULL)
1334 * @data: Pointer to interrupt specific data
1335 */
1336void irq_chip_enable_parent(struct irq_data *data)
1337{
1338 data = data->parent_data;
1339 if (data->chip->irq_enable)
1340 data->chip->irq_enable(data);
1341 else
1342 data->chip->irq_unmask(data);
1343}
65efd9a4 1344EXPORT_SYMBOL_GPL(irq_chip_enable_parent);
3cfeffc2
SA
1345
1346/**
1347 * irq_chip_disable_parent - Disable the parent interrupt (defaults to mask if
1348 * NULL)
1349 * @data: Pointer to interrupt specific data
1350 */
1351void irq_chip_disable_parent(struct irq_data *data)
1352{
1353 data = data->parent_data;
1354 if (data->chip->irq_disable)
1355 data->chip->irq_disable(data);
1356 else
1357 data->chip->irq_mask(data);
1358}
65efd9a4 1359EXPORT_SYMBOL_GPL(irq_chip_disable_parent);
3cfeffc2 1360
85f08c17
JL
1361/**
1362 * irq_chip_ack_parent - Acknowledge the parent interrupt
1363 * @data: Pointer to interrupt specific data
1364 */
1365void irq_chip_ack_parent(struct irq_data *data)
1366{
1367 data = data->parent_data;
1368 data->chip->irq_ack(data);
1369}
a4289dc2 1370EXPORT_SYMBOL_GPL(irq_chip_ack_parent);
85f08c17 1371
56e8abab
YC
1372/**
1373 * irq_chip_mask_parent - Mask the parent interrupt
1374 * @data: Pointer to interrupt specific data
1375 */
1376void irq_chip_mask_parent(struct irq_data *data)
1377{
1378 data = data->parent_data;
1379 data->chip->irq_mask(data);
1380}
52b2a05f 1381EXPORT_SYMBOL_GPL(irq_chip_mask_parent);
56e8abab 1382
5aa5bd56
LW
1383/**
1384 * irq_chip_mask_ack_parent - Mask and acknowledge the parent interrupt
1385 * @data: Pointer to interrupt specific data
1386 */
1387void irq_chip_mask_ack_parent(struct irq_data *data)
1388{
1389 data = data->parent_data;
1390 data->chip->irq_mask_ack(data);
1391}
1392EXPORT_SYMBOL_GPL(irq_chip_mask_ack_parent);
1393
56e8abab
YC
1394/**
1395 * irq_chip_unmask_parent - Unmask the parent interrupt
1396 * @data: Pointer to interrupt specific data
1397 */
1398void irq_chip_unmask_parent(struct irq_data *data)
1399{
1400 data = data->parent_data;
1401 data->chip->irq_unmask(data);
1402}
52b2a05f 1403EXPORT_SYMBOL_GPL(irq_chip_unmask_parent);
56e8abab
YC
1404
1405/**
1406 * irq_chip_eoi_parent - Invoke EOI on the parent interrupt
1407 * @data: Pointer to interrupt specific data
1408 */
1409void irq_chip_eoi_parent(struct irq_data *data)
1410{
1411 data = data->parent_data;
1412 data->chip->irq_eoi(data);
1413}
52b2a05f 1414EXPORT_SYMBOL_GPL(irq_chip_eoi_parent);
56e8abab
YC
1415
1416/**
1417 * irq_chip_set_affinity_parent - Set affinity on the parent interrupt
1418 * @data: Pointer to interrupt specific data
1419 * @dest: The affinity mask to set
1420 * @force: Flag to enforce setting (disable online checks)
1421 *
1422 * Conditinal, as the underlying parent chip might not implement it.
1423 */
1424int irq_chip_set_affinity_parent(struct irq_data *data,
1425 const struct cpumask *dest, bool force)
1426{
1427 data = data->parent_data;
1428 if (data->chip->irq_set_affinity)
1429 return data->chip->irq_set_affinity(data, dest, force);
b7560de1
GS
1430
1431 return -ENOSYS;
1432}
65efd9a4 1433EXPORT_SYMBOL_GPL(irq_chip_set_affinity_parent);
b7560de1
GS
1434
1435/**
1436 * irq_chip_set_type_parent - Set IRQ type on the parent interrupt
1437 * @data: Pointer to interrupt specific data
1438 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
1439 *
1440 * Conditional, as the underlying parent chip might not implement it.
1441 */
1442int irq_chip_set_type_parent(struct irq_data *data, unsigned int type)
1443{
1444 data = data->parent_data;
1445
1446 if (data->chip->irq_set_type)
1447 return data->chip->irq_set_type(data, type);
56e8abab
YC
1448
1449 return -ENOSYS;
1450}
52b2a05f 1451EXPORT_SYMBOL_GPL(irq_chip_set_type_parent);
56e8abab 1452
85f08c17
JL
1453/**
1454 * irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware
1455 * @data: Pointer to interrupt specific data
1456 *
1457 * Iterate through the domain hierarchy of the interrupt and check
1458 * whether a hw retrigger function exists. If yes, invoke it.
1459 */
1460int irq_chip_retrigger_hierarchy(struct irq_data *data)
1461{
1462 for (data = data->parent_data; data; data = data->parent_data)
1463 if (data->chip && data->chip->irq_retrigger)
1464 return data->chip->irq_retrigger(data);
1465
6d4affea 1466 return 0;
85f08c17 1467}
8d16f5b9 1468EXPORT_SYMBOL_GPL(irq_chip_retrigger_hierarchy);
08b55e2a 1469
0a4377de
JL
1470/**
1471 * irq_chip_set_vcpu_affinity_parent - Set vcpu affinity on the parent interrupt
1472 * @data: Pointer to interrupt specific data
8505a81b 1473 * @vcpu_info: The vcpu affinity information
0a4377de
JL
1474 */
1475int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info)
1476{
1477 data = data->parent_data;
1478 if (data->chip->irq_set_vcpu_affinity)
1479 return data->chip->irq_set_vcpu_affinity(data, vcpu_info);
1480
1481 return -ENOSYS;
1482}
8d16f5b9 1483EXPORT_SYMBOL_GPL(irq_chip_set_vcpu_affinity_parent);
08b55e2a
MZ
1484/**
1485 * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
1486 * @data: Pointer to interrupt specific data
1487 * @on: Whether to set or reset the wake-up capability of this irq
1488 *
1489 * Conditional, as the underlying parent chip might not implement it.
1490 */
1491int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
1492{
1493 data = data->parent_data;
325aa195
SB
1494
1495 if (data->chip->flags & IRQCHIP_SKIP_SET_WAKE)
1496 return 0;
1497
08b55e2a
MZ
1498 if (data->chip->irq_set_wake)
1499 return data->chip->irq_set_wake(data, on);
1500
1501 return -ENOSYS;
1502}
38f7ae9b 1503EXPORT_SYMBOL_GPL(irq_chip_set_wake_parent);
2bd1298a
LV
1504
1505/**
1506 * irq_chip_request_resources_parent - Request resources on the parent interrupt
1507 * @data: Pointer to interrupt specific data
1508 */
1509int irq_chip_request_resources_parent(struct irq_data *data)
1510{
1511 data = data->parent_data;
1512
1513 if (data->chip->irq_request_resources)
1514 return data->chip->irq_request_resources(data);
1515
1516 return -ENOSYS;
1517}
1518EXPORT_SYMBOL_GPL(irq_chip_request_resources_parent);
1519
1520/**
1521 * irq_chip_release_resources_parent - Release resources on the parent interrupt
1522 * @data: Pointer to interrupt specific data
1523 */
1524void irq_chip_release_resources_parent(struct irq_data *data)
1525{
1526 data = data->parent_data;
1527 if (data->chip->irq_release_resources)
1528 data->chip->irq_release_resources(data);
1529}
1530EXPORT_SYMBOL_GPL(irq_chip_release_resources_parent);
85f08c17 1531#endif
515085ef
JL
1532
1533/**
1534 * irq_chip_compose_msi_msg - Componse msi message for a irq chip
1535 * @data: Pointer to interrupt specific data
1536 * @msg: Pointer to the MSI message
1537 *
1538 * For hierarchical domains we find the first chip in the hierarchy
1539 * which implements the irq_compose_msi_msg callback. For non
1540 * hierarchical we use the top level chip.
1541 */
1542int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
1543{
13b90cad 1544 struct irq_data *pos;
515085ef 1545
13b90cad 1546 for (pos = NULL; !pos && data; data = irqd_get_parent_data(data)) {
515085ef
JL
1547 if (data->chip && data->chip->irq_compose_msi_msg)
1548 pos = data;
13b90cad
TG
1549 }
1550
515085ef
JL
1551 if (!pos)
1552 return -ENOSYS;
1553
1554 pos->chip->irq_compose_msi_msg(pos, msg);
515085ef
JL
1555 return 0;
1556}
be45beb2
JH
1557
1558/**
1559 * irq_chip_pm_get - Enable power for an IRQ chip
1560 * @data: Pointer to interrupt specific data
1561 *
1562 * Enable the power to the IRQ chip referenced by the interrupt data
1563 * structure.
1564 */
1565int irq_chip_pm_get(struct irq_data *data)
1566{
1567 int retval;
1568
1569 if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) {
1570 retval = pm_runtime_get_sync(data->chip->parent_device);
1571 if (retval < 0) {
1572 pm_runtime_put_noidle(data->chip->parent_device);
1573 return retval;
1574 }
1575 }
1576
1577 return 0;
1578}
1579
1580/**
1581 * irq_chip_pm_put - Disable power for an IRQ chip
1582 * @data: Pointer to interrupt specific data
1583 *
1584 * Disable the power to the IRQ chip referenced by the interrupt data
1585 * structure, belongs. Note that power will only be disabled, once this
1586 * function has been called for all IRQs that have called irq_chip_pm_get().
1587 */
1588int irq_chip_pm_put(struct irq_data *data)
1589{
1590 int retval = 0;
1591
1592 if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device)
1593 retval = pm_runtime_put(data->chip->parent_device);
1594
1595 return (retval < 0) ? retval : 0;
1596}