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genirq: Move IRQ_PENDING flag to core
[mirror_ubuntu-zesty-kernel.git] / kernel / irq / chip.c
CommitLineData
dd87eb3a
TG
1/*
2 * linux/kernel/irq/chip.c
3 *
4 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
5 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 *
7 * This file contains the core interrupt handling code, for irq-chip
8 * based architectures.
9 *
10 * Detailed information is available in Documentation/DocBook/genericirq
11 */
12
13#include <linux/irq.h>
7fe3730d 14#include <linux/msi.h>
dd87eb3a
TG
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/kernel_stat.h>
18
19#include "internals.h"
20
21/**
a0cd9ca2 22 * irq_set_chip - set the irq chip for an irq
dd87eb3a
TG
23 * @irq: irq number
24 * @chip: pointer to irq chip description structure
25 */
a0cd9ca2 26int irq_set_chip(unsigned int irq, struct irq_chip *chip)
dd87eb3a 27{
d3c60047 28 struct irq_desc *desc = irq_to_desc(irq);
dd87eb3a
TG
29 unsigned long flags;
30
7d94f7ca 31 if (!desc) {
261c40c1 32 WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq);
dd87eb3a
TG
33 return -EINVAL;
34 }
35
36 if (!chip)
37 chip = &no_irq_chip;
38
239007b8 39 raw_spin_lock_irqsave(&desc->lock, flags);
dd87eb3a 40 irq_chip_set_defaults(chip);
6b8ff312 41 desc->irq_data.chip = chip;
239007b8 42 raw_spin_unlock_irqrestore(&desc->lock, flags);
dd87eb3a
TG
43
44 return 0;
45}
a0cd9ca2 46EXPORT_SYMBOL(irq_set_chip);
dd87eb3a
TG
47
48/**
a0cd9ca2 49 * irq_set_type - set the irq trigger type for an irq
dd87eb3a 50 * @irq: irq number
0c5d1eb7 51 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
dd87eb3a 52 */
a0cd9ca2 53int irq_set_irq_type(unsigned int irq, unsigned int type)
dd87eb3a 54{
d3c60047 55 struct irq_desc *desc = irq_to_desc(irq);
dd87eb3a
TG
56 unsigned long flags;
57 int ret = -ENXIO;
58
7d94f7ca 59 if (!desc) {
dd87eb3a
TG
60 printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq);
61 return -ENODEV;
62 }
63
f2b662da 64 type &= IRQ_TYPE_SENSE_MASK;
0c5d1eb7
DB
65 if (type == IRQ_TYPE_NONE)
66 return 0;
67
43abe43c 68 chip_bus_lock(desc);
239007b8 69 raw_spin_lock_irqsave(&desc->lock, flags);
0b3682ba 70 ret = __irq_set_trigger(desc, irq, type);
239007b8 71 raw_spin_unlock_irqrestore(&desc->lock, flags);
43abe43c 72 chip_bus_sync_unlock(desc);
dd87eb3a
TG
73 return ret;
74}
a0cd9ca2 75EXPORT_SYMBOL(irq_set_irq_type);
dd87eb3a
TG
76
77/**
a0cd9ca2 78 * irq_set_handler_data - set irq handler data for an irq
dd87eb3a
TG
79 * @irq: Interrupt number
80 * @data: Pointer to interrupt specific data
81 *
82 * Set the hardware irq controller data for an irq
83 */
a0cd9ca2 84int irq_set_handler_data(unsigned int irq, void *data)
dd87eb3a 85{
d3c60047 86 struct irq_desc *desc = irq_to_desc(irq);
dd87eb3a
TG
87 unsigned long flags;
88
7d94f7ca 89 if (!desc) {
dd87eb3a
TG
90 printk(KERN_ERR
91 "Trying to install controller data for IRQ%d\n", irq);
92 return -EINVAL;
93 }
94
239007b8 95 raw_spin_lock_irqsave(&desc->lock, flags);
6b8ff312 96 desc->irq_data.handler_data = data;
239007b8 97 raw_spin_unlock_irqrestore(&desc->lock, flags);
dd87eb3a
TG
98 return 0;
99}
a0cd9ca2 100EXPORT_SYMBOL(irq_set_handler_data);
dd87eb3a 101
5b912c10 102/**
a0cd9ca2 103 * irq_set_msi_desc - set MSI descriptor data for an irq
5b912c10 104 * @irq: Interrupt number
472900b8 105 * @entry: Pointer to MSI descriptor data
5b912c10 106 *
24b26d42 107 * Set the MSI descriptor entry for an irq
5b912c10 108 */
a0cd9ca2 109int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
5b912c10 110{
d3c60047 111 struct irq_desc *desc = irq_to_desc(irq);
5b912c10
EB
112 unsigned long flags;
113
7d94f7ca 114 if (!desc) {
5b912c10
EB
115 printk(KERN_ERR
116 "Trying to install msi data for IRQ%d\n", irq);
117 return -EINVAL;
118 }
7d94f7ca 119
239007b8 120 raw_spin_lock_irqsave(&desc->lock, flags);
6b8ff312 121 desc->irq_data.msi_desc = entry;
7fe3730d
ME
122 if (entry)
123 entry->irq = irq;
239007b8 124 raw_spin_unlock_irqrestore(&desc->lock, flags);
5b912c10
EB
125 return 0;
126}
127
dd87eb3a 128/**
a0cd9ca2 129 * irq_set_chip_data - set irq chip data for an irq
dd87eb3a
TG
130 * @irq: Interrupt number
131 * @data: Pointer to chip specific data
132 *
133 * Set the hardware irq chip data for an irq
134 */
a0cd9ca2 135int irq_set_chip_data(unsigned int irq, void *data)
dd87eb3a 136{
d3c60047 137 struct irq_desc *desc = irq_to_desc(irq);
dd87eb3a
TG
138 unsigned long flags;
139
7d94f7ca
YL
140 if (!desc) {
141 printk(KERN_ERR
142 "Trying to install chip data for IRQ%d\n", irq);
143 return -EINVAL;
144 }
145
6b8ff312 146 if (!desc->irq_data.chip) {
dd87eb3a
TG
147 printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq);
148 return -EINVAL;
149 }
150
239007b8 151 raw_spin_lock_irqsave(&desc->lock, flags);
6b8ff312 152 desc->irq_data.chip_data = data;
239007b8 153 raw_spin_unlock_irqrestore(&desc->lock, flags);
dd87eb3a
TG
154
155 return 0;
156}
a0cd9ca2 157EXPORT_SYMBOL(irq_set_chip_data);
dd87eb3a 158
f303a6dd
TG
159struct irq_data *irq_get_irq_data(unsigned int irq)
160{
161 struct irq_desc *desc = irq_to_desc(irq);
162
163 return desc ? &desc->irq_data : NULL;
164}
165EXPORT_SYMBOL_GPL(irq_get_irq_data);
166
c1594b77
TG
167static void irq_state_clr_disabled(struct irq_desc *desc)
168{
169 desc->istate &= ~IRQS_DISABLED;
170 irq_compat_clr_disabled(desc);
171}
172
173static void irq_state_set_disabled(struct irq_desc *desc)
174{
175 desc->istate |= IRQS_DISABLED;
176 irq_compat_set_disabled(desc);
177}
178
46999238
TG
179int irq_startup(struct irq_desc *desc)
180{
c1594b77 181 irq_state_clr_disabled(desc);
46999238
TG
182 desc->depth = 0;
183
3aae994f
TG
184 if (desc->irq_data.chip->irq_startup) {
185 int ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
186 desc->status &= ~IRQ_MASKED;
187 return ret;
188 }
46999238 189
87923470 190 irq_enable(desc);
46999238
TG
191 return 0;
192}
193
194void irq_shutdown(struct irq_desc *desc)
195{
c1594b77 196 irq_state_set_disabled(desc);
46999238 197 desc->depth = 1;
50f7c032
TG
198 if (desc->irq_data.chip->irq_shutdown)
199 desc->irq_data.chip->irq_shutdown(&desc->irq_data);
200 if (desc->irq_data.chip->irq_disable)
201 desc->irq_data.chip->irq_disable(&desc->irq_data);
202 else
203 desc->irq_data.chip->irq_mask(&desc->irq_data);
3aae994f 204 desc->status |= IRQ_MASKED;
46999238
TG
205}
206
87923470
TG
207void irq_enable(struct irq_desc *desc)
208{
c1594b77 209 irq_state_clr_disabled(desc);
50f7c032
TG
210 if (desc->irq_data.chip->irq_enable)
211 desc->irq_data.chip->irq_enable(&desc->irq_data);
212 else
213 desc->irq_data.chip->irq_unmask(&desc->irq_data);
dd87eb3a
TG
214 desc->status &= ~IRQ_MASKED;
215}
216
50f7c032 217void irq_disable(struct irq_desc *desc)
89d694b9 218{
c1594b77 219 irq_state_set_disabled(desc);
50f7c032
TG
220 if (desc->irq_data.chip->irq_disable) {
221 desc->irq_data.chip->irq_disable(&desc->irq_data);
222 desc->status |= IRQ_MASKED;
223 }
89d694b9
TG
224}
225
bd151412 226#ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED
3876ec9e 227/* Temporary migration helpers */
e2c0f8ff
TG
228static void compat_irq_mask(struct irq_data *data)
229{
230 data->chip->mask(data->irq);
231}
232
0eda58b7
TG
233static void compat_irq_unmask(struct irq_data *data)
234{
235 data->chip->unmask(data->irq);
236}
237
22a49163
TG
238static void compat_irq_ack(struct irq_data *data)
239{
240 data->chip->ack(data->irq);
241}
242
9205e31d
TG
243static void compat_irq_mask_ack(struct irq_data *data)
244{
245 data->chip->mask_ack(data->irq);
246}
247
0c5c1557
TG
248static void compat_irq_eoi(struct irq_data *data)
249{
250 data->chip->eoi(data->irq);
251}
252
c5f75634
TG
253static void compat_irq_enable(struct irq_data *data)
254{
255 data->chip->enable(data->irq);
256}
257
bc310dda
TG
258static void compat_irq_disable(struct irq_data *data)
259{
260 data->chip->disable(data->irq);
261}
262
263static void compat_irq_shutdown(struct irq_data *data)
264{
265 data->chip->shutdown(data->irq);
266}
267
37e12df7
TG
268static unsigned int compat_irq_startup(struct irq_data *data)
269{
270 return data->chip->startup(data->irq);
271}
272
c96b3b3c
TG
273static int compat_irq_set_affinity(struct irq_data *data,
274 const struct cpumask *dest, bool force)
275{
276 return data->chip->set_affinity(data->irq, dest);
277}
278
b2ba2c30
TG
279static int compat_irq_set_type(struct irq_data *data, unsigned int type)
280{
281 return data->chip->set_type(data->irq, type);
282}
283
2f7e99bb
TG
284static int compat_irq_set_wake(struct irq_data *data, unsigned int on)
285{
286 return data->chip->set_wake(data->irq, on);
287}
288
21e2b8c6
TG
289static int compat_irq_retrigger(struct irq_data *data)
290{
291 return data->chip->retrigger(data->irq);
292}
293
3876ec9e
TG
294static void compat_bus_lock(struct irq_data *data)
295{
296 data->chip->bus_lock(data->irq);
297}
298
299static void compat_bus_sync_unlock(struct irq_data *data)
300{
301 data->chip->bus_sync_unlock(data->irq);
302}
bd151412 303#endif
3876ec9e 304
dd87eb3a
TG
305/*
306 * Fixup enable/disable function pointers
307 */
308void irq_chip_set_defaults(struct irq_chip *chip)
309{
bd151412 310#ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED
c5f75634
TG
311 if (chip->enable)
312 chip->irq_enable = compat_irq_enable;
bc310dda
TG
313 if (chip->disable)
314 chip->irq_disable = compat_irq_disable;
315 if (chip->shutdown)
316 chip->irq_shutdown = compat_irq_shutdown;
37e12df7
TG
317 if (chip->startup)
318 chip->irq_startup = compat_irq_startup;
b86432b4
ZY
319 if (!chip->end)
320 chip->end = dummy_irq_chip.end;
3876ec9e
TG
321 if (chip->bus_lock)
322 chip->irq_bus_lock = compat_bus_lock;
323 if (chip->bus_sync_unlock)
324 chip->irq_bus_sync_unlock = compat_bus_sync_unlock;
e2c0f8ff
TG
325 if (chip->mask)
326 chip->irq_mask = compat_irq_mask;
0eda58b7
TG
327 if (chip->unmask)
328 chip->irq_unmask = compat_irq_unmask;
22a49163
TG
329 if (chip->ack)
330 chip->irq_ack = compat_irq_ack;
9205e31d
TG
331 if (chip->mask_ack)
332 chip->irq_mask_ack = compat_irq_mask_ack;
0c5c1557
TG
333 if (chip->eoi)
334 chip->irq_eoi = compat_irq_eoi;
c96b3b3c
TG
335 if (chip->set_affinity)
336 chip->irq_set_affinity = compat_irq_set_affinity;
b2ba2c30
TG
337 if (chip->set_type)
338 chip->irq_set_type = compat_irq_set_type;
2f7e99bb
TG
339 if (chip->set_wake)
340 chip->irq_set_wake = compat_irq_set_wake;
21e2b8c6
TG
341 if (chip->retrigger)
342 chip->irq_retrigger = compat_irq_retrigger;
bd151412 343#endif
dd87eb3a
TG
344}
345
9205e31d 346static inline void mask_ack_irq(struct irq_desc *desc)
dd87eb3a 347{
9205e31d
TG
348 if (desc->irq_data.chip->irq_mask_ack)
349 desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
dd87eb3a 350 else {
e2c0f8ff 351 desc->irq_data.chip->irq_mask(&desc->irq_data);
22a49163
TG
352 if (desc->irq_data.chip->irq_ack)
353 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 354 }
0b1adaa0
TG
355 desc->status |= IRQ_MASKED;
356}
357
e2c0f8ff 358static inline void mask_irq(struct irq_desc *desc)
0b1adaa0 359{
e2c0f8ff
TG
360 if (desc->irq_data.chip->irq_mask) {
361 desc->irq_data.chip->irq_mask(&desc->irq_data);
0b1adaa0
TG
362 desc->status |= IRQ_MASKED;
363 }
364}
365
0eda58b7 366static inline void unmask_irq(struct irq_desc *desc)
0b1adaa0 367{
0eda58b7
TG
368 if (desc->irq_data.chip->irq_unmask) {
369 desc->irq_data.chip->irq_unmask(&desc->irq_data);
0b1adaa0
TG
370 desc->status &= ~IRQ_MASKED;
371 }
dd87eb3a
TG
372}
373
399b5da2
TG
374/*
375 * handle_nested_irq - Handle a nested irq from a irq thread
376 * @irq: the interrupt number
377 *
378 * Handle interrupts which are nested into a threaded interrupt
379 * handler. The handler function is called inside the calling
380 * threads context.
381 */
382void handle_nested_irq(unsigned int irq)
383{
384 struct irq_desc *desc = irq_to_desc(irq);
385 struct irqaction *action;
386 irqreturn_t action_ret;
387
388 might_sleep();
389
239007b8 390 raw_spin_lock_irq(&desc->lock);
399b5da2
TG
391
392 kstat_incr_irqs_this_cpu(irq, desc);
393
394 action = desc->action;
c1594b77 395 if (unlikely(!action || (desc->istate & IRQS_DISABLED)))
399b5da2
TG
396 goto out_unlock;
397
009b4c3b
TG
398 irq_compat_set_progress(desc);
399 desc->istate |= IRQS_INPROGRESS;
239007b8 400 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
401
402 action_ret = action->thread_fn(action->irq, action->dev_id);
403 if (!noirqdebug)
404 note_interrupt(irq, desc, action_ret);
405
239007b8 406 raw_spin_lock_irq(&desc->lock);
009b4c3b
TG
407 desc->istate &= ~IRQS_INPROGRESS;
408 irq_compat_clr_progress(desc);
399b5da2
TG
409
410out_unlock:
239007b8 411 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
412}
413EXPORT_SYMBOL_GPL(handle_nested_irq);
414
fe200ae4
TG
415static bool irq_check_poll(struct irq_desc *desc)
416{
6954b75b 417 if (!(desc->istate & IRQS_POLL_INPROGRESS))
fe200ae4
TG
418 return false;
419 return irq_wait_for_poll(desc);
420}
421
dd87eb3a
TG
422/**
423 * handle_simple_irq - Simple and software-decoded IRQs.
424 * @irq: the interrupt number
425 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
426 *
427 * Simple interrupts are either sent from a demultiplexing interrupt
428 * handler or come from hardware, where no interrupt hardware control
429 * is necessary.
430 *
431 * Note: The caller is expected to handle the ack, clear, mask and
432 * unmask issues if necessary.
433 */
7ad5b3a5 434void
7d12e780 435handle_simple_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 436{
239007b8 437 raw_spin_lock(&desc->lock);
dd87eb3a 438
009b4c3b 439 if (unlikely(desc->istate & IRQS_INPROGRESS))
fe200ae4
TG
440 if (!irq_check_poll(desc))
441 goto out_unlock;
442
163ef309 443 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 444 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 445
c1594b77 446 if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED)))
dd87eb3a
TG
447 goto out_unlock;
448
107781e7 449 handle_irq_event(desc);
dd87eb3a 450
dd87eb3a 451out_unlock:
239007b8 452 raw_spin_unlock(&desc->lock);
dd87eb3a
TG
453}
454
455/**
456 * handle_level_irq - Level type irq handler
457 * @irq: the interrupt number
458 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
459 *
460 * Level type interrupts are active as long as the hardware line has
461 * the active level. This may require to mask the interrupt and unmask
462 * it after the associated handler has acknowledged the device, so the
463 * interrupt line is back to inactive.
464 */
7ad5b3a5 465void
7d12e780 466handle_level_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 467{
239007b8 468 raw_spin_lock(&desc->lock);
9205e31d 469 mask_ack_irq(desc);
dd87eb3a 470
009b4c3b 471 if (unlikely(desc->istate & IRQS_INPROGRESS))
fe200ae4
TG
472 if (!irq_check_poll(desc))
473 goto out_unlock;
474
163ef309 475 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 476 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
477
478 /*
479 * If its disabled or no action available
480 * keep it masked and get out of here
481 */
c1594b77 482 if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED)))
86998aa6 483 goto out_unlock;
dd87eb3a 484
1529866c 485 handle_irq_event(desc);
b25c340c 486
c1594b77 487 if (!(desc->istate & (IRQS_DISABLED | IRQS_ONESHOT)))
0eda58b7 488 unmask_irq(desc);
86998aa6 489out_unlock:
239007b8 490 raw_spin_unlock(&desc->lock);
dd87eb3a 491}
14819ea1 492EXPORT_SYMBOL_GPL(handle_level_irq);
dd87eb3a
TG
493
494/**
47c2a3aa 495 * handle_fasteoi_irq - irq handler for transparent controllers
dd87eb3a
TG
496 * @irq: the interrupt number
497 * @desc: the interrupt description structure for this irq
dd87eb3a 498 *
47c2a3aa 499 * Only a single callback will be issued to the chip: an ->eoi()
dd87eb3a
TG
500 * call when the interrupt has been serviced. This enables support
501 * for modern forms of interrupt handlers, which handle the flow
502 * details in hardware, transparently.
503 */
7ad5b3a5 504void
7d12e780 505handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 506{
239007b8 507 raw_spin_lock(&desc->lock);
dd87eb3a 508
009b4c3b 509 if (unlikely(desc->istate & IRQS_INPROGRESS))
fe200ae4
TG
510 if (!irq_check_poll(desc))
511 goto out;
dd87eb3a 512
163ef309 513 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 514 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
515
516 /*
517 * If its disabled or no action available
76d21601 518 * then mask it and get out of here:
dd87eb3a 519 */
c1594b77 520 if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED))) {
2a0d6fb3
TG
521 irq_compat_set_pending(desc);
522 desc->istate |= IRQS_PENDING;
e2c0f8ff 523 mask_irq(desc);
dd87eb3a 524 goto out;
98bb244b 525 }
a7ae4de5 526 handle_irq_event(desc);
dd87eb3a 527out:
0c5c1557 528 desc->irq_data.chip->irq_eoi(&desc->irq_data);
239007b8 529 raw_spin_unlock(&desc->lock);
dd87eb3a
TG
530}
531
532/**
533 * handle_edge_irq - edge type IRQ handler
534 * @irq: the interrupt number
535 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
536 *
537 * Interrupt occures on the falling and/or rising edge of a hardware
538 * signal. The occurence is latched into the irq controller hardware
539 * and must be acked in order to be reenabled. After the ack another
540 * interrupt can happen on the same source even before the first one
dfff0615 541 * is handled by the associated event handler. If this happens it
dd87eb3a
TG
542 * might be necessary to disable (mask) the interrupt depending on the
543 * controller hardware. This requires to reenable the interrupt inside
544 * of the loop which handles the interrupts which have arrived while
545 * the handler was running. If all pending interrupts are handled, the
546 * loop is left.
547 */
7ad5b3a5 548void
7d12e780 549handle_edge_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 550{
239007b8 551 raw_spin_lock(&desc->lock);
dd87eb3a 552
163ef309 553 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
554 /*
555 * If we're currently running this IRQ, or its disabled,
556 * we shouldn't process the IRQ. Mark it pending, handle
557 * the necessary masking and go out
558 */
c1594b77
TG
559 if (unlikely((desc->istate & (IRQS_DISABLED | IRQS_INPROGRESS) ||
560 !desc->action))) {
fe200ae4 561 if (!irq_check_poll(desc)) {
2a0d6fb3
TG
562 irq_compat_set_pending(desc);
563 desc->istate |= IRQS_PENDING;
fe200ae4
TG
564 mask_ack_irq(desc);
565 goto out_unlock;
566 }
dd87eb3a 567 }
d6c88a50 568 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
569
570 /* Start handling the irq */
22a49163 571 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 572
dd87eb3a 573 do {
a60a5dc2 574 if (unlikely(!desc->action)) {
e2c0f8ff 575 mask_irq(desc);
dd87eb3a
TG
576 goto out_unlock;
577 }
578
579 /*
580 * When another irq arrived while we were handling
581 * one, we could have masked the irq.
582 * Renable it, if it was not disabled in meantime.
583 */
2a0d6fb3 584 if (unlikely(desc->istate & IRQS_PENDING)) {
c1594b77
TG
585 if (!(desc->istate & IRQS_DISABLED) &&
586 (desc->status & IRQ_MASKED))
587 unmask_irq(desc);
dd87eb3a
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588 }
589
a60a5dc2 590 handle_irq_event(desc);
dd87eb3a 591
2a0d6fb3 592 } while ((desc->istate & IRQS_PENDING) &&
c1594b77 593 !(desc->istate & IRQS_DISABLED));
dd87eb3a 594
dd87eb3a 595out_unlock:
239007b8 596 raw_spin_unlock(&desc->lock);
dd87eb3a
TG
597}
598
dd87eb3a 599/**
24b26d42 600 * handle_percpu_irq - Per CPU local irq handler
dd87eb3a
TG
601 * @irq: the interrupt number
602 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
603 *
604 * Per CPU interrupts on SMP machines without locking requirements
605 */
7ad5b3a5 606void
7d12e780 607handle_percpu_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 608{
35e857cb 609 struct irq_chip *chip = irq_desc_get_chip(desc);
dd87eb3a 610
d6c88a50 611 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 612
849f061c
TG
613 if (chip->irq_ack)
614 chip->irq_ack(&desc->irq_data);
dd87eb3a 615
849f061c 616 handle_irq_event_percpu(desc, desc->action);
dd87eb3a 617
849f061c
TG
618 if (chip->irq_eoi)
619 chip->irq_eoi(&desc->irq_data);
dd87eb3a
TG
620}
621
dd87eb3a 622void
a460e745
IM
623__set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
624 const char *name)
dd87eb3a 625{
d3c60047 626 struct irq_desc *desc = irq_to_desc(irq);
dd87eb3a
TG
627 unsigned long flags;
628
7d94f7ca 629 if (!desc) {
dd87eb3a
TG
630 printk(KERN_ERR
631 "Trying to install type control for IRQ%d\n", irq);
632 return;
633 }
634
dd87eb3a
TG
635 if (!handle)
636 handle = handle_bad_irq;
6b8ff312 637 else if (desc->irq_data.chip == &no_irq_chip) {
f8b5473f 638 printk(KERN_WARNING "Trying to install %sinterrupt handler "
b039db8e 639 "for IRQ%d\n", is_chained ? "chained " : "", irq);
f8b5473f
TG
640 /*
641 * Some ARM implementations install a handler for really dumb
642 * interrupt hardware without setting an irq_chip. This worked
643 * with the ARM no_irq_chip but the check in setup_irq would
644 * prevent us to setup the interrupt at all. Switch it to
645 * dummy_irq_chip for easy transition.
646 */
6b8ff312 647 desc->irq_data.chip = &dummy_irq_chip;
f8b5473f 648 }
dd87eb3a 649
3876ec9e 650 chip_bus_lock(desc);
239007b8 651 raw_spin_lock_irqsave(&desc->lock, flags);
dd87eb3a
TG
652
653 /* Uninstall? */
654 if (handle == handle_bad_irq) {
6b8ff312 655 if (desc->irq_data.chip != &no_irq_chip)
9205e31d 656 mask_ack_irq(desc);
c1594b77
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657 irq_compat_set_disabled(desc);
658 desc->istate |= IRQS_DISABLED;
dd87eb3a
TG
659 desc->depth = 1;
660 }
661 desc->handle_irq = handle;
a460e745 662 desc->name = name;
dd87eb3a
TG
663
664 if (handle != handle_bad_irq && is_chained) {
dd87eb3a 665 desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE;
46999238 666 irq_startup(desc);
dd87eb3a 667 }
239007b8 668 raw_spin_unlock_irqrestore(&desc->lock, flags);
3876ec9e 669 chip_bus_sync_unlock(desc);
dd87eb3a 670}
14819ea1 671EXPORT_SYMBOL_GPL(__set_irq_handler);
dd87eb3a
TG
672
673void
674set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
57a58a94 675 irq_flow_handler_t handle)
dd87eb3a 676{
35e857cb 677 irq_set_chip(irq, chip);
a460e745 678 __set_irq_handler(irq, handle, 0, NULL);
dd87eb3a
TG
679}
680
a460e745
IM
681void
682set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
683 irq_flow_handler_t handle, const char *name)
dd87eb3a 684{
35e857cb 685 irq_set_chip(irq, chip);
a460e745 686 __set_irq_handler(irq, handle, 0, name);
dd87eb3a 687}
46f4f8f6 688
44247184 689void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
46f4f8f6 690{
d3c60047 691 struct irq_desc *desc = irq_to_desc(irq);
46f4f8f6
RB
692 unsigned long flags;
693
44247184 694 if (!desc)
46f4f8f6 695 return;
46f4f8f6 696
44247184
TG
697 /* Sanitize flags */
698 set &= IRQF_MODIFY_MASK;
699 clr &= IRQF_MODIFY_MASK;
46f4f8f6 700
239007b8 701 raw_spin_lock_irqsave(&desc->lock, flags);
44247184
TG
702 desc->status &= ~clr;
703 desc->status |= set;
239007b8 704 raw_spin_unlock_irqrestore(&desc->lock, flags);
46f4f8f6 705}