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Commit | Line | Data |
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dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
18 | ||
19 | #include "internals.h" | |
20 | ||
ced5b697 | 21 | static void dynamic_irq_init_x(unsigned int irq, bool keep_chip_data) |
3a16d713 | 22 | { |
0b8f1efa | 23 | struct irq_desc *desc; |
3a16d713 EB |
24 | unsigned long flags; |
25 | ||
0b8f1efa | 26 | desc = irq_to_desc(irq); |
7d94f7ca | 27 | if (!desc) { |
261c40c1 | 28 | WARN(1, KERN_ERR "Trying to initialize invalid IRQ%d\n", irq); |
3a16d713 EB |
29 | return; |
30 | } | |
31 | ||
32 | /* Ensure we don't have left over values from a previous use of this irq */ | |
239007b8 | 33 | raw_spin_lock_irqsave(&desc->lock, flags); |
3a16d713 | 34 | desc->status = IRQ_DISABLED; |
6b8ff312 | 35 | desc->irq_data.chip = &no_irq_chip; |
3a16d713 EB |
36 | desc->handle_irq = handle_bad_irq; |
37 | desc->depth = 1; | |
6b8ff312 TG |
38 | desc->irq_data.msi_desc = NULL; |
39 | desc->irq_data.handler_data = NULL; | |
ced5b697 | 40 | if (!keep_chip_data) |
6b8ff312 | 41 | desc->irq_data.chip_data = NULL; |
3a16d713 EB |
42 | desc->action = NULL; |
43 | desc->irq_count = 0; | |
44 | desc->irqs_unhandled = 0; | |
45 | #ifdef CONFIG_SMP | |
6b8ff312 | 46 | cpumask_setall(desc->irq_data.affinity); |
7f7ace0c MT |
47 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
48 | cpumask_clear(desc->pending_mask); | |
49 | #endif | |
3a16d713 | 50 | #endif |
239007b8 | 51 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3a16d713 EB |
52 | } |
53 | ||
54 | /** | |
ced5b697 | 55 | * dynamic_irq_init - initialize a dynamically allocated irq |
3a16d713 EB |
56 | * @irq: irq number to initialize |
57 | */ | |
ced5b697 BP |
58 | void dynamic_irq_init(unsigned int irq) |
59 | { | |
60 | dynamic_irq_init_x(irq, false); | |
61 | } | |
62 | ||
63 | /** | |
64 | * dynamic_irq_init_keep_chip_data - initialize a dynamically allocated irq | |
65 | * @irq: irq number to initialize | |
66 | * | |
6b8ff312 | 67 | * does not set irq_to_desc(irq)->irq_data.chip_data to NULL |
ced5b697 BP |
68 | */ |
69 | void dynamic_irq_init_keep_chip_data(unsigned int irq) | |
70 | { | |
71 | dynamic_irq_init_x(irq, true); | |
72 | } | |
73 | ||
74 | static void dynamic_irq_cleanup_x(unsigned int irq, bool keep_chip_data) | |
3a16d713 | 75 | { |
d3c60047 | 76 | struct irq_desc *desc = irq_to_desc(irq); |
3a16d713 EB |
77 | unsigned long flags; |
78 | ||
7d94f7ca | 79 | if (!desc) { |
261c40c1 | 80 | WARN(1, KERN_ERR "Trying to cleanup invalid IRQ%d\n", irq); |
3a16d713 EB |
81 | return; |
82 | } | |
83 | ||
239007b8 | 84 | raw_spin_lock_irqsave(&desc->lock, flags); |
1f80025e | 85 | if (desc->action) { |
239007b8 | 86 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
261c40c1 | 87 | WARN(1, KERN_ERR "Destroying IRQ%d without calling free_irq\n", |
1f80025e | 88 | irq); |
1f80025e EB |
89 | return; |
90 | } | |
6b8ff312 TG |
91 | desc->irq_data.msi_desc = NULL; |
92 | desc->irq_data.handler_data = NULL; | |
ced5b697 | 93 | if (!keep_chip_data) |
6b8ff312 | 94 | desc->irq_data.chip_data = NULL; |
3a16d713 | 95 | desc->handle_irq = handle_bad_irq; |
6b8ff312 | 96 | desc->irq_data.chip = &no_irq_chip; |
b6f3b780 | 97 | desc->name = NULL; |
0f3c2a89 | 98 | clear_kstat_irqs(desc); |
239007b8 | 99 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3a16d713 EB |
100 | } |
101 | ||
ced5b697 BP |
102 | /** |
103 | * dynamic_irq_cleanup - cleanup a dynamically allocated irq | |
104 | * @irq: irq number to initialize | |
105 | */ | |
106 | void dynamic_irq_cleanup(unsigned int irq) | |
107 | { | |
108 | dynamic_irq_cleanup_x(irq, false); | |
109 | } | |
110 | ||
111 | /** | |
112 | * dynamic_irq_cleanup_keep_chip_data - cleanup a dynamically allocated irq | |
113 | * @irq: irq number to initialize | |
114 | * | |
6b8ff312 | 115 | * does not set irq_to_desc(irq)->irq_data.chip_data to NULL |
ced5b697 BP |
116 | */ |
117 | void dynamic_irq_cleanup_keep_chip_data(unsigned int irq) | |
118 | { | |
119 | dynamic_irq_cleanup_x(irq, true); | |
120 | } | |
121 | ||
3a16d713 | 122 | |
dd87eb3a TG |
123 | /** |
124 | * set_irq_chip - set the irq chip for an irq | |
125 | * @irq: irq number | |
126 | * @chip: pointer to irq chip description structure | |
127 | */ | |
128 | int set_irq_chip(unsigned int irq, struct irq_chip *chip) | |
129 | { | |
d3c60047 | 130 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
131 | unsigned long flags; |
132 | ||
7d94f7ca | 133 | if (!desc) { |
261c40c1 | 134 | WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq); |
dd87eb3a TG |
135 | return -EINVAL; |
136 | } | |
137 | ||
138 | if (!chip) | |
139 | chip = &no_irq_chip; | |
140 | ||
239007b8 | 141 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a | 142 | irq_chip_set_defaults(chip); |
6b8ff312 | 143 | desc->irq_data.chip = chip; |
239007b8 | 144 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
145 | |
146 | return 0; | |
147 | } | |
148 | EXPORT_SYMBOL(set_irq_chip); | |
149 | ||
150 | /** | |
0c5d1eb7 | 151 | * set_irq_type - set the irq trigger type for an irq |
dd87eb3a | 152 | * @irq: irq number |
0c5d1eb7 | 153 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a TG |
154 | */ |
155 | int set_irq_type(unsigned int irq, unsigned int type) | |
156 | { | |
d3c60047 | 157 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
158 | unsigned long flags; |
159 | int ret = -ENXIO; | |
160 | ||
7d94f7ca | 161 | if (!desc) { |
dd87eb3a TG |
162 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); |
163 | return -ENODEV; | |
164 | } | |
165 | ||
f2b662da | 166 | type &= IRQ_TYPE_SENSE_MASK; |
0c5d1eb7 DB |
167 | if (type == IRQ_TYPE_NONE) |
168 | return 0; | |
169 | ||
239007b8 | 170 | raw_spin_lock_irqsave(&desc->lock, flags); |
0b3682ba | 171 | ret = __irq_set_trigger(desc, irq, type); |
239007b8 | 172 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
173 | return ret; |
174 | } | |
175 | EXPORT_SYMBOL(set_irq_type); | |
176 | ||
177 | /** | |
178 | * set_irq_data - set irq type data for an irq | |
179 | * @irq: Interrupt number | |
180 | * @data: Pointer to interrupt specific data | |
181 | * | |
182 | * Set the hardware irq controller data for an irq | |
183 | */ | |
184 | int set_irq_data(unsigned int irq, void *data) | |
185 | { | |
d3c60047 | 186 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
187 | unsigned long flags; |
188 | ||
7d94f7ca | 189 | if (!desc) { |
dd87eb3a TG |
190 | printk(KERN_ERR |
191 | "Trying to install controller data for IRQ%d\n", irq); | |
192 | return -EINVAL; | |
193 | } | |
194 | ||
239007b8 | 195 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 196 | desc->irq_data.handler_data = data; |
239007b8 | 197 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
198 | return 0; |
199 | } | |
200 | EXPORT_SYMBOL(set_irq_data); | |
201 | ||
5b912c10 | 202 | /** |
24b26d42 | 203 | * set_irq_msi - set MSI descriptor data for an irq |
5b912c10 | 204 | * @irq: Interrupt number |
472900b8 | 205 | * @entry: Pointer to MSI descriptor data |
5b912c10 | 206 | * |
24b26d42 | 207 | * Set the MSI descriptor entry for an irq |
5b912c10 EB |
208 | */ |
209 | int set_irq_msi(unsigned int irq, struct msi_desc *entry) | |
210 | { | |
d3c60047 | 211 | struct irq_desc *desc = irq_to_desc(irq); |
5b912c10 EB |
212 | unsigned long flags; |
213 | ||
7d94f7ca | 214 | if (!desc) { |
5b912c10 EB |
215 | printk(KERN_ERR |
216 | "Trying to install msi data for IRQ%d\n", irq); | |
217 | return -EINVAL; | |
218 | } | |
7d94f7ca | 219 | |
239007b8 | 220 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 221 | desc->irq_data.msi_desc = entry; |
7fe3730d ME |
222 | if (entry) |
223 | entry->irq = irq; | |
239007b8 | 224 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
5b912c10 EB |
225 | return 0; |
226 | } | |
227 | ||
dd87eb3a TG |
228 | /** |
229 | * set_irq_chip_data - set irq chip data for an irq | |
230 | * @irq: Interrupt number | |
231 | * @data: Pointer to chip specific data | |
232 | * | |
233 | * Set the hardware irq chip data for an irq | |
234 | */ | |
235 | int set_irq_chip_data(unsigned int irq, void *data) | |
236 | { | |
d3c60047 | 237 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
238 | unsigned long flags; |
239 | ||
7d94f7ca YL |
240 | if (!desc) { |
241 | printk(KERN_ERR | |
242 | "Trying to install chip data for IRQ%d\n", irq); | |
243 | return -EINVAL; | |
244 | } | |
245 | ||
6b8ff312 | 246 | if (!desc->irq_data.chip) { |
dd87eb3a TG |
247 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); |
248 | return -EINVAL; | |
249 | } | |
250 | ||
239007b8 | 251 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 252 | desc->irq_data.chip_data = data; |
239007b8 | 253 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
254 | |
255 | return 0; | |
256 | } | |
257 | EXPORT_SYMBOL(set_irq_chip_data); | |
258 | ||
399b5da2 TG |
259 | /** |
260 | * set_irq_nested_thread - Set/Reset the IRQ_NESTED_THREAD flag of an irq | |
261 | * | |
262 | * @irq: Interrupt number | |
263 | * @nest: 0 to clear / 1 to set the IRQ_NESTED_THREAD flag | |
264 | * | |
265 | * The IRQ_NESTED_THREAD flag indicates that on | |
266 | * request_threaded_irq() no separate interrupt thread should be | |
267 | * created for the irq as the handler are called nested in the | |
268 | * context of a demultiplexing interrupt handler thread. | |
269 | */ | |
270 | void set_irq_nested_thread(unsigned int irq, int nest) | |
271 | { | |
272 | struct irq_desc *desc = irq_to_desc(irq); | |
273 | unsigned long flags; | |
274 | ||
275 | if (!desc) | |
276 | return; | |
277 | ||
239007b8 | 278 | raw_spin_lock_irqsave(&desc->lock, flags); |
399b5da2 TG |
279 | if (nest) |
280 | desc->status |= IRQ_NESTED_THREAD; | |
281 | else | |
282 | desc->status &= ~IRQ_NESTED_THREAD; | |
239007b8 | 283 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
399b5da2 TG |
284 | } |
285 | EXPORT_SYMBOL_GPL(set_irq_nested_thread); | |
286 | ||
dd87eb3a TG |
287 | /* |
288 | * default enable function | |
289 | */ | |
c5f75634 | 290 | static void default_enable(struct irq_data *data) |
dd87eb3a | 291 | { |
c5f75634 | 292 | struct irq_desc *desc = irq_data_to_desc(data); |
dd87eb3a | 293 | |
0eda58b7 | 294 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
dd87eb3a TG |
295 | desc->status &= ~IRQ_MASKED; |
296 | } | |
297 | ||
298 | /* | |
299 | * default disable function | |
300 | */ | |
bc310dda | 301 | static void default_disable(struct irq_data *data) |
dd87eb3a | 302 | { |
dd87eb3a TG |
303 | } |
304 | ||
305 | /* | |
306 | * default startup function | |
307 | */ | |
37e12df7 | 308 | static unsigned int default_startup(struct irq_data *data) |
dd87eb3a | 309 | { |
37e12df7 | 310 | struct irq_desc *desc = irq_data_to_desc(data); |
08678b08 | 311 | |
37e12df7 | 312 | desc->irq_data.chip->irq_enable(data); |
dd87eb3a TG |
313 | return 0; |
314 | } | |
315 | ||
89d694b9 TG |
316 | /* |
317 | * default shutdown function | |
318 | */ | |
bc310dda | 319 | static void default_shutdown(struct irq_data *data) |
89d694b9 | 320 | { |
bc310dda | 321 | struct irq_desc *desc = irq_data_to_desc(data); |
89d694b9 | 322 | |
e2c0f8ff | 323 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
89d694b9 TG |
324 | desc->status |= IRQ_MASKED; |
325 | } | |
326 | ||
3876ec9e | 327 | /* Temporary migration helpers */ |
e2c0f8ff TG |
328 | static void compat_irq_mask(struct irq_data *data) |
329 | { | |
330 | data->chip->mask(data->irq); | |
331 | } | |
332 | ||
0eda58b7 TG |
333 | static void compat_irq_unmask(struct irq_data *data) |
334 | { | |
335 | data->chip->unmask(data->irq); | |
336 | } | |
337 | ||
22a49163 TG |
338 | static void compat_irq_ack(struct irq_data *data) |
339 | { | |
340 | data->chip->ack(data->irq); | |
341 | } | |
342 | ||
9205e31d TG |
343 | static void compat_irq_mask_ack(struct irq_data *data) |
344 | { | |
345 | data->chip->mask_ack(data->irq); | |
346 | } | |
347 | ||
0c5c1557 TG |
348 | static void compat_irq_eoi(struct irq_data *data) |
349 | { | |
350 | data->chip->eoi(data->irq); | |
351 | } | |
352 | ||
c5f75634 TG |
353 | static void compat_irq_enable(struct irq_data *data) |
354 | { | |
355 | data->chip->enable(data->irq); | |
356 | } | |
357 | ||
bc310dda TG |
358 | static void compat_irq_disable(struct irq_data *data) |
359 | { | |
360 | data->chip->disable(data->irq); | |
361 | } | |
362 | ||
363 | static void compat_irq_shutdown(struct irq_data *data) | |
364 | { | |
365 | data->chip->shutdown(data->irq); | |
366 | } | |
367 | ||
37e12df7 TG |
368 | static unsigned int compat_irq_startup(struct irq_data *data) |
369 | { | |
370 | return data->chip->startup(data->irq); | |
371 | } | |
372 | ||
3876ec9e TG |
373 | static void compat_bus_lock(struct irq_data *data) |
374 | { | |
375 | data->chip->bus_lock(data->irq); | |
376 | } | |
377 | ||
378 | static void compat_bus_sync_unlock(struct irq_data *data) | |
379 | { | |
380 | data->chip->bus_sync_unlock(data->irq); | |
381 | } | |
382 | ||
dd87eb3a TG |
383 | /* |
384 | * Fixup enable/disable function pointers | |
385 | */ | |
386 | void irq_chip_set_defaults(struct irq_chip *chip) | |
387 | { | |
c5f75634 TG |
388 | /* |
389 | * Compat fixup functions need to be before we set the | |
390 | * defaults for enable/disable/startup/shutdown | |
391 | */ | |
392 | if (chip->enable) | |
393 | chip->irq_enable = compat_irq_enable; | |
bc310dda TG |
394 | if (chip->disable) |
395 | chip->irq_disable = compat_irq_disable; | |
396 | if (chip->shutdown) | |
397 | chip->irq_shutdown = compat_irq_shutdown; | |
37e12df7 TG |
398 | if (chip->startup) |
399 | chip->irq_startup = compat_irq_startup; | |
c5f75634 TG |
400 | |
401 | /* | |
402 | * The real defaults | |
403 | */ | |
404 | if (!chip->irq_enable) | |
405 | chip->irq_enable = default_enable; | |
bc310dda TG |
406 | if (!chip->irq_disable) |
407 | chip->irq_disable = default_disable; | |
37e12df7 TG |
408 | if (!chip->irq_startup) |
409 | chip->irq_startup = default_startup; | |
89d694b9 | 410 | /* |
bc310dda TG |
411 | * We use chip->irq_disable, when the user provided its own. When |
412 | * we have default_disable set for chip->irq_disable, then we need | |
89d694b9 TG |
413 | * to use default_shutdown, otherwise the irq line is not |
414 | * disabled on free_irq(): | |
415 | */ | |
bc310dda TG |
416 | if (!chip->irq_shutdown) |
417 | chip->irq_shutdown = chip->irq_disable != default_disable ? | |
418 | chip->irq_disable : default_shutdown; | |
b86432b4 ZY |
419 | if (!chip->end) |
420 | chip->end = dummy_irq_chip.end; | |
3876ec9e | 421 | |
bc310dda TG |
422 | /* |
423 | * Now fix up the remaining compat handlers | |
424 | */ | |
3876ec9e TG |
425 | if (chip->bus_lock) |
426 | chip->irq_bus_lock = compat_bus_lock; | |
427 | if (chip->bus_sync_unlock) | |
428 | chip->irq_bus_sync_unlock = compat_bus_sync_unlock; | |
e2c0f8ff TG |
429 | if (chip->mask) |
430 | chip->irq_mask = compat_irq_mask; | |
0eda58b7 TG |
431 | if (chip->unmask) |
432 | chip->irq_unmask = compat_irq_unmask; | |
22a49163 TG |
433 | if (chip->ack) |
434 | chip->irq_ack = compat_irq_ack; | |
9205e31d TG |
435 | if (chip->mask_ack) |
436 | chip->irq_mask_ack = compat_irq_mask_ack; | |
0c5c1557 TG |
437 | if (chip->eoi) |
438 | chip->irq_eoi = compat_irq_eoi; | |
dd87eb3a TG |
439 | } |
440 | ||
9205e31d | 441 | static inline void mask_ack_irq(struct irq_desc *desc) |
dd87eb3a | 442 | { |
9205e31d TG |
443 | if (desc->irq_data.chip->irq_mask_ack) |
444 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | |
dd87eb3a | 445 | else { |
e2c0f8ff | 446 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
22a49163 TG |
447 | if (desc->irq_data.chip->irq_ack) |
448 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 449 | } |
0b1adaa0 TG |
450 | desc->status |= IRQ_MASKED; |
451 | } | |
452 | ||
e2c0f8ff | 453 | static inline void mask_irq(struct irq_desc *desc) |
0b1adaa0 | 454 | { |
e2c0f8ff TG |
455 | if (desc->irq_data.chip->irq_mask) { |
456 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
0b1adaa0 TG |
457 | desc->status |= IRQ_MASKED; |
458 | } | |
459 | } | |
460 | ||
0eda58b7 | 461 | static inline void unmask_irq(struct irq_desc *desc) |
0b1adaa0 | 462 | { |
0eda58b7 TG |
463 | if (desc->irq_data.chip->irq_unmask) { |
464 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
0b1adaa0 TG |
465 | desc->status &= ~IRQ_MASKED; |
466 | } | |
dd87eb3a TG |
467 | } |
468 | ||
399b5da2 TG |
469 | /* |
470 | * handle_nested_irq - Handle a nested irq from a irq thread | |
471 | * @irq: the interrupt number | |
472 | * | |
473 | * Handle interrupts which are nested into a threaded interrupt | |
474 | * handler. The handler function is called inside the calling | |
475 | * threads context. | |
476 | */ | |
477 | void handle_nested_irq(unsigned int irq) | |
478 | { | |
479 | struct irq_desc *desc = irq_to_desc(irq); | |
480 | struct irqaction *action; | |
481 | irqreturn_t action_ret; | |
482 | ||
483 | might_sleep(); | |
484 | ||
239007b8 | 485 | raw_spin_lock_irq(&desc->lock); |
399b5da2 TG |
486 | |
487 | kstat_incr_irqs_this_cpu(irq, desc); | |
488 | ||
489 | action = desc->action; | |
490 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) | |
491 | goto out_unlock; | |
492 | ||
493 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 494 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
495 | |
496 | action_ret = action->thread_fn(action->irq, action->dev_id); | |
497 | if (!noirqdebug) | |
498 | note_interrupt(irq, desc, action_ret); | |
499 | ||
239007b8 | 500 | raw_spin_lock_irq(&desc->lock); |
399b5da2 TG |
501 | desc->status &= ~IRQ_INPROGRESS; |
502 | ||
503 | out_unlock: | |
239007b8 | 504 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
505 | } |
506 | EXPORT_SYMBOL_GPL(handle_nested_irq); | |
507 | ||
dd87eb3a TG |
508 | /** |
509 | * handle_simple_irq - Simple and software-decoded IRQs. | |
510 | * @irq: the interrupt number | |
511 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
512 | * |
513 | * Simple interrupts are either sent from a demultiplexing interrupt | |
514 | * handler or come from hardware, where no interrupt hardware control | |
515 | * is necessary. | |
516 | * | |
517 | * Note: The caller is expected to handle the ack, clear, mask and | |
518 | * unmask issues if necessary. | |
519 | */ | |
7ad5b3a5 | 520 | void |
7d12e780 | 521 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
522 | { |
523 | struct irqaction *action; | |
524 | irqreturn_t action_ret; | |
dd87eb3a | 525 | |
239007b8 | 526 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
527 | |
528 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
529 | goto out_unlock; | |
971e5b35 | 530 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
d6c88a50 | 531 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
532 | |
533 | action = desc->action; | |
971e5b35 | 534 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
dd87eb3a TG |
535 | goto out_unlock; |
536 | ||
537 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 538 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 539 | |
7d12e780 | 540 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 541 | if (!noirqdebug) |
7d12e780 | 542 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 543 | |
239007b8 | 544 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
545 | desc->status &= ~IRQ_INPROGRESS; |
546 | out_unlock: | |
239007b8 | 547 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
548 | } |
549 | ||
550 | /** | |
551 | * handle_level_irq - Level type irq handler | |
552 | * @irq: the interrupt number | |
553 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
554 | * |
555 | * Level type interrupts are active as long as the hardware line has | |
556 | * the active level. This may require to mask the interrupt and unmask | |
557 | * it after the associated handler has acknowledged the device, so the | |
558 | * interrupt line is back to inactive. | |
559 | */ | |
7ad5b3a5 | 560 | void |
7d12e780 | 561 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 562 | { |
dd87eb3a TG |
563 | struct irqaction *action; |
564 | irqreturn_t action_ret; | |
565 | ||
239007b8 | 566 | raw_spin_lock(&desc->lock); |
9205e31d | 567 | mask_ack_irq(desc); |
dd87eb3a TG |
568 | |
569 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
86998aa6 | 570 | goto out_unlock; |
dd87eb3a | 571 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
d6c88a50 | 572 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
573 | |
574 | /* | |
575 | * If its disabled or no action available | |
576 | * keep it masked and get out of here | |
577 | */ | |
578 | action = desc->action; | |
49663421 | 579 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
86998aa6 | 580 | goto out_unlock; |
dd87eb3a TG |
581 | |
582 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 583 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 584 | |
7d12e780 | 585 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 586 | if (!noirqdebug) |
7d12e780 | 587 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 588 | |
239007b8 | 589 | raw_spin_lock(&desc->lock); |
dd87eb3a | 590 | desc->status &= ~IRQ_INPROGRESS; |
b25c340c | 591 | |
0b1adaa0 | 592 | if (!(desc->status & (IRQ_DISABLED | IRQ_ONESHOT))) |
0eda58b7 | 593 | unmask_irq(desc); |
86998aa6 | 594 | out_unlock: |
239007b8 | 595 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 596 | } |
14819ea1 | 597 | EXPORT_SYMBOL_GPL(handle_level_irq); |
dd87eb3a TG |
598 | |
599 | /** | |
47c2a3aa | 600 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
601 | * @irq: the interrupt number |
602 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 603 | * |
47c2a3aa | 604 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
605 | * call when the interrupt has been serviced. This enables support |
606 | * for modern forms of interrupt handlers, which handle the flow | |
607 | * details in hardware, transparently. | |
608 | */ | |
7ad5b3a5 | 609 | void |
7d12e780 | 610 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 611 | { |
dd87eb3a TG |
612 | struct irqaction *action; |
613 | irqreturn_t action_ret; | |
614 | ||
239007b8 | 615 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
616 | |
617 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
618 | goto out; | |
619 | ||
620 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
d6c88a50 | 621 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
622 | |
623 | /* | |
624 | * If its disabled or no action available | |
76d21601 | 625 | * then mask it and get out of here: |
dd87eb3a TG |
626 | */ |
627 | action = desc->action; | |
98bb244b BH |
628 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
629 | desc->status |= IRQ_PENDING; | |
e2c0f8ff | 630 | mask_irq(desc); |
dd87eb3a | 631 | goto out; |
98bb244b | 632 | } |
dd87eb3a TG |
633 | |
634 | desc->status |= IRQ_INPROGRESS; | |
98bb244b | 635 | desc->status &= ~IRQ_PENDING; |
239007b8 | 636 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 637 | |
7d12e780 | 638 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 639 | if (!noirqdebug) |
7d12e780 | 640 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 641 | |
239007b8 | 642 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
643 | desc->status &= ~IRQ_INPROGRESS; |
644 | out: | |
0c5c1557 | 645 | desc->irq_data.chip->irq_eoi(&desc->irq_data); |
dd87eb3a | 646 | |
239007b8 | 647 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
648 | } |
649 | ||
650 | /** | |
651 | * handle_edge_irq - edge type IRQ handler | |
652 | * @irq: the interrupt number | |
653 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
654 | * |
655 | * Interrupt occures on the falling and/or rising edge of a hardware | |
656 | * signal. The occurence is latched into the irq controller hardware | |
657 | * and must be acked in order to be reenabled. After the ack another | |
658 | * interrupt can happen on the same source even before the first one | |
dfff0615 | 659 | * is handled by the associated event handler. If this happens it |
dd87eb3a TG |
660 | * might be necessary to disable (mask) the interrupt depending on the |
661 | * controller hardware. This requires to reenable the interrupt inside | |
662 | * of the loop which handles the interrupts which have arrived while | |
663 | * the handler was running. If all pending interrupts are handled, the | |
664 | * loop is left. | |
665 | */ | |
7ad5b3a5 | 666 | void |
7d12e780 | 667 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 668 | { |
239007b8 | 669 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
670 | |
671 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
672 | ||
673 | /* | |
674 | * If we're currently running this IRQ, or its disabled, | |
675 | * we shouldn't process the IRQ. Mark it pending, handle | |
676 | * the necessary masking and go out | |
677 | */ | |
678 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || | |
679 | !desc->action)) { | |
680 | desc->status |= (IRQ_PENDING | IRQ_MASKED); | |
9205e31d | 681 | mask_ack_irq(desc); |
dd87eb3a TG |
682 | goto out_unlock; |
683 | } | |
d6c88a50 | 684 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
685 | |
686 | /* Start handling the irq */ | |
22a49163 | 687 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
dd87eb3a TG |
688 | |
689 | /* Mark the IRQ currently in progress.*/ | |
690 | desc->status |= IRQ_INPROGRESS; | |
691 | ||
692 | do { | |
693 | struct irqaction *action = desc->action; | |
694 | irqreturn_t action_ret; | |
695 | ||
696 | if (unlikely(!action)) { | |
e2c0f8ff | 697 | mask_irq(desc); |
dd87eb3a TG |
698 | goto out_unlock; |
699 | } | |
700 | ||
701 | /* | |
702 | * When another irq arrived while we were handling | |
703 | * one, we could have masked the irq. | |
704 | * Renable it, if it was not disabled in meantime. | |
705 | */ | |
706 | if (unlikely((desc->status & | |
707 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == | |
708 | (IRQ_PENDING | IRQ_MASKED))) { | |
0eda58b7 | 709 | unmask_irq(desc); |
dd87eb3a TG |
710 | } |
711 | ||
712 | desc->status &= ~IRQ_PENDING; | |
239007b8 | 713 | raw_spin_unlock(&desc->lock); |
7d12e780 | 714 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 715 | if (!noirqdebug) |
7d12e780 | 716 | note_interrupt(irq, desc, action_ret); |
239007b8 | 717 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
718 | |
719 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); | |
720 | ||
721 | desc->status &= ~IRQ_INPROGRESS; | |
722 | out_unlock: | |
239007b8 | 723 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
724 | } |
725 | ||
dd87eb3a | 726 | /** |
24b26d42 | 727 | * handle_percpu_irq - Per CPU local irq handler |
dd87eb3a TG |
728 | * @irq: the interrupt number |
729 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
730 | * |
731 | * Per CPU interrupts on SMP machines without locking requirements | |
732 | */ | |
7ad5b3a5 | 733 | void |
7d12e780 | 734 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
735 | { |
736 | irqreturn_t action_ret; | |
737 | ||
d6c88a50 | 738 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a | 739 | |
22a49163 TG |
740 | if (desc->irq_data.chip->irq_ack) |
741 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 742 | |
7d12e780 | 743 | action_ret = handle_IRQ_event(irq, desc->action); |
dd87eb3a | 744 | if (!noirqdebug) |
7d12e780 | 745 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 746 | |
0c5c1557 TG |
747 | if (desc->irq_data.chip->irq_eoi) |
748 | desc->irq_data.chip->irq_eoi(&desc->irq_data); | |
dd87eb3a TG |
749 | } |
750 | ||
dd87eb3a | 751 | void |
a460e745 IM |
752 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
753 | const char *name) | |
dd87eb3a | 754 | { |
d3c60047 | 755 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
756 | unsigned long flags; |
757 | ||
7d94f7ca | 758 | if (!desc) { |
dd87eb3a TG |
759 | printk(KERN_ERR |
760 | "Trying to install type control for IRQ%d\n", irq); | |
761 | return; | |
762 | } | |
763 | ||
dd87eb3a TG |
764 | if (!handle) |
765 | handle = handle_bad_irq; | |
6b8ff312 | 766 | else if (desc->irq_data.chip == &no_irq_chip) { |
f8b5473f | 767 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
b039db8e | 768 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
f8b5473f TG |
769 | /* |
770 | * Some ARM implementations install a handler for really dumb | |
771 | * interrupt hardware without setting an irq_chip. This worked | |
772 | * with the ARM no_irq_chip but the check in setup_irq would | |
773 | * prevent us to setup the interrupt at all. Switch it to | |
774 | * dummy_irq_chip for easy transition. | |
775 | */ | |
6b8ff312 | 776 | desc->irq_data.chip = &dummy_irq_chip; |
f8b5473f | 777 | } |
dd87eb3a | 778 | |
3876ec9e | 779 | chip_bus_lock(desc); |
239007b8 | 780 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a TG |
781 | |
782 | /* Uninstall? */ | |
783 | if (handle == handle_bad_irq) { | |
6b8ff312 | 784 | if (desc->irq_data.chip != &no_irq_chip) |
9205e31d | 785 | mask_ack_irq(desc); |
dd87eb3a TG |
786 | desc->status |= IRQ_DISABLED; |
787 | desc->depth = 1; | |
788 | } | |
789 | desc->handle_irq = handle; | |
a460e745 | 790 | desc->name = name; |
dd87eb3a TG |
791 | |
792 | if (handle != handle_bad_irq && is_chained) { | |
793 | desc->status &= ~IRQ_DISABLED; | |
794 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; | |
795 | desc->depth = 0; | |
37e12df7 | 796 | desc->irq_data.chip->irq_startup(&desc->irq_data); |
dd87eb3a | 797 | } |
239007b8 | 798 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3876ec9e | 799 | chip_bus_sync_unlock(desc); |
dd87eb3a | 800 | } |
14819ea1 | 801 | EXPORT_SYMBOL_GPL(__set_irq_handler); |
dd87eb3a TG |
802 | |
803 | void | |
804 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
57a58a94 | 805 | irq_flow_handler_t handle) |
dd87eb3a TG |
806 | { |
807 | set_irq_chip(irq, chip); | |
a460e745 | 808 | __set_irq_handler(irq, handle, 0, NULL); |
dd87eb3a TG |
809 | } |
810 | ||
a460e745 IM |
811 | void |
812 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | |
813 | irq_flow_handler_t handle, const char *name) | |
dd87eb3a | 814 | { |
a460e745 IM |
815 | set_irq_chip(irq, chip); |
816 | __set_irq_handler(irq, handle, 0, name); | |
dd87eb3a | 817 | } |
46f4f8f6 | 818 | |
860652bf | 819 | void set_irq_noprobe(unsigned int irq) |
46f4f8f6 | 820 | { |
d3c60047 | 821 | struct irq_desc *desc = irq_to_desc(irq); |
46f4f8f6 RB |
822 | unsigned long flags; |
823 | ||
7d94f7ca | 824 | if (!desc) { |
46f4f8f6 | 825 | printk(KERN_ERR "Trying to mark IRQ%d non-probeable\n", irq); |
46f4f8f6 RB |
826 | return; |
827 | } | |
828 | ||
239007b8 | 829 | raw_spin_lock_irqsave(&desc->lock, flags); |
46f4f8f6 | 830 | desc->status |= IRQ_NOPROBE; |
239007b8 | 831 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
46f4f8f6 RB |
832 | } |
833 | ||
860652bf | 834 | void set_irq_probe(unsigned int irq) |
46f4f8f6 | 835 | { |
d3c60047 | 836 | struct irq_desc *desc = irq_to_desc(irq); |
46f4f8f6 RB |
837 | unsigned long flags; |
838 | ||
7d94f7ca | 839 | if (!desc) { |
46f4f8f6 | 840 | printk(KERN_ERR "Trying to mark IRQ%d probeable\n", irq); |
46f4f8f6 RB |
841 | return; |
842 | } | |
843 | ||
239007b8 | 844 | raw_spin_lock_irqsave(&desc->lock, flags); |
46f4f8f6 | 845 | desc->status &= ~IRQ_NOPROBE; |
239007b8 | 846 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
46f4f8f6 | 847 | } |