]>
Commit | Line | Data |
---|---|---|
dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
18 | ||
19 | #include "internals.h" | |
20 | ||
21 | /** | |
22 | * set_irq_chip - set the irq chip for an irq | |
23 | * @irq: irq number | |
24 | * @chip: pointer to irq chip description structure | |
25 | */ | |
26 | int set_irq_chip(unsigned int irq, struct irq_chip *chip) | |
27 | { | |
d3c60047 | 28 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
29 | unsigned long flags; |
30 | ||
7d94f7ca | 31 | if (!desc) { |
261c40c1 | 32 | WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq); |
dd87eb3a TG |
33 | return -EINVAL; |
34 | } | |
35 | ||
36 | if (!chip) | |
37 | chip = &no_irq_chip; | |
38 | ||
239007b8 | 39 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a | 40 | irq_chip_set_defaults(chip); |
6b8ff312 | 41 | desc->irq_data.chip = chip; |
239007b8 | 42 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
43 | |
44 | return 0; | |
45 | } | |
46 | EXPORT_SYMBOL(set_irq_chip); | |
47 | ||
48 | /** | |
0c5d1eb7 | 49 | * set_irq_type - set the irq trigger type for an irq |
dd87eb3a | 50 | * @irq: irq number |
0c5d1eb7 | 51 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a TG |
52 | */ |
53 | int set_irq_type(unsigned int irq, unsigned int type) | |
54 | { | |
d3c60047 | 55 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
56 | unsigned long flags; |
57 | int ret = -ENXIO; | |
58 | ||
7d94f7ca | 59 | if (!desc) { |
dd87eb3a TG |
60 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); |
61 | return -ENODEV; | |
62 | } | |
63 | ||
f2b662da | 64 | type &= IRQ_TYPE_SENSE_MASK; |
0c5d1eb7 DB |
65 | if (type == IRQ_TYPE_NONE) |
66 | return 0; | |
67 | ||
43abe43c | 68 | chip_bus_lock(desc); |
239007b8 | 69 | raw_spin_lock_irqsave(&desc->lock, flags); |
0b3682ba | 70 | ret = __irq_set_trigger(desc, irq, type); |
239007b8 | 71 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
43abe43c | 72 | chip_bus_sync_unlock(desc); |
dd87eb3a TG |
73 | return ret; |
74 | } | |
75 | EXPORT_SYMBOL(set_irq_type); | |
76 | ||
77 | /** | |
78 | * set_irq_data - set irq type data for an irq | |
79 | * @irq: Interrupt number | |
80 | * @data: Pointer to interrupt specific data | |
81 | * | |
82 | * Set the hardware irq controller data for an irq | |
83 | */ | |
84 | int set_irq_data(unsigned int irq, void *data) | |
85 | { | |
d3c60047 | 86 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
87 | unsigned long flags; |
88 | ||
7d94f7ca | 89 | if (!desc) { |
dd87eb3a TG |
90 | printk(KERN_ERR |
91 | "Trying to install controller data for IRQ%d\n", irq); | |
92 | return -EINVAL; | |
93 | } | |
94 | ||
239007b8 | 95 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 96 | desc->irq_data.handler_data = data; |
239007b8 | 97 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
98 | return 0; |
99 | } | |
100 | EXPORT_SYMBOL(set_irq_data); | |
101 | ||
5b912c10 | 102 | /** |
24b26d42 | 103 | * set_irq_msi - set MSI descriptor data for an irq |
5b912c10 | 104 | * @irq: Interrupt number |
472900b8 | 105 | * @entry: Pointer to MSI descriptor data |
5b912c10 | 106 | * |
24b26d42 | 107 | * Set the MSI descriptor entry for an irq |
5b912c10 EB |
108 | */ |
109 | int set_irq_msi(unsigned int irq, struct msi_desc *entry) | |
110 | { | |
d3c60047 | 111 | struct irq_desc *desc = irq_to_desc(irq); |
5b912c10 EB |
112 | unsigned long flags; |
113 | ||
7d94f7ca | 114 | if (!desc) { |
5b912c10 EB |
115 | printk(KERN_ERR |
116 | "Trying to install msi data for IRQ%d\n", irq); | |
117 | return -EINVAL; | |
118 | } | |
7d94f7ca | 119 | |
239007b8 | 120 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 121 | desc->irq_data.msi_desc = entry; |
7fe3730d ME |
122 | if (entry) |
123 | entry->irq = irq; | |
239007b8 | 124 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
5b912c10 EB |
125 | return 0; |
126 | } | |
127 | ||
dd87eb3a TG |
128 | /** |
129 | * set_irq_chip_data - set irq chip data for an irq | |
130 | * @irq: Interrupt number | |
131 | * @data: Pointer to chip specific data | |
132 | * | |
133 | * Set the hardware irq chip data for an irq | |
134 | */ | |
135 | int set_irq_chip_data(unsigned int irq, void *data) | |
136 | { | |
d3c60047 | 137 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
138 | unsigned long flags; |
139 | ||
7d94f7ca YL |
140 | if (!desc) { |
141 | printk(KERN_ERR | |
142 | "Trying to install chip data for IRQ%d\n", irq); | |
143 | return -EINVAL; | |
144 | } | |
145 | ||
6b8ff312 | 146 | if (!desc->irq_data.chip) { |
dd87eb3a TG |
147 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); |
148 | return -EINVAL; | |
149 | } | |
150 | ||
239007b8 | 151 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 152 | desc->irq_data.chip_data = data; |
239007b8 | 153 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
154 | |
155 | return 0; | |
156 | } | |
157 | EXPORT_SYMBOL(set_irq_chip_data); | |
158 | ||
f303a6dd TG |
159 | struct irq_data *irq_get_irq_data(unsigned int irq) |
160 | { | |
161 | struct irq_desc *desc = irq_to_desc(irq); | |
162 | ||
163 | return desc ? &desc->irq_data : NULL; | |
164 | } | |
165 | EXPORT_SYMBOL_GPL(irq_get_irq_data); | |
166 | ||
399b5da2 TG |
167 | /** |
168 | * set_irq_nested_thread - Set/Reset the IRQ_NESTED_THREAD flag of an irq | |
169 | * | |
170 | * @irq: Interrupt number | |
171 | * @nest: 0 to clear / 1 to set the IRQ_NESTED_THREAD flag | |
172 | * | |
173 | * The IRQ_NESTED_THREAD flag indicates that on | |
174 | * request_threaded_irq() no separate interrupt thread should be | |
175 | * created for the irq as the handler are called nested in the | |
176 | * context of a demultiplexing interrupt handler thread. | |
177 | */ | |
178 | void set_irq_nested_thread(unsigned int irq, int nest) | |
179 | { | |
180 | struct irq_desc *desc = irq_to_desc(irq); | |
181 | unsigned long flags; | |
182 | ||
183 | if (!desc) | |
184 | return; | |
185 | ||
239007b8 | 186 | raw_spin_lock_irqsave(&desc->lock, flags); |
399b5da2 TG |
187 | if (nest) |
188 | desc->status |= IRQ_NESTED_THREAD; | |
189 | else | |
190 | desc->status &= ~IRQ_NESTED_THREAD; | |
239007b8 | 191 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
399b5da2 TG |
192 | } |
193 | EXPORT_SYMBOL_GPL(set_irq_nested_thread); | |
194 | ||
dd87eb3a TG |
195 | /* |
196 | * default enable function | |
197 | */ | |
c5f75634 | 198 | static void default_enable(struct irq_data *data) |
dd87eb3a | 199 | { |
c5f75634 | 200 | struct irq_desc *desc = irq_data_to_desc(data); |
dd87eb3a | 201 | |
0eda58b7 | 202 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
dd87eb3a TG |
203 | desc->status &= ~IRQ_MASKED; |
204 | } | |
205 | ||
206 | /* | |
207 | * default disable function | |
208 | */ | |
bc310dda | 209 | static void default_disable(struct irq_data *data) |
dd87eb3a | 210 | { |
dd87eb3a TG |
211 | } |
212 | ||
213 | /* | |
214 | * default startup function | |
215 | */ | |
37e12df7 | 216 | static unsigned int default_startup(struct irq_data *data) |
dd87eb3a | 217 | { |
37e12df7 | 218 | struct irq_desc *desc = irq_data_to_desc(data); |
08678b08 | 219 | |
37e12df7 | 220 | desc->irq_data.chip->irq_enable(data); |
dd87eb3a TG |
221 | return 0; |
222 | } | |
223 | ||
89d694b9 TG |
224 | /* |
225 | * default shutdown function | |
226 | */ | |
bc310dda | 227 | static void default_shutdown(struct irq_data *data) |
89d694b9 | 228 | { |
bc310dda | 229 | struct irq_desc *desc = irq_data_to_desc(data); |
89d694b9 | 230 | |
e2c0f8ff | 231 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
89d694b9 TG |
232 | desc->status |= IRQ_MASKED; |
233 | } | |
234 | ||
bd151412 | 235 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
3876ec9e | 236 | /* Temporary migration helpers */ |
e2c0f8ff TG |
237 | static void compat_irq_mask(struct irq_data *data) |
238 | { | |
239 | data->chip->mask(data->irq); | |
240 | } | |
241 | ||
0eda58b7 TG |
242 | static void compat_irq_unmask(struct irq_data *data) |
243 | { | |
244 | data->chip->unmask(data->irq); | |
245 | } | |
246 | ||
22a49163 TG |
247 | static void compat_irq_ack(struct irq_data *data) |
248 | { | |
249 | data->chip->ack(data->irq); | |
250 | } | |
251 | ||
9205e31d TG |
252 | static void compat_irq_mask_ack(struct irq_data *data) |
253 | { | |
254 | data->chip->mask_ack(data->irq); | |
255 | } | |
256 | ||
0c5c1557 TG |
257 | static void compat_irq_eoi(struct irq_data *data) |
258 | { | |
259 | data->chip->eoi(data->irq); | |
260 | } | |
261 | ||
c5f75634 TG |
262 | static void compat_irq_enable(struct irq_data *data) |
263 | { | |
264 | data->chip->enable(data->irq); | |
265 | } | |
266 | ||
bc310dda TG |
267 | static void compat_irq_disable(struct irq_data *data) |
268 | { | |
269 | data->chip->disable(data->irq); | |
270 | } | |
271 | ||
272 | static void compat_irq_shutdown(struct irq_data *data) | |
273 | { | |
274 | data->chip->shutdown(data->irq); | |
275 | } | |
276 | ||
37e12df7 TG |
277 | static unsigned int compat_irq_startup(struct irq_data *data) |
278 | { | |
279 | return data->chip->startup(data->irq); | |
280 | } | |
281 | ||
c96b3b3c TG |
282 | static int compat_irq_set_affinity(struct irq_data *data, |
283 | const struct cpumask *dest, bool force) | |
284 | { | |
285 | return data->chip->set_affinity(data->irq, dest); | |
286 | } | |
287 | ||
b2ba2c30 TG |
288 | static int compat_irq_set_type(struct irq_data *data, unsigned int type) |
289 | { | |
290 | return data->chip->set_type(data->irq, type); | |
291 | } | |
292 | ||
2f7e99bb TG |
293 | static int compat_irq_set_wake(struct irq_data *data, unsigned int on) |
294 | { | |
295 | return data->chip->set_wake(data->irq, on); | |
296 | } | |
297 | ||
21e2b8c6 TG |
298 | static int compat_irq_retrigger(struct irq_data *data) |
299 | { | |
300 | return data->chip->retrigger(data->irq); | |
301 | } | |
302 | ||
3876ec9e TG |
303 | static void compat_bus_lock(struct irq_data *data) |
304 | { | |
305 | data->chip->bus_lock(data->irq); | |
306 | } | |
307 | ||
308 | static void compat_bus_sync_unlock(struct irq_data *data) | |
309 | { | |
310 | data->chip->bus_sync_unlock(data->irq); | |
311 | } | |
bd151412 | 312 | #endif |
3876ec9e | 313 | |
dd87eb3a TG |
314 | /* |
315 | * Fixup enable/disable function pointers | |
316 | */ | |
317 | void irq_chip_set_defaults(struct irq_chip *chip) | |
318 | { | |
bd151412 | 319 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
c5f75634 TG |
320 | /* |
321 | * Compat fixup functions need to be before we set the | |
322 | * defaults for enable/disable/startup/shutdown | |
323 | */ | |
324 | if (chip->enable) | |
325 | chip->irq_enable = compat_irq_enable; | |
bc310dda TG |
326 | if (chip->disable) |
327 | chip->irq_disable = compat_irq_disable; | |
328 | if (chip->shutdown) | |
329 | chip->irq_shutdown = compat_irq_shutdown; | |
37e12df7 TG |
330 | if (chip->startup) |
331 | chip->irq_startup = compat_irq_startup; | |
bd151412 | 332 | #endif |
c5f75634 TG |
333 | /* |
334 | * The real defaults | |
335 | */ | |
336 | if (!chip->irq_enable) | |
337 | chip->irq_enable = default_enable; | |
bc310dda TG |
338 | if (!chip->irq_disable) |
339 | chip->irq_disable = default_disable; | |
37e12df7 TG |
340 | if (!chip->irq_startup) |
341 | chip->irq_startup = default_startup; | |
89d694b9 | 342 | /* |
bc310dda TG |
343 | * We use chip->irq_disable, when the user provided its own. When |
344 | * we have default_disable set for chip->irq_disable, then we need | |
89d694b9 TG |
345 | * to use default_shutdown, otherwise the irq line is not |
346 | * disabled on free_irq(): | |
347 | */ | |
bc310dda TG |
348 | if (!chip->irq_shutdown) |
349 | chip->irq_shutdown = chip->irq_disable != default_disable ? | |
350 | chip->irq_disable : default_shutdown; | |
bd151412 TG |
351 | |
352 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED | |
b86432b4 ZY |
353 | if (!chip->end) |
354 | chip->end = dummy_irq_chip.end; | |
3876ec9e | 355 | |
bc310dda TG |
356 | /* |
357 | * Now fix up the remaining compat handlers | |
358 | */ | |
3876ec9e TG |
359 | if (chip->bus_lock) |
360 | chip->irq_bus_lock = compat_bus_lock; | |
361 | if (chip->bus_sync_unlock) | |
362 | chip->irq_bus_sync_unlock = compat_bus_sync_unlock; | |
e2c0f8ff TG |
363 | if (chip->mask) |
364 | chip->irq_mask = compat_irq_mask; | |
0eda58b7 TG |
365 | if (chip->unmask) |
366 | chip->irq_unmask = compat_irq_unmask; | |
22a49163 TG |
367 | if (chip->ack) |
368 | chip->irq_ack = compat_irq_ack; | |
9205e31d TG |
369 | if (chip->mask_ack) |
370 | chip->irq_mask_ack = compat_irq_mask_ack; | |
0c5c1557 TG |
371 | if (chip->eoi) |
372 | chip->irq_eoi = compat_irq_eoi; | |
c96b3b3c TG |
373 | if (chip->set_affinity) |
374 | chip->irq_set_affinity = compat_irq_set_affinity; | |
b2ba2c30 TG |
375 | if (chip->set_type) |
376 | chip->irq_set_type = compat_irq_set_type; | |
2f7e99bb TG |
377 | if (chip->set_wake) |
378 | chip->irq_set_wake = compat_irq_set_wake; | |
21e2b8c6 TG |
379 | if (chip->retrigger) |
380 | chip->irq_retrigger = compat_irq_retrigger; | |
bd151412 | 381 | #endif |
dd87eb3a TG |
382 | } |
383 | ||
9205e31d | 384 | static inline void mask_ack_irq(struct irq_desc *desc) |
dd87eb3a | 385 | { |
9205e31d TG |
386 | if (desc->irq_data.chip->irq_mask_ack) |
387 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | |
dd87eb3a | 388 | else { |
e2c0f8ff | 389 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
22a49163 TG |
390 | if (desc->irq_data.chip->irq_ack) |
391 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 392 | } |
0b1adaa0 TG |
393 | desc->status |= IRQ_MASKED; |
394 | } | |
395 | ||
e2c0f8ff | 396 | static inline void mask_irq(struct irq_desc *desc) |
0b1adaa0 | 397 | { |
e2c0f8ff TG |
398 | if (desc->irq_data.chip->irq_mask) { |
399 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
0b1adaa0 TG |
400 | desc->status |= IRQ_MASKED; |
401 | } | |
402 | } | |
403 | ||
0eda58b7 | 404 | static inline void unmask_irq(struct irq_desc *desc) |
0b1adaa0 | 405 | { |
0eda58b7 TG |
406 | if (desc->irq_data.chip->irq_unmask) { |
407 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
0b1adaa0 TG |
408 | desc->status &= ~IRQ_MASKED; |
409 | } | |
dd87eb3a TG |
410 | } |
411 | ||
399b5da2 TG |
412 | /* |
413 | * handle_nested_irq - Handle a nested irq from a irq thread | |
414 | * @irq: the interrupt number | |
415 | * | |
416 | * Handle interrupts which are nested into a threaded interrupt | |
417 | * handler. The handler function is called inside the calling | |
418 | * threads context. | |
419 | */ | |
420 | void handle_nested_irq(unsigned int irq) | |
421 | { | |
422 | struct irq_desc *desc = irq_to_desc(irq); | |
423 | struct irqaction *action; | |
424 | irqreturn_t action_ret; | |
425 | ||
426 | might_sleep(); | |
427 | ||
239007b8 | 428 | raw_spin_lock_irq(&desc->lock); |
399b5da2 TG |
429 | |
430 | kstat_incr_irqs_this_cpu(irq, desc); | |
431 | ||
432 | action = desc->action; | |
433 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) | |
434 | goto out_unlock; | |
435 | ||
436 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 437 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
438 | |
439 | action_ret = action->thread_fn(action->irq, action->dev_id); | |
440 | if (!noirqdebug) | |
441 | note_interrupt(irq, desc, action_ret); | |
442 | ||
239007b8 | 443 | raw_spin_lock_irq(&desc->lock); |
399b5da2 TG |
444 | desc->status &= ~IRQ_INPROGRESS; |
445 | ||
446 | out_unlock: | |
239007b8 | 447 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
448 | } |
449 | EXPORT_SYMBOL_GPL(handle_nested_irq); | |
450 | ||
dd87eb3a TG |
451 | /** |
452 | * handle_simple_irq - Simple and software-decoded IRQs. | |
453 | * @irq: the interrupt number | |
454 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
455 | * |
456 | * Simple interrupts are either sent from a demultiplexing interrupt | |
457 | * handler or come from hardware, where no interrupt hardware control | |
458 | * is necessary. | |
459 | * | |
460 | * Note: The caller is expected to handle the ack, clear, mask and | |
461 | * unmask issues if necessary. | |
462 | */ | |
7ad5b3a5 | 463 | void |
7d12e780 | 464 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
465 | { |
466 | struct irqaction *action; | |
467 | irqreturn_t action_ret; | |
dd87eb3a | 468 | |
239007b8 | 469 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
470 | |
471 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
472 | goto out_unlock; | |
971e5b35 | 473 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
d6c88a50 | 474 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
475 | |
476 | action = desc->action; | |
971e5b35 | 477 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
dd87eb3a TG |
478 | goto out_unlock; |
479 | ||
480 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 481 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 482 | |
7d12e780 | 483 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 484 | if (!noirqdebug) |
7d12e780 | 485 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 486 | |
239007b8 | 487 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
488 | desc->status &= ~IRQ_INPROGRESS; |
489 | out_unlock: | |
239007b8 | 490 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
491 | } |
492 | ||
493 | /** | |
494 | * handle_level_irq - Level type irq handler | |
495 | * @irq: the interrupt number | |
496 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
497 | * |
498 | * Level type interrupts are active as long as the hardware line has | |
499 | * the active level. This may require to mask the interrupt and unmask | |
500 | * it after the associated handler has acknowledged the device, so the | |
501 | * interrupt line is back to inactive. | |
502 | */ | |
7ad5b3a5 | 503 | void |
7d12e780 | 504 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 505 | { |
dd87eb3a TG |
506 | struct irqaction *action; |
507 | irqreturn_t action_ret; | |
508 | ||
239007b8 | 509 | raw_spin_lock(&desc->lock); |
9205e31d | 510 | mask_ack_irq(desc); |
dd87eb3a TG |
511 | |
512 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
86998aa6 | 513 | goto out_unlock; |
dd87eb3a | 514 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
d6c88a50 | 515 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
516 | |
517 | /* | |
518 | * If its disabled or no action available | |
519 | * keep it masked and get out of here | |
520 | */ | |
521 | action = desc->action; | |
49663421 | 522 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
86998aa6 | 523 | goto out_unlock; |
dd87eb3a TG |
524 | |
525 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 526 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 527 | |
7d12e780 | 528 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 529 | if (!noirqdebug) |
7d12e780 | 530 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 531 | |
239007b8 | 532 | raw_spin_lock(&desc->lock); |
dd87eb3a | 533 | desc->status &= ~IRQ_INPROGRESS; |
b25c340c | 534 | |
0b1adaa0 | 535 | if (!(desc->status & (IRQ_DISABLED | IRQ_ONESHOT))) |
0eda58b7 | 536 | unmask_irq(desc); |
86998aa6 | 537 | out_unlock: |
239007b8 | 538 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 539 | } |
14819ea1 | 540 | EXPORT_SYMBOL_GPL(handle_level_irq); |
dd87eb3a TG |
541 | |
542 | /** | |
47c2a3aa | 543 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
544 | * @irq: the interrupt number |
545 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 546 | * |
47c2a3aa | 547 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
548 | * call when the interrupt has been serviced. This enables support |
549 | * for modern forms of interrupt handlers, which handle the flow | |
550 | * details in hardware, transparently. | |
551 | */ | |
7ad5b3a5 | 552 | void |
7d12e780 | 553 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 554 | { |
dd87eb3a TG |
555 | struct irqaction *action; |
556 | irqreturn_t action_ret; | |
557 | ||
239007b8 | 558 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
559 | |
560 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
561 | goto out; | |
562 | ||
563 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
d6c88a50 | 564 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
565 | |
566 | /* | |
567 | * If its disabled or no action available | |
76d21601 | 568 | * then mask it and get out of here: |
dd87eb3a TG |
569 | */ |
570 | action = desc->action; | |
98bb244b BH |
571 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
572 | desc->status |= IRQ_PENDING; | |
e2c0f8ff | 573 | mask_irq(desc); |
dd87eb3a | 574 | goto out; |
98bb244b | 575 | } |
dd87eb3a TG |
576 | |
577 | desc->status |= IRQ_INPROGRESS; | |
98bb244b | 578 | desc->status &= ~IRQ_PENDING; |
239007b8 | 579 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 580 | |
7d12e780 | 581 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 582 | if (!noirqdebug) |
7d12e780 | 583 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 584 | |
239007b8 | 585 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
586 | desc->status &= ~IRQ_INPROGRESS; |
587 | out: | |
0c5c1557 | 588 | desc->irq_data.chip->irq_eoi(&desc->irq_data); |
dd87eb3a | 589 | |
239007b8 | 590 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
591 | } |
592 | ||
593 | /** | |
594 | * handle_edge_irq - edge type IRQ handler | |
595 | * @irq: the interrupt number | |
596 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
597 | * |
598 | * Interrupt occures on the falling and/or rising edge of a hardware | |
599 | * signal. The occurence is latched into the irq controller hardware | |
600 | * and must be acked in order to be reenabled. After the ack another | |
601 | * interrupt can happen on the same source even before the first one | |
dfff0615 | 602 | * is handled by the associated event handler. If this happens it |
dd87eb3a TG |
603 | * might be necessary to disable (mask) the interrupt depending on the |
604 | * controller hardware. This requires to reenable the interrupt inside | |
605 | * of the loop which handles the interrupts which have arrived while | |
606 | * the handler was running. If all pending interrupts are handled, the | |
607 | * loop is left. | |
608 | */ | |
7ad5b3a5 | 609 | void |
7d12e780 | 610 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 611 | { |
239007b8 | 612 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
613 | |
614 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
615 | ||
616 | /* | |
617 | * If we're currently running this IRQ, or its disabled, | |
618 | * we shouldn't process the IRQ. Mark it pending, handle | |
619 | * the necessary masking and go out | |
620 | */ | |
621 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || | |
622 | !desc->action)) { | |
623 | desc->status |= (IRQ_PENDING | IRQ_MASKED); | |
9205e31d | 624 | mask_ack_irq(desc); |
dd87eb3a TG |
625 | goto out_unlock; |
626 | } | |
d6c88a50 | 627 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
628 | |
629 | /* Start handling the irq */ | |
22a49163 | 630 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
dd87eb3a TG |
631 | |
632 | /* Mark the IRQ currently in progress.*/ | |
633 | desc->status |= IRQ_INPROGRESS; | |
634 | ||
635 | do { | |
636 | struct irqaction *action = desc->action; | |
637 | irqreturn_t action_ret; | |
638 | ||
639 | if (unlikely(!action)) { | |
e2c0f8ff | 640 | mask_irq(desc); |
dd87eb3a TG |
641 | goto out_unlock; |
642 | } | |
643 | ||
644 | /* | |
645 | * When another irq arrived while we were handling | |
646 | * one, we could have masked the irq. | |
647 | * Renable it, if it was not disabled in meantime. | |
648 | */ | |
649 | if (unlikely((desc->status & | |
650 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == | |
651 | (IRQ_PENDING | IRQ_MASKED))) { | |
0eda58b7 | 652 | unmask_irq(desc); |
dd87eb3a TG |
653 | } |
654 | ||
655 | desc->status &= ~IRQ_PENDING; | |
239007b8 | 656 | raw_spin_unlock(&desc->lock); |
7d12e780 | 657 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 658 | if (!noirqdebug) |
7d12e780 | 659 | note_interrupt(irq, desc, action_ret); |
239007b8 | 660 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
661 | |
662 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); | |
663 | ||
664 | desc->status &= ~IRQ_INPROGRESS; | |
665 | out_unlock: | |
239007b8 | 666 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
667 | } |
668 | ||
dd87eb3a | 669 | /** |
24b26d42 | 670 | * handle_percpu_irq - Per CPU local irq handler |
dd87eb3a TG |
671 | * @irq: the interrupt number |
672 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
673 | * |
674 | * Per CPU interrupts on SMP machines without locking requirements | |
675 | */ | |
7ad5b3a5 | 676 | void |
7d12e780 | 677 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
678 | { |
679 | irqreturn_t action_ret; | |
680 | ||
d6c88a50 | 681 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a | 682 | |
22a49163 TG |
683 | if (desc->irq_data.chip->irq_ack) |
684 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 685 | |
7d12e780 | 686 | action_ret = handle_IRQ_event(irq, desc->action); |
dd87eb3a | 687 | if (!noirqdebug) |
7d12e780 | 688 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 689 | |
0c5c1557 TG |
690 | if (desc->irq_data.chip->irq_eoi) |
691 | desc->irq_data.chip->irq_eoi(&desc->irq_data); | |
dd87eb3a TG |
692 | } |
693 | ||
dd87eb3a | 694 | void |
a460e745 IM |
695 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
696 | const char *name) | |
dd87eb3a | 697 | { |
d3c60047 | 698 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
699 | unsigned long flags; |
700 | ||
7d94f7ca | 701 | if (!desc) { |
dd87eb3a TG |
702 | printk(KERN_ERR |
703 | "Trying to install type control for IRQ%d\n", irq); | |
704 | return; | |
705 | } | |
706 | ||
dd87eb3a TG |
707 | if (!handle) |
708 | handle = handle_bad_irq; | |
6b8ff312 | 709 | else if (desc->irq_data.chip == &no_irq_chip) { |
f8b5473f | 710 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
b039db8e | 711 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
f8b5473f TG |
712 | /* |
713 | * Some ARM implementations install a handler for really dumb | |
714 | * interrupt hardware without setting an irq_chip. This worked | |
715 | * with the ARM no_irq_chip but the check in setup_irq would | |
716 | * prevent us to setup the interrupt at all. Switch it to | |
717 | * dummy_irq_chip for easy transition. | |
718 | */ | |
6b8ff312 | 719 | desc->irq_data.chip = &dummy_irq_chip; |
f8b5473f | 720 | } |
dd87eb3a | 721 | |
3876ec9e | 722 | chip_bus_lock(desc); |
239007b8 | 723 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a TG |
724 | |
725 | /* Uninstall? */ | |
726 | if (handle == handle_bad_irq) { | |
6b8ff312 | 727 | if (desc->irq_data.chip != &no_irq_chip) |
9205e31d | 728 | mask_ack_irq(desc); |
dd87eb3a TG |
729 | desc->status |= IRQ_DISABLED; |
730 | desc->depth = 1; | |
731 | } | |
732 | desc->handle_irq = handle; | |
a460e745 | 733 | desc->name = name; |
dd87eb3a TG |
734 | |
735 | if (handle != handle_bad_irq && is_chained) { | |
736 | desc->status &= ~IRQ_DISABLED; | |
737 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; | |
738 | desc->depth = 0; | |
37e12df7 | 739 | desc->irq_data.chip->irq_startup(&desc->irq_data); |
dd87eb3a | 740 | } |
239007b8 | 741 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3876ec9e | 742 | chip_bus_sync_unlock(desc); |
dd87eb3a | 743 | } |
14819ea1 | 744 | EXPORT_SYMBOL_GPL(__set_irq_handler); |
dd87eb3a TG |
745 | |
746 | void | |
747 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
57a58a94 | 748 | irq_flow_handler_t handle) |
dd87eb3a TG |
749 | { |
750 | set_irq_chip(irq, chip); | |
a460e745 | 751 | __set_irq_handler(irq, handle, 0, NULL); |
dd87eb3a TG |
752 | } |
753 | ||
a460e745 IM |
754 | void |
755 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | |
756 | irq_flow_handler_t handle, const char *name) | |
dd87eb3a | 757 | { |
a460e745 IM |
758 | set_irq_chip(irq, chip); |
759 | __set_irq_handler(irq, handle, 0, name); | |
dd87eb3a | 760 | } |
46f4f8f6 | 761 | |
44247184 | 762 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
46f4f8f6 | 763 | { |
d3c60047 | 764 | struct irq_desc *desc = irq_to_desc(irq); |
46f4f8f6 RB |
765 | unsigned long flags; |
766 | ||
44247184 | 767 | if (!desc) |
46f4f8f6 | 768 | return; |
46f4f8f6 | 769 | |
44247184 TG |
770 | /* Sanitize flags */ |
771 | set &= IRQF_MODIFY_MASK; | |
772 | clr &= IRQF_MODIFY_MASK; | |
46f4f8f6 | 773 | |
239007b8 | 774 | raw_spin_lock_irqsave(&desc->lock, flags); |
44247184 TG |
775 | desc->status &= ~clr; |
776 | desc->status |= set; | |
239007b8 | 777 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
46f4f8f6 | 778 | } |