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Commit | Line | Data |
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dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
18 | ||
19 | #include "internals.h" | |
20 | ||
21 | /** | |
a0cd9ca2 | 22 | * irq_set_chip - set the irq chip for an irq |
dd87eb3a TG |
23 | * @irq: irq number |
24 | * @chip: pointer to irq chip description structure | |
25 | */ | |
a0cd9ca2 | 26 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) |
dd87eb3a | 27 | { |
d3c60047 | 28 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
29 | unsigned long flags; |
30 | ||
7d94f7ca | 31 | if (!desc) { |
261c40c1 | 32 | WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq); |
dd87eb3a TG |
33 | return -EINVAL; |
34 | } | |
35 | ||
36 | if (!chip) | |
37 | chip = &no_irq_chip; | |
38 | ||
239007b8 | 39 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a | 40 | irq_chip_set_defaults(chip); |
6b8ff312 | 41 | desc->irq_data.chip = chip; |
239007b8 | 42 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
43 | |
44 | return 0; | |
45 | } | |
a0cd9ca2 | 46 | EXPORT_SYMBOL(irq_set_chip); |
dd87eb3a TG |
47 | |
48 | /** | |
a0cd9ca2 | 49 | * irq_set_type - set the irq trigger type for an irq |
dd87eb3a | 50 | * @irq: irq number |
0c5d1eb7 | 51 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a | 52 | */ |
a0cd9ca2 | 53 | int irq_set_irq_type(unsigned int irq, unsigned int type) |
dd87eb3a | 54 | { |
d3c60047 | 55 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
56 | unsigned long flags; |
57 | int ret = -ENXIO; | |
58 | ||
7d94f7ca | 59 | if (!desc) { |
dd87eb3a TG |
60 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); |
61 | return -ENODEV; | |
62 | } | |
63 | ||
f2b662da | 64 | type &= IRQ_TYPE_SENSE_MASK; |
0c5d1eb7 DB |
65 | if (type == IRQ_TYPE_NONE) |
66 | return 0; | |
67 | ||
43abe43c | 68 | chip_bus_lock(desc); |
239007b8 | 69 | raw_spin_lock_irqsave(&desc->lock, flags); |
0b3682ba | 70 | ret = __irq_set_trigger(desc, irq, type); |
239007b8 | 71 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
43abe43c | 72 | chip_bus_sync_unlock(desc); |
dd87eb3a TG |
73 | return ret; |
74 | } | |
a0cd9ca2 | 75 | EXPORT_SYMBOL(irq_set_irq_type); |
dd87eb3a TG |
76 | |
77 | /** | |
a0cd9ca2 | 78 | * irq_set_handler_data - set irq handler data for an irq |
dd87eb3a TG |
79 | * @irq: Interrupt number |
80 | * @data: Pointer to interrupt specific data | |
81 | * | |
82 | * Set the hardware irq controller data for an irq | |
83 | */ | |
a0cd9ca2 | 84 | int irq_set_handler_data(unsigned int irq, void *data) |
dd87eb3a | 85 | { |
d3c60047 | 86 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
87 | unsigned long flags; |
88 | ||
7d94f7ca | 89 | if (!desc) { |
dd87eb3a TG |
90 | printk(KERN_ERR |
91 | "Trying to install controller data for IRQ%d\n", irq); | |
92 | return -EINVAL; | |
93 | } | |
94 | ||
239007b8 | 95 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 96 | desc->irq_data.handler_data = data; |
239007b8 | 97 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
98 | return 0; |
99 | } | |
a0cd9ca2 | 100 | EXPORT_SYMBOL(irq_set_handler_data); |
dd87eb3a | 101 | |
5b912c10 | 102 | /** |
a0cd9ca2 | 103 | * irq_set_msi_desc - set MSI descriptor data for an irq |
5b912c10 | 104 | * @irq: Interrupt number |
472900b8 | 105 | * @entry: Pointer to MSI descriptor data |
5b912c10 | 106 | * |
24b26d42 | 107 | * Set the MSI descriptor entry for an irq |
5b912c10 | 108 | */ |
a0cd9ca2 | 109 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) |
5b912c10 | 110 | { |
d3c60047 | 111 | struct irq_desc *desc = irq_to_desc(irq); |
5b912c10 EB |
112 | unsigned long flags; |
113 | ||
7d94f7ca | 114 | if (!desc) { |
5b912c10 EB |
115 | printk(KERN_ERR |
116 | "Trying to install msi data for IRQ%d\n", irq); | |
117 | return -EINVAL; | |
118 | } | |
7d94f7ca | 119 | |
239007b8 | 120 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 121 | desc->irq_data.msi_desc = entry; |
7fe3730d ME |
122 | if (entry) |
123 | entry->irq = irq; | |
239007b8 | 124 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
5b912c10 EB |
125 | return 0; |
126 | } | |
127 | ||
dd87eb3a | 128 | /** |
a0cd9ca2 | 129 | * irq_set_chip_data - set irq chip data for an irq |
dd87eb3a TG |
130 | * @irq: Interrupt number |
131 | * @data: Pointer to chip specific data | |
132 | * | |
133 | * Set the hardware irq chip data for an irq | |
134 | */ | |
a0cd9ca2 | 135 | int irq_set_chip_data(unsigned int irq, void *data) |
dd87eb3a | 136 | { |
d3c60047 | 137 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
138 | unsigned long flags; |
139 | ||
7d94f7ca YL |
140 | if (!desc) { |
141 | printk(KERN_ERR | |
142 | "Trying to install chip data for IRQ%d\n", irq); | |
143 | return -EINVAL; | |
144 | } | |
145 | ||
6b8ff312 | 146 | if (!desc->irq_data.chip) { |
dd87eb3a TG |
147 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); |
148 | return -EINVAL; | |
149 | } | |
150 | ||
239007b8 | 151 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 152 | desc->irq_data.chip_data = data; |
239007b8 | 153 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
154 | |
155 | return 0; | |
156 | } | |
a0cd9ca2 | 157 | EXPORT_SYMBOL(irq_set_chip_data); |
dd87eb3a | 158 | |
f303a6dd TG |
159 | struct irq_data *irq_get_irq_data(unsigned int irq) |
160 | { | |
161 | struct irq_desc *desc = irq_to_desc(irq); | |
162 | ||
163 | return desc ? &desc->irq_data : NULL; | |
164 | } | |
165 | EXPORT_SYMBOL_GPL(irq_get_irq_data); | |
166 | ||
399b5da2 TG |
167 | /** |
168 | * set_irq_nested_thread - Set/Reset the IRQ_NESTED_THREAD flag of an irq | |
169 | * | |
170 | * @irq: Interrupt number | |
171 | * @nest: 0 to clear / 1 to set the IRQ_NESTED_THREAD flag | |
172 | * | |
173 | * The IRQ_NESTED_THREAD flag indicates that on | |
174 | * request_threaded_irq() no separate interrupt thread should be | |
175 | * created for the irq as the handler are called nested in the | |
176 | * context of a demultiplexing interrupt handler thread. | |
177 | */ | |
178 | void set_irq_nested_thread(unsigned int irq, int nest) | |
179 | { | |
180 | struct irq_desc *desc = irq_to_desc(irq); | |
181 | unsigned long flags; | |
182 | ||
183 | if (!desc) | |
184 | return; | |
185 | ||
239007b8 | 186 | raw_spin_lock_irqsave(&desc->lock, flags); |
399b5da2 TG |
187 | if (nest) |
188 | desc->status |= IRQ_NESTED_THREAD; | |
189 | else | |
190 | desc->status &= ~IRQ_NESTED_THREAD; | |
239007b8 | 191 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
399b5da2 TG |
192 | } |
193 | EXPORT_SYMBOL_GPL(set_irq_nested_thread); | |
194 | ||
46999238 TG |
195 | int irq_startup(struct irq_desc *desc) |
196 | { | |
197 | desc->status &= ~(IRQ_MASKED | IRQ_DISABLED); | |
198 | desc->depth = 0; | |
199 | ||
200 | if (desc->irq_data.chip->irq_startup) | |
201 | return desc->irq_data.chip->irq_startup(&desc->irq_data); | |
202 | ||
203 | desc->irq_data.chip->irq_enable(&desc->irq_data); | |
204 | return 0; | |
205 | } | |
206 | ||
207 | void irq_shutdown(struct irq_desc *desc) | |
208 | { | |
209 | desc->status |= IRQ_MASKED | IRQ_DISABLED; | |
210 | desc->depth = 1; | |
211 | desc->irq_data.chip->irq_shutdown(&desc->irq_data); | |
212 | } | |
213 | ||
dd87eb3a TG |
214 | /* |
215 | * default enable function | |
216 | */ | |
c5f75634 | 217 | static void default_enable(struct irq_data *data) |
dd87eb3a | 218 | { |
c5f75634 | 219 | struct irq_desc *desc = irq_data_to_desc(data); |
dd87eb3a | 220 | |
0eda58b7 | 221 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
dd87eb3a TG |
222 | desc->status &= ~IRQ_MASKED; |
223 | } | |
224 | ||
225 | /* | |
226 | * default disable function | |
227 | */ | |
bc310dda | 228 | static void default_disable(struct irq_data *data) |
dd87eb3a | 229 | { |
dd87eb3a TG |
230 | } |
231 | ||
89d694b9 TG |
232 | /* |
233 | * default shutdown function | |
234 | */ | |
bc310dda | 235 | static void default_shutdown(struct irq_data *data) |
89d694b9 | 236 | { |
bc310dda | 237 | struct irq_desc *desc = irq_data_to_desc(data); |
89d694b9 | 238 | |
e2c0f8ff | 239 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
89d694b9 TG |
240 | } |
241 | ||
bd151412 | 242 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
3876ec9e | 243 | /* Temporary migration helpers */ |
e2c0f8ff TG |
244 | static void compat_irq_mask(struct irq_data *data) |
245 | { | |
246 | data->chip->mask(data->irq); | |
247 | } | |
248 | ||
0eda58b7 TG |
249 | static void compat_irq_unmask(struct irq_data *data) |
250 | { | |
251 | data->chip->unmask(data->irq); | |
252 | } | |
253 | ||
22a49163 TG |
254 | static void compat_irq_ack(struct irq_data *data) |
255 | { | |
256 | data->chip->ack(data->irq); | |
257 | } | |
258 | ||
9205e31d TG |
259 | static void compat_irq_mask_ack(struct irq_data *data) |
260 | { | |
261 | data->chip->mask_ack(data->irq); | |
262 | } | |
263 | ||
0c5c1557 TG |
264 | static void compat_irq_eoi(struct irq_data *data) |
265 | { | |
266 | data->chip->eoi(data->irq); | |
267 | } | |
268 | ||
c5f75634 TG |
269 | static void compat_irq_enable(struct irq_data *data) |
270 | { | |
271 | data->chip->enable(data->irq); | |
272 | } | |
273 | ||
bc310dda TG |
274 | static void compat_irq_disable(struct irq_data *data) |
275 | { | |
276 | data->chip->disable(data->irq); | |
277 | } | |
278 | ||
279 | static void compat_irq_shutdown(struct irq_data *data) | |
280 | { | |
281 | data->chip->shutdown(data->irq); | |
282 | } | |
283 | ||
37e12df7 TG |
284 | static unsigned int compat_irq_startup(struct irq_data *data) |
285 | { | |
286 | return data->chip->startup(data->irq); | |
287 | } | |
288 | ||
c96b3b3c TG |
289 | static int compat_irq_set_affinity(struct irq_data *data, |
290 | const struct cpumask *dest, bool force) | |
291 | { | |
292 | return data->chip->set_affinity(data->irq, dest); | |
293 | } | |
294 | ||
b2ba2c30 TG |
295 | static int compat_irq_set_type(struct irq_data *data, unsigned int type) |
296 | { | |
297 | return data->chip->set_type(data->irq, type); | |
298 | } | |
299 | ||
2f7e99bb TG |
300 | static int compat_irq_set_wake(struct irq_data *data, unsigned int on) |
301 | { | |
302 | return data->chip->set_wake(data->irq, on); | |
303 | } | |
304 | ||
21e2b8c6 TG |
305 | static int compat_irq_retrigger(struct irq_data *data) |
306 | { | |
307 | return data->chip->retrigger(data->irq); | |
308 | } | |
309 | ||
3876ec9e TG |
310 | static void compat_bus_lock(struct irq_data *data) |
311 | { | |
312 | data->chip->bus_lock(data->irq); | |
313 | } | |
314 | ||
315 | static void compat_bus_sync_unlock(struct irq_data *data) | |
316 | { | |
317 | data->chip->bus_sync_unlock(data->irq); | |
318 | } | |
bd151412 | 319 | #endif |
3876ec9e | 320 | |
dd87eb3a TG |
321 | /* |
322 | * Fixup enable/disable function pointers | |
323 | */ | |
324 | void irq_chip_set_defaults(struct irq_chip *chip) | |
325 | { | |
bd151412 | 326 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
c5f75634 TG |
327 | /* |
328 | * Compat fixup functions need to be before we set the | |
329 | * defaults for enable/disable/startup/shutdown | |
330 | */ | |
331 | if (chip->enable) | |
332 | chip->irq_enable = compat_irq_enable; | |
bc310dda TG |
333 | if (chip->disable) |
334 | chip->irq_disable = compat_irq_disable; | |
335 | if (chip->shutdown) | |
336 | chip->irq_shutdown = compat_irq_shutdown; | |
37e12df7 TG |
337 | if (chip->startup) |
338 | chip->irq_startup = compat_irq_startup; | |
bd151412 | 339 | #endif |
c5f75634 TG |
340 | /* |
341 | * The real defaults | |
342 | */ | |
343 | if (!chip->irq_enable) | |
344 | chip->irq_enable = default_enable; | |
bc310dda TG |
345 | if (!chip->irq_disable) |
346 | chip->irq_disable = default_disable; | |
89d694b9 | 347 | /* |
bc310dda TG |
348 | * We use chip->irq_disable, when the user provided its own. When |
349 | * we have default_disable set for chip->irq_disable, then we need | |
89d694b9 TG |
350 | * to use default_shutdown, otherwise the irq line is not |
351 | * disabled on free_irq(): | |
352 | */ | |
bc310dda TG |
353 | if (!chip->irq_shutdown) |
354 | chip->irq_shutdown = chip->irq_disable != default_disable ? | |
355 | chip->irq_disable : default_shutdown; | |
bd151412 TG |
356 | |
357 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED | |
b86432b4 ZY |
358 | if (!chip->end) |
359 | chip->end = dummy_irq_chip.end; | |
3876ec9e | 360 | |
bc310dda TG |
361 | /* |
362 | * Now fix up the remaining compat handlers | |
363 | */ | |
3876ec9e TG |
364 | if (chip->bus_lock) |
365 | chip->irq_bus_lock = compat_bus_lock; | |
366 | if (chip->bus_sync_unlock) | |
367 | chip->irq_bus_sync_unlock = compat_bus_sync_unlock; | |
e2c0f8ff TG |
368 | if (chip->mask) |
369 | chip->irq_mask = compat_irq_mask; | |
0eda58b7 TG |
370 | if (chip->unmask) |
371 | chip->irq_unmask = compat_irq_unmask; | |
22a49163 TG |
372 | if (chip->ack) |
373 | chip->irq_ack = compat_irq_ack; | |
9205e31d TG |
374 | if (chip->mask_ack) |
375 | chip->irq_mask_ack = compat_irq_mask_ack; | |
0c5c1557 TG |
376 | if (chip->eoi) |
377 | chip->irq_eoi = compat_irq_eoi; | |
c96b3b3c TG |
378 | if (chip->set_affinity) |
379 | chip->irq_set_affinity = compat_irq_set_affinity; | |
b2ba2c30 TG |
380 | if (chip->set_type) |
381 | chip->irq_set_type = compat_irq_set_type; | |
2f7e99bb TG |
382 | if (chip->set_wake) |
383 | chip->irq_set_wake = compat_irq_set_wake; | |
21e2b8c6 TG |
384 | if (chip->retrigger) |
385 | chip->irq_retrigger = compat_irq_retrigger; | |
bd151412 | 386 | #endif |
dd87eb3a TG |
387 | } |
388 | ||
9205e31d | 389 | static inline void mask_ack_irq(struct irq_desc *desc) |
dd87eb3a | 390 | { |
9205e31d TG |
391 | if (desc->irq_data.chip->irq_mask_ack) |
392 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | |
dd87eb3a | 393 | else { |
e2c0f8ff | 394 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
22a49163 TG |
395 | if (desc->irq_data.chip->irq_ack) |
396 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 397 | } |
0b1adaa0 TG |
398 | desc->status |= IRQ_MASKED; |
399 | } | |
400 | ||
e2c0f8ff | 401 | static inline void mask_irq(struct irq_desc *desc) |
0b1adaa0 | 402 | { |
e2c0f8ff TG |
403 | if (desc->irq_data.chip->irq_mask) { |
404 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
0b1adaa0 TG |
405 | desc->status |= IRQ_MASKED; |
406 | } | |
407 | } | |
408 | ||
0eda58b7 | 409 | static inline void unmask_irq(struct irq_desc *desc) |
0b1adaa0 | 410 | { |
0eda58b7 TG |
411 | if (desc->irq_data.chip->irq_unmask) { |
412 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
0b1adaa0 TG |
413 | desc->status &= ~IRQ_MASKED; |
414 | } | |
dd87eb3a TG |
415 | } |
416 | ||
399b5da2 TG |
417 | /* |
418 | * handle_nested_irq - Handle a nested irq from a irq thread | |
419 | * @irq: the interrupt number | |
420 | * | |
421 | * Handle interrupts which are nested into a threaded interrupt | |
422 | * handler. The handler function is called inside the calling | |
423 | * threads context. | |
424 | */ | |
425 | void handle_nested_irq(unsigned int irq) | |
426 | { | |
427 | struct irq_desc *desc = irq_to_desc(irq); | |
428 | struct irqaction *action; | |
429 | irqreturn_t action_ret; | |
430 | ||
431 | might_sleep(); | |
432 | ||
239007b8 | 433 | raw_spin_lock_irq(&desc->lock); |
399b5da2 TG |
434 | |
435 | kstat_incr_irqs_this_cpu(irq, desc); | |
436 | ||
437 | action = desc->action; | |
438 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) | |
439 | goto out_unlock; | |
440 | ||
441 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 442 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
443 | |
444 | action_ret = action->thread_fn(action->irq, action->dev_id); | |
445 | if (!noirqdebug) | |
446 | note_interrupt(irq, desc, action_ret); | |
447 | ||
239007b8 | 448 | raw_spin_lock_irq(&desc->lock); |
399b5da2 TG |
449 | desc->status &= ~IRQ_INPROGRESS; |
450 | ||
451 | out_unlock: | |
239007b8 | 452 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
453 | } |
454 | EXPORT_SYMBOL_GPL(handle_nested_irq); | |
455 | ||
fe200ae4 TG |
456 | static bool irq_check_poll(struct irq_desc *desc) |
457 | { | |
458 | if (!(desc->status & IRQ_POLL_INPROGRESS)) | |
459 | return false; | |
460 | return irq_wait_for_poll(desc); | |
461 | } | |
462 | ||
dd87eb3a TG |
463 | /** |
464 | * handle_simple_irq - Simple and software-decoded IRQs. | |
465 | * @irq: the interrupt number | |
466 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
467 | * |
468 | * Simple interrupts are either sent from a demultiplexing interrupt | |
469 | * handler or come from hardware, where no interrupt hardware control | |
470 | * is necessary. | |
471 | * | |
472 | * Note: The caller is expected to handle the ack, clear, mask and | |
473 | * unmask issues if necessary. | |
474 | */ | |
7ad5b3a5 | 475 | void |
7d12e780 | 476 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
477 | { |
478 | struct irqaction *action; | |
479 | irqreturn_t action_ret; | |
dd87eb3a | 480 | |
239007b8 | 481 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
482 | |
483 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
fe200ae4 TG |
484 | if (!irq_check_poll(desc)) |
485 | goto out_unlock; | |
486 | ||
971e5b35 | 487 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
d6c88a50 | 488 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
489 | |
490 | action = desc->action; | |
971e5b35 | 491 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
dd87eb3a TG |
492 | goto out_unlock; |
493 | ||
494 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 495 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 496 | |
7d12e780 | 497 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 498 | if (!noirqdebug) |
7d12e780 | 499 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 500 | |
239007b8 | 501 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
502 | desc->status &= ~IRQ_INPROGRESS; |
503 | out_unlock: | |
239007b8 | 504 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
505 | } |
506 | ||
507 | /** | |
508 | * handle_level_irq - Level type irq handler | |
509 | * @irq: the interrupt number | |
510 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
511 | * |
512 | * Level type interrupts are active as long as the hardware line has | |
513 | * the active level. This may require to mask the interrupt and unmask | |
514 | * it after the associated handler has acknowledged the device, so the | |
515 | * interrupt line is back to inactive. | |
516 | */ | |
7ad5b3a5 | 517 | void |
7d12e780 | 518 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 519 | { |
dd87eb3a TG |
520 | struct irqaction *action; |
521 | irqreturn_t action_ret; | |
522 | ||
239007b8 | 523 | raw_spin_lock(&desc->lock); |
9205e31d | 524 | mask_ack_irq(desc); |
dd87eb3a TG |
525 | |
526 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
fe200ae4 TG |
527 | if (!irq_check_poll(desc)) |
528 | goto out_unlock; | |
529 | ||
dd87eb3a | 530 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
d6c88a50 | 531 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
532 | |
533 | /* | |
534 | * If its disabled or no action available | |
535 | * keep it masked and get out of here | |
536 | */ | |
537 | action = desc->action; | |
49663421 | 538 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
86998aa6 | 539 | goto out_unlock; |
dd87eb3a TG |
540 | |
541 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 542 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 543 | |
7d12e780 | 544 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 545 | if (!noirqdebug) |
7d12e780 | 546 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 547 | |
239007b8 | 548 | raw_spin_lock(&desc->lock); |
dd87eb3a | 549 | desc->status &= ~IRQ_INPROGRESS; |
b25c340c | 550 | |
0b1adaa0 | 551 | if (!(desc->status & (IRQ_DISABLED | IRQ_ONESHOT))) |
0eda58b7 | 552 | unmask_irq(desc); |
86998aa6 | 553 | out_unlock: |
239007b8 | 554 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 555 | } |
14819ea1 | 556 | EXPORT_SYMBOL_GPL(handle_level_irq); |
dd87eb3a TG |
557 | |
558 | /** | |
47c2a3aa | 559 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
560 | * @irq: the interrupt number |
561 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 562 | * |
47c2a3aa | 563 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
564 | * call when the interrupt has been serviced. This enables support |
565 | * for modern forms of interrupt handlers, which handle the flow | |
566 | * details in hardware, transparently. | |
567 | */ | |
7ad5b3a5 | 568 | void |
7d12e780 | 569 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 570 | { |
dd87eb3a TG |
571 | struct irqaction *action; |
572 | irqreturn_t action_ret; | |
573 | ||
239007b8 | 574 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
575 | |
576 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
fe200ae4 TG |
577 | if (!irq_check_poll(desc)) |
578 | goto out; | |
dd87eb3a TG |
579 | |
580 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
d6c88a50 | 581 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
582 | |
583 | /* | |
584 | * If its disabled or no action available | |
76d21601 | 585 | * then mask it and get out of here: |
dd87eb3a TG |
586 | */ |
587 | action = desc->action; | |
98bb244b BH |
588 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
589 | desc->status |= IRQ_PENDING; | |
e2c0f8ff | 590 | mask_irq(desc); |
dd87eb3a | 591 | goto out; |
98bb244b | 592 | } |
dd87eb3a TG |
593 | |
594 | desc->status |= IRQ_INPROGRESS; | |
98bb244b | 595 | desc->status &= ~IRQ_PENDING; |
239007b8 | 596 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 597 | |
7d12e780 | 598 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 599 | if (!noirqdebug) |
7d12e780 | 600 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 601 | |
239007b8 | 602 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
603 | desc->status &= ~IRQ_INPROGRESS; |
604 | out: | |
0c5c1557 | 605 | desc->irq_data.chip->irq_eoi(&desc->irq_data); |
dd87eb3a | 606 | |
239007b8 | 607 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
608 | } |
609 | ||
610 | /** | |
611 | * handle_edge_irq - edge type IRQ handler | |
612 | * @irq: the interrupt number | |
613 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
614 | * |
615 | * Interrupt occures on the falling and/or rising edge of a hardware | |
616 | * signal. The occurence is latched into the irq controller hardware | |
617 | * and must be acked in order to be reenabled. After the ack another | |
618 | * interrupt can happen on the same source even before the first one | |
dfff0615 | 619 | * is handled by the associated event handler. If this happens it |
dd87eb3a TG |
620 | * might be necessary to disable (mask) the interrupt depending on the |
621 | * controller hardware. This requires to reenable the interrupt inside | |
622 | * of the loop which handles the interrupts which have arrived while | |
623 | * the handler was running. If all pending interrupts are handled, the | |
624 | * loop is left. | |
625 | */ | |
7ad5b3a5 | 626 | void |
7d12e780 | 627 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 628 | { |
239007b8 | 629 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
630 | |
631 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
632 | ||
633 | /* | |
634 | * If we're currently running this IRQ, or its disabled, | |
635 | * we shouldn't process the IRQ. Mark it pending, handle | |
636 | * the necessary masking and go out | |
637 | */ | |
638 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || | |
639 | !desc->action)) { | |
fe200ae4 TG |
640 | if (!irq_check_poll(desc)) { |
641 | desc->status |= (IRQ_PENDING | IRQ_MASKED); | |
642 | mask_ack_irq(desc); | |
643 | goto out_unlock; | |
644 | } | |
dd87eb3a | 645 | } |
d6c88a50 | 646 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
647 | |
648 | /* Start handling the irq */ | |
22a49163 | 649 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
dd87eb3a TG |
650 | |
651 | /* Mark the IRQ currently in progress.*/ | |
652 | desc->status |= IRQ_INPROGRESS; | |
653 | ||
654 | do { | |
655 | struct irqaction *action = desc->action; | |
656 | irqreturn_t action_ret; | |
657 | ||
658 | if (unlikely(!action)) { | |
e2c0f8ff | 659 | mask_irq(desc); |
dd87eb3a TG |
660 | goto out_unlock; |
661 | } | |
662 | ||
663 | /* | |
664 | * When another irq arrived while we were handling | |
665 | * one, we could have masked the irq. | |
666 | * Renable it, if it was not disabled in meantime. | |
667 | */ | |
668 | if (unlikely((desc->status & | |
669 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == | |
670 | (IRQ_PENDING | IRQ_MASKED))) { | |
0eda58b7 | 671 | unmask_irq(desc); |
dd87eb3a TG |
672 | } |
673 | ||
674 | desc->status &= ~IRQ_PENDING; | |
239007b8 | 675 | raw_spin_unlock(&desc->lock); |
7d12e780 | 676 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 677 | if (!noirqdebug) |
7d12e780 | 678 | note_interrupt(irq, desc, action_ret); |
239007b8 | 679 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
680 | |
681 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); | |
682 | ||
683 | desc->status &= ~IRQ_INPROGRESS; | |
684 | out_unlock: | |
239007b8 | 685 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
686 | } |
687 | ||
dd87eb3a | 688 | /** |
24b26d42 | 689 | * handle_percpu_irq - Per CPU local irq handler |
dd87eb3a TG |
690 | * @irq: the interrupt number |
691 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
692 | * |
693 | * Per CPU interrupts on SMP machines without locking requirements | |
694 | */ | |
7ad5b3a5 | 695 | void |
7d12e780 | 696 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
697 | { |
698 | irqreturn_t action_ret; | |
699 | ||
d6c88a50 | 700 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a | 701 | |
22a49163 TG |
702 | if (desc->irq_data.chip->irq_ack) |
703 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 704 | |
7d12e780 | 705 | action_ret = handle_IRQ_event(irq, desc->action); |
dd87eb3a | 706 | if (!noirqdebug) |
7d12e780 | 707 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 708 | |
0c5c1557 TG |
709 | if (desc->irq_data.chip->irq_eoi) |
710 | desc->irq_data.chip->irq_eoi(&desc->irq_data); | |
dd87eb3a TG |
711 | } |
712 | ||
dd87eb3a | 713 | void |
a460e745 IM |
714 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
715 | const char *name) | |
dd87eb3a | 716 | { |
d3c60047 | 717 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
718 | unsigned long flags; |
719 | ||
7d94f7ca | 720 | if (!desc) { |
dd87eb3a TG |
721 | printk(KERN_ERR |
722 | "Trying to install type control for IRQ%d\n", irq); | |
723 | return; | |
724 | } | |
725 | ||
dd87eb3a TG |
726 | if (!handle) |
727 | handle = handle_bad_irq; | |
6b8ff312 | 728 | else if (desc->irq_data.chip == &no_irq_chip) { |
f8b5473f | 729 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
b039db8e | 730 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
f8b5473f TG |
731 | /* |
732 | * Some ARM implementations install a handler for really dumb | |
733 | * interrupt hardware without setting an irq_chip. This worked | |
734 | * with the ARM no_irq_chip but the check in setup_irq would | |
735 | * prevent us to setup the interrupt at all. Switch it to | |
736 | * dummy_irq_chip for easy transition. | |
737 | */ | |
6b8ff312 | 738 | desc->irq_data.chip = &dummy_irq_chip; |
f8b5473f | 739 | } |
dd87eb3a | 740 | |
3876ec9e | 741 | chip_bus_lock(desc); |
239007b8 | 742 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a TG |
743 | |
744 | /* Uninstall? */ | |
745 | if (handle == handle_bad_irq) { | |
6b8ff312 | 746 | if (desc->irq_data.chip != &no_irq_chip) |
9205e31d | 747 | mask_ack_irq(desc); |
dd87eb3a TG |
748 | desc->status |= IRQ_DISABLED; |
749 | desc->depth = 1; | |
750 | } | |
751 | desc->handle_irq = handle; | |
a460e745 | 752 | desc->name = name; |
dd87eb3a TG |
753 | |
754 | if (handle != handle_bad_irq && is_chained) { | |
dd87eb3a | 755 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; |
46999238 | 756 | irq_startup(desc); |
dd87eb3a | 757 | } |
239007b8 | 758 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3876ec9e | 759 | chip_bus_sync_unlock(desc); |
dd87eb3a | 760 | } |
14819ea1 | 761 | EXPORT_SYMBOL_GPL(__set_irq_handler); |
dd87eb3a TG |
762 | |
763 | void | |
764 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
57a58a94 | 765 | irq_flow_handler_t handle) |
dd87eb3a TG |
766 | { |
767 | set_irq_chip(irq, chip); | |
a460e745 | 768 | __set_irq_handler(irq, handle, 0, NULL); |
dd87eb3a TG |
769 | } |
770 | ||
a460e745 IM |
771 | void |
772 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | |
773 | irq_flow_handler_t handle, const char *name) | |
dd87eb3a | 774 | { |
a460e745 IM |
775 | set_irq_chip(irq, chip); |
776 | __set_irq_handler(irq, handle, 0, name); | |
dd87eb3a | 777 | } |
46f4f8f6 | 778 | |
44247184 | 779 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
46f4f8f6 | 780 | { |
d3c60047 | 781 | struct irq_desc *desc = irq_to_desc(irq); |
46f4f8f6 RB |
782 | unsigned long flags; |
783 | ||
44247184 | 784 | if (!desc) |
46f4f8f6 | 785 | return; |
46f4f8f6 | 786 | |
44247184 TG |
787 | /* Sanitize flags */ |
788 | set &= IRQF_MODIFY_MASK; | |
789 | clr &= IRQF_MODIFY_MASK; | |
46f4f8f6 | 790 | |
239007b8 | 791 | raw_spin_lock_irqsave(&desc->lock, flags); |
44247184 TG |
792 | desc->status &= ~clr; |
793 | desc->status |= set; | |
239007b8 | 794 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
46f4f8f6 | 795 | } |