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genirq: Introduce IRQD_MANAGED_SHUTDOWN
[mirror_ubuntu-focal-kernel.git] / kernel / irq / chip.c
CommitLineData
dd87eb3a
TG
1/*
2 * linux/kernel/irq/chip.c
3 *
4 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
5 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 *
7 * This file contains the core interrupt handling code, for irq-chip
8 * based architectures.
9 *
10 * Detailed information is available in Documentation/DocBook/genericirq
11 */
12
13#include <linux/irq.h>
7fe3730d 14#include <linux/msi.h>
dd87eb3a
TG
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/kernel_stat.h>
f8264e34 18#include <linux/irqdomain.h>
dd87eb3a 19
f069686e
SR
20#include <trace/events/irq.h>
21
dd87eb3a
TG
22#include "internals.h"
23
e509bd7d
MW
24static irqreturn_t bad_chained_irq(int irq, void *dev_id)
25{
26 WARN_ONCE(1, "Chained irq %d should not call an action\n", irq);
27 return IRQ_NONE;
28}
29
30/*
31 * Chained handlers should never call action on their IRQ. This default
32 * action will emit warning if such thing happens.
33 */
34struct irqaction chained_action = {
35 .handler = bad_chained_irq,
36};
37
dd87eb3a 38/**
a0cd9ca2 39 * irq_set_chip - set the irq chip for an irq
dd87eb3a
TG
40 * @irq: irq number
41 * @chip: pointer to irq chip description structure
42 */
a0cd9ca2 43int irq_set_chip(unsigned int irq, struct irq_chip *chip)
dd87eb3a 44{
dd87eb3a 45 unsigned long flags;
31d9d9b6 46 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 47
02725e74 48 if (!desc)
dd87eb3a 49 return -EINVAL;
dd87eb3a
TG
50
51 if (!chip)
52 chip = &no_irq_chip;
53
6b8ff312 54 desc->irq_data.chip = chip;
02725e74 55 irq_put_desc_unlock(desc, flags);
d72274e5
DD
56 /*
57 * For !CONFIG_SPARSE_IRQ make the irq show up in
f63b6a05 58 * allocated_irqs.
d72274e5 59 */
f63b6a05 60 irq_mark_irq(irq);
dd87eb3a
TG
61 return 0;
62}
a0cd9ca2 63EXPORT_SYMBOL(irq_set_chip);
dd87eb3a
TG
64
65/**
a0cd9ca2 66 * irq_set_type - set the irq trigger type for an irq
dd87eb3a 67 * @irq: irq number
0c5d1eb7 68 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
dd87eb3a 69 */
a0cd9ca2 70int irq_set_irq_type(unsigned int irq, unsigned int type)
dd87eb3a 71{
dd87eb3a 72 unsigned long flags;
31d9d9b6 73 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
02725e74 74 int ret = 0;
dd87eb3a 75
02725e74
TG
76 if (!desc)
77 return -EINVAL;
dd87eb3a 78
a1ff541a 79 ret = __irq_set_trigger(desc, type);
02725e74 80 irq_put_desc_busunlock(desc, flags);
dd87eb3a
TG
81 return ret;
82}
a0cd9ca2 83EXPORT_SYMBOL(irq_set_irq_type);
dd87eb3a
TG
84
85/**
a0cd9ca2 86 * irq_set_handler_data - set irq handler data for an irq
dd87eb3a
TG
87 * @irq: Interrupt number
88 * @data: Pointer to interrupt specific data
89 *
90 * Set the hardware irq controller data for an irq
91 */
a0cd9ca2 92int irq_set_handler_data(unsigned int irq, void *data)
dd87eb3a 93{
dd87eb3a 94 unsigned long flags;
31d9d9b6 95 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 96
02725e74 97 if (!desc)
dd87eb3a 98 return -EINVAL;
af7080e0 99 desc->irq_common_data.handler_data = data;
02725e74 100 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
101 return 0;
102}
a0cd9ca2 103EXPORT_SYMBOL(irq_set_handler_data);
dd87eb3a 104
5b912c10 105/**
51906e77
AG
106 * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset
107 * @irq_base: Interrupt number base
108 * @irq_offset: Interrupt number offset
109 * @entry: Pointer to MSI descriptor data
5b912c10 110 *
51906e77 111 * Set the MSI descriptor entry for an irq at offset
5b912c10 112 */
51906e77
AG
113int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
114 struct msi_desc *entry)
5b912c10 115{
5b912c10 116 unsigned long flags;
51906e77 117 struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
5b912c10 118
02725e74 119 if (!desc)
5b912c10 120 return -EINVAL;
b237721c 121 desc->irq_common_data.msi_desc = entry;
51906e77
AG
122 if (entry && !irq_offset)
123 entry->irq = irq_base;
02725e74 124 irq_put_desc_unlock(desc, flags);
5b912c10
EB
125 return 0;
126}
127
51906e77
AG
128/**
129 * irq_set_msi_desc - set MSI descriptor data for an irq
130 * @irq: Interrupt number
131 * @entry: Pointer to MSI descriptor data
132 *
133 * Set the MSI descriptor entry for an irq
134 */
135int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
136{
137 return irq_set_msi_desc_off(irq, 0, entry);
138}
139
dd87eb3a 140/**
a0cd9ca2 141 * irq_set_chip_data - set irq chip data for an irq
dd87eb3a
TG
142 * @irq: Interrupt number
143 * @data: Pointer to chip specific data
144 *
145 * Set the hardware irq chip data for an irq
146 */
a0cd9ca2 147int irq_set_chip_data(unsigned int irq, void *data)
dd87eb3a 148{
dd87eb3a 149 unsigned long flags;
31d9d9b6 150 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 151
02725e74 152 if (!desc)
dd87eb3a 153 return -EINVAL;
6b8ff312 154 desc->irq_data.chip_data = data;
02725e74 155 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
156 return 0;
157}
a0cd9ca2 158EXPORT_SYMBOL(irq_set_chip_data);
dd87eb3a 159
f303a6dd
TG
160struct irq_data *irq_get_irq_data(unsigned int irq)
161{
162 struct irq_desc *desc = irq_to_desc(irq);
163
164 return desc ? &desc->irq_data : NULL;
165}
166EXPORT_SYMBOL_GPL(irq_get_irq_data);
167
c1594b77
TG
168static void irq_state_clr_disabled(struct irq_desc *desc)
169{
801a0e9a 170 irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
171}
172
173static void irq_state_set_disabled(struct irq_desc *desc)
174{
801a0e9a 175 irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
176}
177
6e40262e
TG
178static void irq_state_clr_masked(struct irq_desc *desc)
179{
32f4125e 180 irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
181}
182
183static void irq_state_set_masked(struct irq_desc *desc)
184{
32f4125e 185 irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
186}
187
201d7f47
TG
188static void irq_state_clr_started(struct irq_desc *desc)
189{
190 irqd_clear(&desc->irq_data, IRQD_IRQ_STARTED);
191}
192
193static void irq_state_set_started(struct irq_desc *desc)
194{
195 irqd_set(&desc->irq_data, IRQD_IRQ_STARTED);
196}
197
b4bc724e 198int irq_startup(struct irq_desc *desc, bool resend)
46999238 199{
b4bc724e
TG
200 int ret = 0;
201
46999238
TG
202 desc->depth = 0;
203
201d7f47 204 if (irqd_is_started(&desc->irq_data)) {
b4bc724e 205 irq_enable(desc);
201d7f47
TG
206 } else {
207 irq_domain_activate_irq(&desc->irq_data);
208 if (desc->irq_data.chip->irq_startup) {
209 ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
210 irq_state_clr_disabled(desc);
211 irq_state_clr_masked(desc);
212 } else {
213 irq_enable(desc);
214 }
215 irq_state_set_started(desc);
2e051552
TG
216 /* Set default affinity mask once everything is setup */
217 irq_setup_affinity(desc);
3aae994f 218 }
201d7f47 219
b4bc724e 220 if (resend)
0798abeb 221 check_irq_resend(desc);
201d7f47 222
b4bc724e 223 return ret;
46999238
TG
224}
225
201d7f47
TG
226static void __irq_disable(struct irq_desc *desc, bool mask);
227
46999238
TG
228void irq_shutdown(struct irq_desc *desc)
229{
201d7f47
TG
230 if (irqd_is_started(&desc->irq_data)) {
231 desc->depth = 1;
232 if (desc->irq_data.chip->irq_shutdown) {
233 desc->irq_data.chip->irq_shutdown(&desc->irq_data);
234 irq_state_set_disabled(desc);
235 irq_state_set_masked(desc);
236 } else {
237 __irq_disable(desc, true);
238 }
239 irq_state_clr_started(desc);
240 }
241 /*
242 * This must be called even if the interrupt was never started up,
243 * because the activation can happen before the interrupt is
244 * available for request/startup. It has it's own state tracking so
245 * it's safe to call it unconditionally.
246 */
f8264e34 247 irq_domain_deactivate_irq(&desc->irq_data);
46999238
TG
248}
249
87923470
TG
250void irq_enable(struct irq_desc *desc)
251{
c1594b77 252 irq_state_clr_disabled(desc);
50f7c032
TG
253 if (desc->irq_data.chip->irq_enable)
254 desc->irq_data.chip->irq_enable(&desc->irq_data);
255 else
256 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 257 irq_state_clr_masked(desc);
dd87eb3a
TG
258}
259
201d7f47
TG
260static void __irq_disable(struct irq_desc *desc, bool mask)
261{
262 irq_state_set_disabled(desc);
263 if (desc->irq_data.chip->irq_disable) {
264 desc->irq_data.chip->irq_disable(&desc->irq_data);
265 irq_state_set_masked(desc);
266 } else if (mask) {
267 mask_irq(desc);
268 }
269}
270
d671a605 271/**
f788e7bf 272 * irq_disable - Mark interrupt disabled
d671a605
AF
273 * @desc: irq descriptor which should be disabled
274 *
275 * If the chip does not implement the irq_disable callback, we
276 * use a lazy disable approach. That means we mark the interrupt
277 * disabled, but leave the hardware unmasked. That's an
278 * optimization because we avoid the hardware access for the
279 * common case where no interrupt happens after we marked it
280 * disabled. If an interrupt happens, then the interrupt flow
281 * handler masks the line at the hardware level and marks it
282 * pending.
e9849777
TG
283 *
284 * If the interrupt chip does not implement the irq_disable callback,
285 * a driver can disable the lazy approach for a particular irq line by
286 * calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can
287 * be used for devices which cannot disable the interrupt at the
288 * device level under certain circumstances and have to use
289 * disable_irq[_nosync] instead.
d671a605 290 */
50f7c032 291void irq_disable(struct irq_desc *desc)
89d694b9 292{
201d7f47 293 __irq_disable(desc, irq_settings_disable_unlazy(desc));
89d694b9
TG
294}
295
31d9d9b6
MZ
296void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu)
297{
298 if (desc->irq_data.chip->irq_enable)
299 desc->irq_data.chip->irq_enable(&desc->irq_data);
300 else
301 desc->irq_data.chip->irq_unmask(&desc->irq_data);
302 cpumask_set_cpu(cpu, desc->percpu_enabled);
303}
304
305void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu)
306{
307 if (desc->irq_data.chip->irq_disable)
308 desc->irq_data.chip->irq_disable(&desc->irq_data);
309 else
310 desc->irq_data.chip->irq_mask(&desc->irq_data);
311 cpumask_clear_cpu(cpu, desc->percpu_enabled);
312}
313
9205e31d 314static inline void mask_ack_irq(struct irq_desc *desc)
dd87eb3a 315{
9205e31d
TG
316 if (desc->irq_data.chip->irq_mask_ack)
317 desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
dd87eb3a 318 else {
e2c0f8ff 319 desc->irq_data.chip->irq_mask(&desc->irq_data);
22a49163
TG
320 if (desc->irq_data.chip->irq_ack)
321 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 322 }
6e40262e 323 irq_state_set_masked(desc);
0b1adaa0
TG
324}
325
d4d5e089 326void mask_irq(struct irq_desc *desc)
0b1adaa0 327{
e2c0f8ff
TG
328 if (desc->irq_data.chip->irq_mask) {
329 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 330 irq_state_set_masked(desc);
0b1adaa0
TG
331 }
332}
333
d4d5e089 334void unmask_irq(struct irq_desc *desc)
0b1adaa0 335{
0eda58b7
TG
336 if (desc->irq_data.chip->irq_unmask) {
337 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 338 irq_state_clr_masked(desc);
0b1adaa0 339 }
dd87eb3a
TG
340}
341
328a4978
TG
342void unmask_threaded_irq(struct irq_desc *desc)
343{
344 struct irq_chip *chip = desc->irq_data.chip;
345
346 if (chip->flags & IRQCHIP_EOI_THREADED)
347 chip->irq_eoi(&desc->irq_data);
348
349 if (chip->irq_unmask) {
350 chip->irq_unmask(&desc->irq_data);
351 irq_state_clr_masked(desc);
352 }
353}
354
399b5da2
TG
355/*
356 * handle_nested_irq - Handle a nested irq from a irq thread
357 * @irq: the interrupt number
358 *
359 * Handle interrupts which are nested into a threaded interrupt
360 * handler. The handler function is called inside the calling
361 * threads context.
362 */
363void handle_nested_irq(unsigned int irq)
364{
365 struct irq_desc *desc = irq_to_desc(irq);
366 struct irqaction *action;
367 irqreturn_t action_ret;
368
369 might_sleep();
370
239007b8 371 raw_spin_lock_irq(&desc->lock);
399b5da2 372
293a7a0a 373 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
399b5da2
TG
374
375 action = desc->action;
23812b9d
NJ
376 if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) {
377 desc->istate |= IRQS_PENDING;
399b5da2 378 goto out_unlock;
23812b9d 379 }
399b5da2 380
a946e8c7 381 kstat_incr_irqs_this_cpu(desc);
32f4125e 382 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
239007b8 383 raw_spin_unlock_irq(&desc->lock);
399b5da2 384
45e52022
CK
385 action_ret = IRQ_NONE;
386 for_each_action_of_desc(desc, action)
387 action_ret |= action->thread_fn(action->irq, action->dev_id);
388
399b5da2 389 if (!noirqdebug)
0dcdbc97 390 note_interrupt(desc, action_ret);
399b5da2 391
239007b8 392 raw_spin_lock_irq(&desc->lock);
32f4125e 393 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
399b5da2
TG
394
395out_unlock:
239007b8 396 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
397}
398EXPORT_SYMBOL_GPL(handle_nested_irq);
399
fe200ae4
TG
400static bool irq_check_poll(struct irq_desc *desc)
401{
6954b75b 402 if (!(desc->istate & IRQS_POLL_INPROGRESS))
fe200ae4
TG
403 return false;
404 return irq_wait_for_poll(desc);
405}
406
c7bd3ec0
TG
407static bool irq_may_run(struct irq_desc *desc)
408{
9ce7a258
TG
409 unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED;
410
411 /*
412 * If the interrupt is not in progress and is not an armed
413 * wakeup interrupt, proceed.
414 */
415 if (!irqd_has_set(&desc->irq_data, mask))
c7bd3ec0 416 return true;
9ce7a258
TG
417
418 /*
419 * If the interrupt is an armed wakeup source, mark it pending
420 * and suspended, disable it and notify the pm core about the
421 * event.
422 */
423 if (irq_pm_check_wakeup(desc))
424 return false;
425
426 /*
427 * Handle a potential concurrent poll on a different core.
428 */
c7bd3ec0
TG
429 return irq_check_poll(desc);
430}
431
dd87eb3a
TG
432/**
433 * handle_simple_irq - Simple and software-decoded IRQs.
dd87eb3a 434 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
435 *
436 * Simple interrupts are either sent from a demultiplexing interrupt
437 * handler or come from hardware, where no interrupt hardware control
438 * is necessary.
439 *
440 * Note: The caller is expected to handle the ack, clear, mask and
441 * unmask issues if necessary.
442 */
bd0b9ac4 443void handle_simple_irq(struct irq_desc *desc)
dd87eb3a 444{
239007b8 445 raw_spin_lock(&desc->lock);
dd87eb3a 446
c7bd3ec0
TG
447 if (!irq_may_run(desc))
448 goto out_unlock;
fe200ae4 449
163ef309 450 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a 451
23812b9d
NJ
452 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
453 desc->istate |= IRQS_PENDING;
dd87eb3a 454 goto out_unlock;
23812b9d 455 }
dd87eb3a 456
a946e8c7 457 kstat_incr_irqs_this_cpu(desc);
107781e7 458 handle_irq_event(desc);
dd87eb3a 459
dd87eb3a 460out_unlock:
239007b8 461 raw_spin_unlock(&desc->lock);
dd87eb3a 462}
edf76f83 463EXPORT_SYMBOL_GPL(handle_simple_irq);
dd87eb3a 464
edd14cfe
KB
465/**
466 * handle_untracked_irq - Simple and software-decoded IRQs.
467 * @desc: the interrupt description structure for this irq
468 *
469 * Untracked interrupts are sent from a demultiplexing interrupt
470 * handler when the demultiplexer does not know which device it its
471 * multiplexed irq domain generated the interrupt. IRQ's handled
472 * through here are not subjected to stats tracking, randomness, or
473 * spurious interrupt detection.
474 *
475 * Note: Like handle_simple_irq, the caller is expected to handle
476 * the ack, clear, mask and unmask issues if necessary.
477 */
478void handle_untracked_irq(struct irq_desc *desc)
479{
480 unsigned int flags = 0;
481
482 raw_spin_lock(&desc->lock);
483
484 if (!irq_may_run(desc))
485 goto out_unlock;
486
487 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
488
489 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
490 desc->istate |= IRQS_PENDING;
491 goto out_unlock;
492 }
493
494 desc->istate &= ~IRQS_PENDING;
495 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
496 raw_spin_unlock(&desc->lock);
497
498 __handle_irq_event_percpu(desc, &flags);
499
500 raw_spin_lock(&desc->lock);
501 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
502
503out_unlock:
504 raw_spin_unlock(&desc->lock);
505}
506EXPORT_SYMBOL_GPL(handle_untracked_irq);
507
ac563761
TG
508/*
509 * Called unconditionally from handle_level_irq() and only for oneshot
510 * interrupts from handle_fasteoi_irq()
511 */
512static void cond_unmask_irq(struct irq_desc *desc)
513{
514 /*
515 * We need to unmask in the following cases:
516 * - Standard level irq (IRQF_ONESHOT is not set)
517 * - Oneshot irq which did not wake the thread (caused by a
518 * spurious interrupt or a primary handler handling it
519 * completely).
520 */
521 if (!irqd_irq_disabled(&desc->irq_data) &&
522 irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot)
523 unmask_irq(desc);
524}
525
dd87eb3a
TG
526/**
527 * handle_level_irq - Level type irq handler
dd87eb3a 528 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
529 *
530 * Level type interrupts are active as long as the hardware line has
531 * the active level. This may require to mask the interrupt and unmask
532 * it after the associated handler has acknowledged the device, so the
533 * interrupt line is back to inactive.
534 */
bd0b9ac4 535void handle_level_irq(struct irq_desc *desc)
dd87eb3a 536{
239007b8 537 raw_spin_lock(&desc->lock);
9205e31d 538 mask_ack_irq(desc);
dd87eb3a 539
c7bd3ec0
TG
540 if (!irq_may_run(desc))
541 goto out_unlock;
fe200ae4 542
163ef309 543 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
544
545 /*
546 * If its disabled or no action available
547 * keep it masked and get out of here
548 */
d4dc0f90
TG
549 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
550 desc->istate |= IRQS_PENDING;
86998aa6 551 goto out_unlock;
d4dc0f90 552 }
dd87eb3a 553
a946e8c7 554 kstat_incr_irqs_this_cpu(desc);
1529866c 555 handle_irq_event(desc);
b25c340c 556
ac563761
TG
557 cond_unmask_irq(desc);
558
86998aa6 559out_unlock:
239007b8 560 raw_spin_unlock(&desc->lock);
dd87eb3a 561}
14819ea1 562EXPORT_SYMBOL_GPL(handle_level_irq);
dd87eb3a 563
78129576
TG
564#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
565static inline void preflow_handler(struct irq_desc *desc)
566{
567 if (desc->preflow_handler)
568 desc->preflow_handler(&desc->irq_data);
569}
570#else
571static inline void preflow_handler(struct irq_desc *desc) { }
572#endif
573
328a4978
TG
574static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
575{
576 if (!(desc->istate & IRQS_ONESHOT)) {
577 chip->irq_eoi(&desc->irq_data);
578 return;
579 }
580 /*
581 * We need to unmask in the following cases:
582 * - Oneshot irq which did not wake the thread (caused by a
583 * spurious interrupt or a primary handler handling it
584 * completely).
585 */
586 if (!irqd_irq_disabled(&desc->irq_data) &&
587 irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) {
588 chip->irq_eoi(&desc->irq_data);
589 unmask_irq(desc);
590 } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) {
591 chip->irq_eoi(&desc->irq_data);
592 }
593}
594
dd87eb3a 595/**
47c2a3aa 596 * handle_fasteoi_irq - irq handler for transparent controllers
dd87eb3a 597 * @desc: the interrupt description structure for this irq
dd87eb3a 598 *
47c2a3aa 599 * Only a single callback will be issued to the chip: an ->eoi()
dd87eb3a
TG
600 * call when the interrupt has been serviced. This enables support
601 * for modern forms of interrupt handlers, which handle the flow
602 * details in hardware, transparently.
603 */
bd0b9ac4 604void handle_fasteoi_irq(struct irq_desc *desc)
dd87eb3a 605{
328a4978
TG
606 struct irq_chip *chip = desc->irq_data.chip;
607
239007b8 608 raw_spin_lock(&desc->lock);
dd87eb3a 609
c7bd3ec0
TG
610 if (!irq_may_run(desc))
611 goto out;
dd87eb3a 612
163ef309 613 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
614
615 /*
616 * If its disabled or no action available
76d21601 617 * then mask it and get out of here:
dd87eb3a 618 */
32f4125e 619 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
2a0d6fb3 620 desc->istate |= IRQS_PENDING;
e2c0f8ff 621 mask_irq(desc);
dd87eb3a 622 goto out;
98bb244b 623 }
c69e3758 624
a946e8c7 625 kstat_incr_irqs_this_cpu(desc);
c69e3758
TG
626 if (desc->istate & IRQS_ONESHOT)
627 mask_irq(desc);
628
78129576 629 preflow_handler(desc);
a7ae4de5 630 handle_irq_event(desc);
77694b40 631
328a4978 632 cond_unmask_eoi_irq(desc, chip);
ac563761 633
239007b8 634 raw_spin_unlock(&desc->lock);
77694b40
TG
635 return;
636out:
328a4978
TG
637 if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
638 chip->irq_eoi(&desc->irq_data);
639 raw_spin_unlock(&desc->lock);
dd87eb3a 640}
7cad45ee 641EXPORT_SYMBOL_GPL(handle_fasteoi_irq);
dd87eb3a
TG
642
643/**
644 * handle_edge_irq - edge type IRQ handler
dd87eb3a 645 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
646 *
647 * Interrupt occures on the falling and/or rising edge of a hardware
25985edc 648 * signal. The occurrence is latched into the irq controller hardware
dd87eb3a
TG
649 * and must be acked in order to be reenabled. After the ack another
650 * interrupt can happen on the same source even before the first one
dfff0615 651 * is handled by the associated event handler. If this happens it
dd87eb3a
TG
652 * might be necessary to disable (mask) the interrupt depending on the
653 * controller hardware. This requires to reenable the interrupt inside
654 * of the loop which handles the interrupts which have arrived while
655 * the handler was running. If all pending interrupts are handled, the
656 * loop is left.
657 */
bd0b9ac4 658void handle_edge_irq(struct irq_desc *desc)
dd87eb3a 659{
239007b8 660 raw_spin_lock(&desc->lock);
dd87eb3a 661
163ef309 662 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
c3d7acd0 663
c7bd3ec0
TG
664 if (!irq_may_run(desc)) {
665 desc->istate |= IRQS_PENDING;
666 mask_ack_irq(desc);
667 goto out_unlock;
dd87eb3a 668 }
c3d7acd0 669
dd87eb3a 670 /*
c3d7acd0
TG
671 * If its disabled or no action available then mask it and get
672 * out of here.
dd87eb3a 673 */
c3d7acd0
TG
674 if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
675 desc->istate |= IRQS_PENDING;
676 mask_ack_irq(desc);
677 goto out_unlock;
dd87eb3a 678 }
c3d7acd0 679
b51bf95c 680 kstat_incr_irqs_this_cpu(desc);
dd87eb3a
TG
681
682 /* Start handling the irq */
22a49163 683 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 684
dd87eb3a 685 do {
a60a5dc2 686 if (unlikely(!desc->action)) {
e2c0f8ff 687 mask_irq(desc);
dd87eb3a
TG
688 goto out_unlock;
689 }
690
691 /*
692 * When another irq arrived while we were handling
693 * one, we could have masked the irq.
694 * Renable it, if it was not disabled in meantime.
695 */
2a0d6fb3 696 if (unlikely(desc->istate & IRQS_PENDING)) {
32f4125e
TG
697 if (!irqd_irq_disabled(&desc->irq_data) &&
698 irqd_irq_masked(&desc->irq_data))
c1594b77 699 unmask_irq(desc);
dd87eb3a
TG
700 }
701
a60a5dc2 702 handle_irq_event(desc);
dd87eb3a 703
2a0d6fb3 704 } while ((desc->istate & IRQS_PENDING) &&
32f4125e 705 !irqd_irq_disabled(&desc->irq_data));
dd87eb3a 706
dd87eb3a 707out_unlock:
239007b8 708 raw_spin_unlock(&desc->lock);
dd87eb3a 709}
3911ff30 710EXPORT_SYMBOL(handle_edge_irq);
dd87eb3a 711
0521c8fb
TG
712#ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
713/**
714 * handle_edge_eoi_irq - edge eoi type IRQ handler
0521c8fb
TG
715 * @desc: the interrupt description structure for this irq
716 *
717 * Similar as the above handle_edge_irq, but using eoi and w/o the
718 * mask/unmask logic.
719 */
bd0b9ac4 720void handle_edge_eoi_irq(struct irq_desc *desc)
0521c8fb
TG
721{
722 struct irq_chip *chip = irq_desc_get_chip(desc);
723
724 raw_spin_lock(&desc->lock);
725
726 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
c3d7acd0 727
c7bd3ec0
TG
728 if (!irq_may_run(desc)) {
729 desc->istate |= IRQS_PENDING;
730 goto out_eoi;
0521c8fb 731 }
c3d7acd0 732
0521c8fb 733 /*
c3d7acd0
TG
734 * If its disabled or no action available then mask it and get
735 * out of here.
0521c8fb 736 */
c3d7acd0
TG
737 if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
738 desc->istate |= IRQS_PENDING;
739 goto out_eoi;
0521c8fb 740 }
c3d7acd0 741
b51bf95c 742 kstat_incr_irqs_this_cpu(desc);
0521c8fb
TG
743
744 do {
745 if (unlikely(!desc->action))
746 goto out_eoi;
747
748 handle_irq_event(desc);
749
750 } while ((desc->istate & IRQS_PENDING) &&
751 !irqd_irq_disabled(&desc->irq_data));
752
ac0e0447 753out_eoi:
0521c8fb
TG
754 chip->irq_eoi(&desc->irq_data);
755 raw_spin_unlock(&desc->lock);
756}
757#endif
758
dd87eb3a 759/**
24b26d42 760 * handle_percpu_irq - Per CPU local irq handler
dd87eb3a 761 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
762 *
763 * Per CPU interrupts on SMP machines without locking requirements
764 */
bd0b9ac4 765void handle_percpu_irq(struct irq_desc *desc)
dd87eb3a 766{
35e857cb 767 struct irq_chip *chip = irq_desc_get_chip(desc);
dd87eb3a 768
b51bf95c 769 kstat_incr_irqs_this_cpu(desc);
dd87eb3a 770
849f061c
TG
771 if (chip->irq_ack)
772 chip->irq_ack(&desc->irq_data);
dd87eb3a 773
71f64340 774 handle_irq_event_percpu(desc);
dd87eb3a 775
849f061c
TG
776 if (chip->irq_eoi)
777 chip->irq_eoi(&desc->irq_data);
dd87eb3a
TG
778}
779
31d9d9b6
MZ
780/**
781 * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
31d9d9b6
MZ
782 * @desc: the interrupt description structure for this irq
783 *
784 * Per CPU interrupts on SMP machines without locking requirements. Same as
785 * handle_percpu_irq() above but with the following extras:
786 *
787 * action->percpu_dev_id is a pointer to percpu variables which
788 * contain the real device id for the cpu on which this handler is
789 * called
790 */
bd0b9ac4 791void handle_percpu_devid_irq(struct irq_desc *desc)
31d9d9b6
MZ
792{
793 struct irq_chip *chip = irq_desc_get_chip(desc);
794 struct irqaction *action = desc->action;
bd0b9ac4 795 unsigned int irq = irq_desc_get_irq(desc);
31d9d9b6
MZ
796 irqreturn_t res;
797
b51bf95c 798 kstat_incr_irqs_this_cpu(desc);
31d9d9b6
MZ
799
800 if (chip->irq_ack)
801 chip->irq_ack(&desc->irq_data);
802
fc590c22
TG
803 if (likely(action)) {
804 trace_irq_handler_entry(irq, action);
805 res = action->handler(irq, raw_cpu_ptr(action->percpu_dev_id));
806 trace_irq_handler_exit(irq, action, res);
807 } else {
808 unsigned int cpu = smp_processor_id();
809 bool enabled = cpumask_test_cpu(cpu, desc->percpu_enabled);
810
811 if (enabled)
812 irq_percpu_disable(desc, cpu);
813
814 pr_err_once("Spurious%s percpu IRQ%u on CPU%u\n",
815 enabled ? " and unmasked" : "", irq, cpu);
816 }
31d9d9b6
MZ
817
818 if (chip->irq_eoi)
819 chip->irq_eoi(&desc->irq_data);
820}
821
b8129a1f 822static void
3b0f95be
RK
823__irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle,
824 int is_chained, const char *name)
dd87eb3a 825{
091738a2 826 if (!handle) {
dd87eb3a 827 handle = handle_bad_irq;
091738a2 828 } else {
f86eff22
MZ
829 struct irq_data *irq_data = &desc->irq_data;
830#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
831 /*
832 * With hierarchical domains we might run into a
833 * situation where the outermost chip is not yet set
834 * up, but the inner chips are there. Instead of
835 * bailing we install the handler, but obviously we
836 * cannot enable/startup the interrupt at this point.
837 */
838 while (irq_data) {
839 if (irq_data->chip != &no_irq_chip)
840 break;
841 /*
842 * Bail out if the outer chip is not set up
843 * and the interrrupt supposed to be started
844 * right away.
845 */
846 if (WARN_ON(is_chained))
3b0f95be 847 return;
f86eff22
MZ
848 /* Try the parent */
849 irq_data = irq_data->parent_data;
850 }
851#endif
852 if (WARN_ON(!irq_data || irq_data->chip == &no_irq_chip))
3b0f95be 853 return;
f8b5473f 854 }
dd87eb3a 855
dd87eb3a
TG
856 /* Uninstall? */
857 if (handle == handle_bad_irq) {
6b8ff312 858 if (desc->irq_data.chip != &no_irq_chip)
9205e31d 859 mask_ack_irq(desc);
801a0e9a 860 irq_state_set_disabled(desc);
e509bd7d
MW
861 if (is_chained)
862 desc->action = NULL;
dd87eb3a
TG
863 desc->depth = 1;
864 }
865 desc->handle_irq = handle;
a460e745 866 desc->name = name;
dd87eb3a
TG
867
868 if (handle != handle_bad_irq && is_chained) {
1984e075
MZ
869 unsigned int type = irqd_get_trigger_type(&desc->irq_data);
870
1e12c4a9
MZ
871 /*
872 * We're about to start this interrupt immediately,
873 * hence the need to set the trigger configuration.
874 * But the .set_type callback may have overridden the
875 * flow handler, ignoring that we're dealing with a
876 * chained interrupt. Reset it immediately because we
877 * do know better.
878 */
1984e075
MZ
879 if (type != IRQ_TYPE_NONE) {
880 __irq_set_trigger(desc, type);
881 desc->handle_irq = handle;
882 }
1e12c4a9 883
1ccb4e61
TG
884 irq_settings_set_noprobe(desc);
885 irq_settings_set_norequest(desc);
7f1b1244 886 irq_settings_set_nothread(desc);
e509bd7d 887 desc->action = &chained_action;
b4bc724e 888 irq_startup(desc, true);
dd87eb3a 889 }
3b0f95be
RK
890}
891
892void
893__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
894 const char *name)
895{
896 unsigned long flags;
897 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
898
899 if (!desc)
900 return;
901
902 __irq_do_set_handler(desc, handle, is_chained, name);
02725e74 903 irq_put_desc_busunlock(desc, flags);
dd87eb3a 904}
3836ca08 905EXPORT_SYMBOL_GPL(__irq_set_handler);
dd87eb3a 906
3b0f95be
RK
907void
908irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
909 void *data)
910{
911 unsigned long flags;
912 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
913
914 if (!desc)
915 return;
916
af7080e0 917 desc->irq_common_data.handler_data = data;
2c4569ca 918 __irq_do_set_handler(desc, handle, 1, NULL);
3b0f95be
RK
919
920 irq_put_desc_busunlock(desc, flags);
921}
922EXPORT_SYMBOL_GPL(irq_set_chained_handler_and_data);
923
dd87eb3a 924void
3836ca08 925irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
a460e745 926 irq_flow_handler_t handle, const char *name)
dd87eb3a 927{
35e857cb 928 irq_set_chip(irq, chip);
3836ca08 929 __irq_set_handler(irq, handle, 0, name);
dd87eb3a 930}
b3ae66f2 931EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name);
46f4f8f6 932
44247184 933void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
46f4f8f6 934{
46f4f8f6 935 unsigned long flags;
31d9d9b6 936 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
46f4f8f6 937
44247184 938 if (!desc)
46f4f8f6 939 return;
04c848d3
TG
940
941 /*
942 * Warn when a driver sets the no autoenable flag on an already
943 * active interrupt.
944 */
945 WARN_ON_ONCE(!desc->depth && (set & _IRQ_NOAUTOEN));
946
a005677b
TG
947 irq_settings_clr_and_set(desc, clr, set);
948
876dbd4c 949 irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
e1ef8241 950 IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
a005677b
TG
951 if (irq_settings_has_no_balance_set(desc))
952 irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
953 if (irq_settings_is_per_cpu(desc))
954 irqd_set(&desc->irq_data, IRQD_PER_CPU);
e1ef8241
TG
955 if (irq_settings_can_move_pcntxt(desc))
956 irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
0ef5ca1e
TG
957 if (irq_settings_is_level(desc))
958 irqd_set(&desc->irq_data, IRQD_LEVEL);
a005677b 959
876dbd4c
TG
960 irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc));
961
02725e74 962 irq_put_desc_unlock(desc, flags);
46f4f8f6 963}
edf76f83 964EXPORT_SYMBOL_GPL(irq_modify_status);
0fdb4b25
DD
965
966/**
967 * irq_cpu_online - Invoke all irq_cpu_online functions.
968 *
969 * Iterate through all irqs and invoke the chip.irq_cpu_online()
970 * for each.
971 */
972void irq_cpu_online(void)
973{
974 struct irq_desc *desc;
975 struct irq_chip *chip;
976 unsigned long flags;
977 unsigned int irq;
978
979 for_each_active_irq(irq) {
980 desc = irq_to_desc(irq);
981 if (!desc)
982 continue;
983
984 raw_spin_lock_irqsave(&desc->lock, flags);
985
986 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
987 if (chip && chip->irq_cpu_online &&
988 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 989 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
990 chip->irq_cpu_online(&desc->irq_data);
991
992 raw_spin_unlock_irqrestore(&desc->lock, flags);
993 }
994}
995
996/**
997 * irq_cpu_offline - Invoke all irq_cpu_offline functions.
998 *
999 * Iterate through all irqs and invoke the chip.irq_cpu_offline()
1000 * for each.
1001 */
1002void irq_cpu_offline(void)
1003{
1004 struct irq_desc *desc;
1005 struct irq_chip *chip;
1006 unsigned long flags;
1007 unsigned int irq;
1008
1009 for_each_active_irq(irq) {
1010 desc = irq_to_desc(irq);
1011 if (!desc)
1012 continue;
1013
1014 raw_spin_lock_irqsave(&desc->lock, flags);
1015
1016 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
1017 if (chip && chip->irq_cpu_offline &&
1018 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 1019 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
1020 chip->irq_cpu_offline(&desc->irq_data);
1021
1022 raw_spin_unlock_irqrestore(&desc->lock, flags);
1023 }
1024}
85f08c17
JL
1025
1026#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
3cfeffc2
SA
1027/**
1028 * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if
1029 * NULL)
1030 * @data: Pointer to interrupt specific data
1031 */
1032void irq_chip_enable_parent(struct irq_data *data)
1033{
1034 data = data->parent_data;
1035 if (data->chip->irq_enable)
1036 data->chip->irq_enable(data);
1037 else
1038 data->chip->irq_unmask(data);
1039}
1040
1041/**
1042 * irq_chip_disable_parent - Disable the parent interrupt (defaults to mask if
1043 * NULL)
1044 * @data: Pointer to interrupt specific data
1045 */
1046void irq_chip_disable_parent(struct irq_data *data)
1047{
1048 data = data->parent_data;
1049 if (data->chip->irq_disable)
1050 data->chip->irq_disable(data);
1051 else
1052 data->chip->irq_mask(data);
1053}
1054
85f08c17
JL
1055/**
1056 * irq_chip_ack_parent - Acknowledge the parent interrupt
1057 * @data: Pointer to interrupt specific data
1058 */
1059void irq_chip_ack_parent(struct irq_data *data)
1060{
1061 data = data->parent_data;
1062 data->chip->irq_ack(data);
1063}
a4289dc2 1064EXPORT_SYMBOL_GPL(irq_chip_ack_parent);
85f08c17 1065
56e8abab
YC
1066/**
1067 * irq_chip_mask_parent - Mask the parent interrupt
1068 * @data: Pointer to interrupt specific data
1069 */
1070void irq_chip_mask_parent(struct irq_data *data)
1071{
1072 data = data->parent_data;
1073 data->chip->irq_mask(data);
1074}
52b2a05f 1075EXPORT_SYMBOL_GPL(irq_chip_mask_parent);
56e8abab
YC
1076
1077/**
1078 * irq_chip_unmask_parent - Unmask the parent interrupt
1079 * @data: Pointer to interrupt specific data
1080 */
1081void irq_chip_unmask_parent(struct irq_data *data)
1082{
1083 data = data->parent_data;
1084 data->chip->irq_unmask(data);
1085}
52b2a05f 1086EXPORT_SYMBOL_GPL(irq_chip_unmask_parent);
56e8abab
YC
1087
1088/**
1089 * irq_chip_eoi_parent - Invoke EOI on the parent interrupt
1090 * @data: Pointer to interrupt specific data
1091 */
1092void irq_chip_eoi_parent(struct irq_data *data)
1093{
1094 data = data->parent_data;
1095 data->chip->irq_eoi(data);
1096}
52b2a05f 1097EXPORT_SYMBOL_GPL(irq_chip_eoi_parent);
56e8abab
YC
1098
1099/**
1100 * irq_chip_set_affinity_parent - Set affinity on the parent interrupt
1101 * @data: Pointer to interrupt specific data
1102 * @dest: The affinity mask to set
1103 * @force: Flag to enforce setting (disable online checks)
1104 *
1105 * Conditinal, as the underlying parent chip might not implement it.
1106 */
1107int irq_chip_set_affinity_parent(struct irq_data *data,
1108 const struct cpumask *dest, bool force)
1109{
1110 data = data->parent_data;
1111 if (data->chip->irq_set_affinity)
1112 return data->chip->irq_set_affinity(data, dest, force);
b7560de1
GS
1113
1114 return -ENOSYS;
1115}
1116
1117/**
1118 * irq_chip_set_type_parent - Set IRQ type on the parent interrupt
1119 * @data: Pointer to interrupt specific data
1120 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
1121 *
1122 * Conditional, as the underlying parent chip might not implement it.
1123 */
1124int irq_chip_set_type_parent(struct irq_data *data, unsigned int type)
1125{
1126 data = data->parent_data;
1127
1128 if (data->chip->irq_set_type)
1129 return data->chip->irq_set_type(data, type);
56e8abab
YC
1130
1131 return -ENOSYS;
1132}
52b2a05f 1133EXPORT_SYMBOL_GPL(irq_chip_set_type_parent);
56e8abab 1134
85f08c17
JL
1135/**
1136 * irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware
1137 * @data: Pointer to interrupt specific data
1138 *
1139 * Iterate through the domain hierarchy of the interrupt and check
1140 * whether a hw retrigger function exists. If yes, invoke it.
1141 */
1142int irq_chip_retrigger_hierarchy(struct irq_data *data)
1143{
1144 for (data = data->parent_data; data; data = data->parent_data)
1145 if (data->chip && data->chip->irq_retrigger)
1146 return data->chip->irq_retrigger(data);
1147
6d4affea 1148 return 0;
85f08c17 1149}
08b55e2a 1150
0a4377de
JL
1151/**
1152 * irq_chip_set_vcpu_affinity_parent - Set vcpu affinity on the parent interrupt
1153 * @data: Pointer to interrupt specific data
8505a81b 1154 * @vcpu_info: The vcpu affinity information
0a4377de
JL
1155 */
1156int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info)
1157{
1158 data = data->parent_data;
1159 if (data->chip->irq_set_vcpu_affinity)
1160 return data->chip->irq_set_vcpu_affinity(data, vcpu_info);
1161
1162 return -ENOSYS;
1163}
1164
08b55e2a
MZ
1165/**
1166 * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
1167 * @data: Pointer to interrupt specific data
1168 * @on: Whether to set or reset the wake-up capability of this irq
1169 *
1170 * Conditional, as the underlying parent chip might not implement it.
1171 */
1172int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
1173{
1174 data = data->parent_data;
1175 if (data->chip->irq_set_wake)
1176 return data->chip->irq_set_wake(data, on);
1177
1178 return -ENOSYS;
1179}
85f08c17 1180#endif
515085ef
JL
1181
1182/**
1183 * irq_chip_compose_msi_msg - Componse msi message for a irq chip
1184 * @data: Pointer to interrupt specific data
1185 * @msg: Pointer to the MSI message
1186 *
1187 * For hierarchical domains we find the first chip in the hierarchy
1188 * which implements the irq_compose_msi_msg callback. For non
1189 * hierarchical we use the top level chip.
1190 */
1191int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
1192{
1193 struct irq_data *pos = NULL;
1194
1195#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
1196 for (; data; data = data->parent_data)
1197#endif
1198 if (data->chip && data->chip->irq_compose_msi_msg)
1199 pos = data;
1200 if (!pos)
1201 return -ENOSYS;
1202
1203 pos->chip->irq_compose_msi_msg(pos, msg);
1204
1205 return 0;
1206}
be45beb2
JH
1207
1208/**
1209 * irq_chip_pm_get - Enable power for an IRQ chip
1210 * @data: Pointer to interrupt specific data
1211 *
1212 * Enable the power to the IRQ chip referenced by the interrupt data
1213 * structure.
1214 */
1215int irq_chip_pm_get(struct irq_data *data)
1216{
1217 int retval;
1218
1219 if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) {
1220 retval = pm_runtime_get_sync(data->chip->parent_device);
1221 if (retval < 0) {
1222 pm_runtime_put_noidle(data->chip->parent_device);
1223 return retval;
1224 }
1225 }
1226
1227 return 0;
1228}
1229
1230/**
1231 * irq_chip_pm_put - Disable power for an IRQ chip
1232 * @data: Pointer to interrupt specific data
1233 *
1234 * Disable the power to the IRQ chip referenced by the interrupt data
1235 * structure, belongs. Note that power will only be disabled, once this
1236 * function has been called for all IRQs that have called irq_chip_pm_get().
1237 */
1238int irq_chip_pm_put(struct irq_data *data)
1239{
1240 int retval = 0;
1241
1242 if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device)
1243 retval = pm_runtime_put(data->chip->parent_device);
1244
1245 return (retval < 0) ? retval : 0;
1246}