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Commit | Line | Data |
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dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
18 | ||
19 | #include "internals.h" | |
20 | ||
21 | /** | |
a0cd9ca2 | 22 | * irq_set_chip - set the irq chip for an irq |
dd87eb3a TG |
23 | * @irq: irq number |
24 | * @chip: pointer to irq chip description structure | |
25 | */ | |
a0cd9ca2 | 26 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) |
dd87eb3a | 27 | { |
d3c60047 | 28 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
29 | unsigned long flags; |
30 | ||
7d94f7ca | 31 | if (!desc) { |
261c40c1 | 32 | WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq); |
dd87eb3a TG |
33 | return -EINVAL; |
34 | } | |
35 | ||
36 | if (!chip) | |
37 | chip = &no_irq_chip; | |
38 | ||
239007b8 | 39 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a | 40 | irq_chip_set_defaults(chip); |
6b8ff312 | 41 | desc->irq_data.chip = chip; |
239007b8 | 42 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
43 | |
44 | return 0; | |
45 | } | |
a0cd9ca2 | 46 | EXPORT_SYMBOL(irq_set_chip); |
dd87eb3a TG |
47 | |
48 | /** | |
a0cd9ca2 | 49 | * irq_set_type - set the irq trigger type for an irq |
dd87eb3a | 50 | * @irq: irq number |
0c5d1eb7 | 51 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a | 52 | */ |
a0cd9ca2 | 53 | int irq_set_irq_type(unsigned int irq, unsigned int type) |
dd87eb3a | 54 | { |
d3c60047 | 55 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
56 | unsigned long flags; |
57 | int ret = -ENXIO; | |
58 | ||
7d94f7ca | 59 | if (!desc) { |
dd87eb3a TG |
60 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); |
61 | return -ENODEV; | |
62 | } | |
63 | ||
f2b662da | 64 | type &= IRQ_TYPE_SENSE_MASK; |
0c5d1eb7 DB |
65 | if (type == IRQ_TYPE_NONE) |
66 | return 0; | |
67 | ||
43abe43c | 68 | chip_bus_lock(desc); |
239007b8 | 69 | raw_spin_lock_irqsave(&desc->lock, flags); |
0b3682ba | 70 | ret = __irq_set_trigger(desc, irq, type); |
239007b8 | 71 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
43abe43c | 72 | chip_bus_sync_unlock(desc); |
dd87eb3a TG |
73 | return ret; |
74 | } | |
a0cd9ca2 | 75 | EXPORT_SYMBOL(irq_set_irq_type); |
dd87eb3a TG |
76 | |
77 | /** | |
a0cd9ca2 | 78 | * irq_set_handler_data - set irq handler data for an irq |
dd87eb3a TG |
79 | * @irq: Interrupt number |
80 | * @data: Pointer to interrupt specific data | |
81 | * | |
82 | * Set the hardware irq controller data for an irq | |
83 | */ | |
a0cd9ca2 | 84 | int irq_set_handler_data(unsigned int irq, void *data) |
dd87eb3a | 85 | { |
d3c60047 | 86 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
87 | unsigned long flags; |
88 | ||
7d94f7ca | 89 | if (!desc) { |
dd87eb3a TG |
90 | printk(KERN_ERR |
91 | "Trying to install controller data for IRQ%d\n", irq); | |
92 | return -EINVAL; | |
93 | } | |
94 | ||
239007b8 | 95 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 96 | desc->irq_data.handler_data = data; |
239007b8 | 97 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
98 | return 0; |
99 | } | |
a0cd9ca2 | 100 | EXPORT_SYMBOL(irq_set_handler_data); |
dd87eb3a | 101 | |
5b912c10 | 102 | /** |
a0cd9ca2 | 103 | * irq_set_msi_desc - set MSI descriptor data for an irq |
5b912c10 | 104 | * @irq: Interrupt number |
472900b8 | 105 | * @entry: Pointer to MSI descriptor data |
5b912c10 | 106 | * |
24b26d42 | 107 | * Set the MSI descriptor entry for an irq |
5b912c10 | 108 | */ |
a0cd9ca2 | 109 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) |
5b912c10 | 110 | { |
d3c60047 | 111 | struct irq_desc *desc = irq_to_desc(irq); |
5b912c10 EB |
112 | unsigned long flags; |
113 | ||
7d94f7ca | 114 | if (!desc) { |
5b912c10 EB |
115 | printk(KERN_ERR |
116 | "Trying to install msi data for IRQ%d\n", irq); | |
117 | return -EINVAL; | |
118 | } | |
7d94f7ca | 119 | |
239007b8 | 120 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 121 | desc->irq_data.msi_desc = entry; |
7fe3730d ME |
122 | if (entry) |
123 | entry->irq = irq; | |
239007b8 | 124 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
5b912c10 EB |
125 | return 0; |
126 | } | |
127 | ||
dd87eb3a | 128 | /** |
a0cd9ca2 | 129 | * irq_set_chip_data - set irq chip data for an irq |
dd87eb3a TG |
130 | * @irq: Interrupt number |
131 | * @data: Pointer to chip specific data | |
132 | * | |
133 | * Set the hardware irq chip data for an irq | |
134 | */ | |
a0cd9ca2 | 135 | int irq_set_chip_data(unsigned int irq, void *data) |
dd87eb3a | 136 | { |
d3c60047 | 137 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
138 | unsigned long flags; |
139 | ||
7d94f7ca YL |
140 | if (!desc) { |
141 | printk(KERN_ERR | |
142 | "Trying to install chip data for IRQ%d\n", irq); | |
143 | return -EINVAL; | |
144 | } | |
145 | ||
6b8ff312 | 146 | if (!desc->irq_data.chip) { |
dd87eb3a TG |
147 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); |
148 | return -EINVAL; | |
149 | } | |
150 | ||
239007b8 | 151 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 152 | desc->irq_data.chip_data = data; |
239007b8 | 153 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
154 | |
155 | return 0; | |
156 | } | |
a0cd9ca2 | 157 | EXPORT_SYMBOL(irq_set_chip_data); |
dd87eb3a | 158 | |
f303a6dd TG |
159 | struct irq_data *irq_get_irq_data(unsigned int irq) |
160 | { | |
161 | struct irq_desc *desc = irq_to_desc(irq); | |
162 | ||
163 | return desc ? &desc->irq_data : NULL; | |
164 | } | |
165 | EXPORT_SYMBOL_GPL(irq_get_irq_data); | |
166 | ||
46999238 TG |
167 | int irq_startup(struct irq_desc *desc) |
168 | { | |
3aae994f | 169 | desc->status &= ~IRQ_DISABLED; |
46999238 TG |
170 | desc->depth = 0; |
171 | ||
3aae994f TG |
172 | if (desc->irq_data.chip->irq_startup) { |
173 | int ret = desc->irq_data.chip->irq_startup(&desc->irq_data); | |
174 | desc->status &= ~IRQ_MASKED; | |
175 | return ret; | |
176 | } | |
46999238 | 177 | |
87923470 | 178 | irq_enable(desc); |
46999238 TG |
179 | return 0; |
180 | } | |
181 | ||
182 | void irq_shutdown(struct irq_desc *desc) | |
183 | { | |
3aae994f | 184 | desc->status |= IRQ_DISABLED; |
46999238 | 185 | desc->depth = 1; |
50f7c032 TG |
186 | if (desc->irq_data.chip->irq_shutdown) |
187 | desc->irq_data.chip->irq_shutdown(&desc->irq_data); | |
188 | if (desc->irq_data.chip->irq_disable) | |
189 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
190 | else | |
191 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
3aae994f | 192 | desc->status |= IRQ_MASKED; |
46999238 TG |
193 | } |
194 | ||
87923470 TG |
195 | void irq_enable(struct irq_desc *desc) |
196 | { | |
3aae994f | 197 | desc->status &= ~IRQ_DISABLED; |
50f7c032 TG |
198 | if (desc->irq_data.chip->irq_enable) |
199 | desc->irq_data.chip->irq_enable(&desc->irq_data); | |
200 | else | |
201 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
dd87eb3a TG |
202 | desc->status &= ~IRQ_MASKED; |
203 | } | |
204 | ||
50f7c032 | 205 | void irq_disable(struct irq_desc *desc) |
89d694b9 | 206 | { |
3aae994f | 207 | desc->status |= IRQ_DISABLED; |
50f7c032 TG |
208 | if (desc->irq_data.chip->irq_disable) { |
209 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
210 | desc->status |= IRQ_MASKED; | |
211 | } | |
89d694b9 TG |
212 | } |
213 | ||
bd151412 | 214 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
3876ec9e | 215 | /* Temporary migration helpers */ |
e2c0f8ff TG |
216 | static void compat_irq_mask(struct irq_data *data) |
217 | { | |
218 | data->chip->mask(data->irq); | |
219 | } | |
220 | ||
0eda58b7 TG |
221 | static void compat_irq_unmask(struct irq_data *data) |
222 | { | |
223 | data->chip->unmask(data->irq); | |
224 | } | |
225 | ||
22a49163 TG |
226 | static void compat_irq_ack(struct irq_data *data) |
227 | { | |
228 | data->chip->ack(data->irq); | |
229 | } | |
230 | ||
9205e31d TG |
231 | static void compat_irq_mask_ack(struct irq_data *data) |
232 | { | |
233 | data->chip->mask_ack(data->irq); | |
234 | } | |
235 | ||
0c5c1557 TG |
236 | static void compat_irq_eoi(struct irq_data *data) |
237 | { | |
238 | data->chip->eoi(data->irq); | |
239 | } | |
240 | ||
c5f75634 TG |
241 | static void compat_irq_enable(struct irq_data *data) |
242 | { | |
243 | data->chip->enable(data->irq); | |
244 | } | |
245 | ||
bc310dda TG |
246 | static void compat_irq_disable(struct irq_data *data) |
247 | { | |
248 | data->chip->disable(data->irq); | |
249 | } | |
250 | ||
251 | static void compat_irq_shutdown(struct irq_data *data) | |
252 | { | |
253 | data->chip->shutdown(data->irq); | |
254 | } | |
255 | ||
37e12df7 TG |
256 | static unsigned int compat_irq_startup(struct irq_data *data) |
257 | { | |
258 | return data->chip->startup(data->irq); | |
259 | } | |
260 | ||
c96b3b3c TG |
261 | static int compat_irq_set_affinity(struct irq_data *data, |
262 | const struct cpumask *dest, bool force) | |
263 | { | |
264 | return data->chip->set_affinity(data->irq, dest); | |
265 | } | |
266 | ||
b2ba2c30 TG |
267 | static int compat_irq_set_type(struct irq_data *data, unsigned int type) |
268 | { | |
269 | return data->chip->set_type(data->irq, type); | |
270 | } | |
271 | ||
2f7e99bb TG |
272 | static int compat_irq_set_wake(struct irq_data *data, unsigned int on) |
273 | { | |
274 | return data->chip->set_wake(data->irq, on); | |
275 | } | |
276 | ||
21e2b8c6 TG |
277 | static int compat_irq_retrigger(struct irq_data *data) |
278 | { | |
279 | return data->chip->retrigger(data->irq); | |
280 | } | |
281 | ||
3876ec9e TG |
282 | static void compat_bus_lock(struct irq_data *data) |
283 | { | |
284 | data->chip->bus_lock(data->irq); | |
285 | } | |
286 | ||
287 | static void compat_bus_sync_unlock(struct irq_data *data) | |
288 | { | |
289 | data->chip->bus_sync_unlock(data->irq); | |
290 | } | |
bd151412 | 291 | #endif |
3876ec9e | 292 | |
dd87eb3a TG |
293 | /* |
294 | * Fixup enable/disable function pointers | |
295 | */ | |
296 | void irq_chip_set_defaults(struct irq_chip *chip) | |
297 | { | |
bd151412 | 298 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
c5f75634 TG |
299 | if (chip->enable) |
300 | chip->irq_enable = compat_irq_enable; | |
bc310dda TG |
301 | if (chip->disable) |
302 | chip->irq_disable = compat_irq_disable; | |
303 | if (chip->shutdown) | |
304 | chip->irq_shutdown = compat_irq_shutdown; | |
37e12df7 TG |
305 | if (chip->startup) |
306 | chip->irq_startup = compat_irq_startup; | |
b86432b4 ZY |
307 | if (!chip->end) |
308 | chip->end = dummy_irq_chip.end; | |
3876ec9e TG |
309 | if (chip->bus_lock) |
310 | chip->irq_bus_lock = compat_bus_lock; | |
311 | if (chip->bus_sync_unlock) | |
312 | chip->irq_bus_sync_unlock = compat_bus_sync_unlock; | |
e2c0f8ff TG |
313 | if (chip->mask) |
314 | chip->irq_mask = compat_irq_mask; | |
0eda58b7 TG |
315 | if (chip->unmask) |
316 | chip->irq_unmask = compat_irq_unmask; | |
22a49163 TG |
317 | if (chip->ack) |
318 | chip->irq_ack = compat_irq_ack; | |
9205e31d TG |
319 | if (chip->mask_ack) |
320 | chip->irq_mask_ack = compat_irq_mask_ack; | |
0c5c1557 TG |
321 | if (chip->eoi) |
322 | chip->irq_eoi = compat_irq_eoi; | |
c96b3b3c TG |
323 | if (chip->set_affinity) |
324 | chip->irq_set_affinity = compat_irq_set_affinity; | |
b2ba2c30 TG |
325 | if (chip->set_type) |
326 | chip->irq_set_type = compat_irq_set_type; | |
2f7e99bb TG |
327 | if (chip->set_wake) |
328 | chip->irq_set_wake = compat_irq_set_wake; | |
21e2b8c6 TG |
329 | if (chip->retrigger) |
330 | chip->irq_retrigger = compat_irq_retrigger; | |
bd151412 | 331 | #endif |
dd87eb3a TG |
332 | } |
333 | ||
9205e31d | 334 | static inline void mask_ack_irq(struct irq_desc *desc) |
dd87eb3a | 335 | { |
9205e31d TG |
336 | if (desc->irq_data.chip->irq_mask_ack) |
337 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | |
dd87eb3a | 338 | else { |
e2c0f8ff | 339 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
22a49163 TG |
340 | if (desc->irq_data.chip->irq_ack) |
341 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 342 | } |
0b1adaa0 TG |
343 | desc->status |= IRQ_MASKED; |
344 | } | |
345 | ||
e2c0f8ff | 346 | static inline void mask_irq(struct irq_desc *desc) |
0b1adaa0 | 347 | { |
e2c0f8ff TG |
348 | if (desc->irq_data.chip->irq_mask) { |
349 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
0b1adaa0 TG |
350 | desc->status |= IRQ_MASKED; |
351 | } | |
352 | } | |
353 | ||
0eda58b7 | 354 | static inline void unmask_irq(struct irq_desc *desc) |
0b1adaa0 | 355 | { |
0eda58b7 TG |
356 | if (desc->irq_data.chip->irq_unmask) { |
357 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
0b1adaa0 TG |
358 | desc->status &= ~IRQ_MASKED; |
359 | } | |
dd87eb3a TG |
360 | } |
361 | ||
399b5da2 TG |
362 | /* |
363 | * handle_nested_irq - Handle a nested irq from a irq thread | |
364 | * @irq: the interrupt number | |
365 | * | |
366 | * Handle interrupts which are nested into a threaded interrupt | |
367 | * handler. The handler function is called inside the calling | |
368 | * threads context. | |
369 | */ | |
370 | void handle_nested_irq(unsigned int irq) | |
371 | { | |
372 | struct irq_desc *desc = irq_to_desc(irq); | |
373 | struct irqaction *action; | |
374 | irqreturn_t action_ret; | |
375 | ||
376 | might_sleep(); | |
377 | ||
239007b8 | 378 | raw_spin_lock_irq(&desc->lock); |
399b5da2 TG |
379 | |
380 | kstat_incr_irqs_this_cpu(irq, desc); | |
381 | ||
382 | action = desc->action; | |
383 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) | |
384 | goto out_unlock; | |
385 | ||
386 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 387 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
388 | |
389 | action_ret = action->thread_fn(action->irq, action->dev_id); | |
390 | if (!noirqdebug) | |
391 | note_interrupt(irq, desc, action_ret); | |
392 | ||
239007b8 | 393 | raw_spin_lock_irq(&desc->lock); |
399b5da2 TG |
394 | desc->status &= ~IRQ_INPROGRESS; |
395 | ||
396 | out_unlock: | |
239007b8 | 397 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
398 | } |
399 | EXPORT_SYMBOL_GPL(handle_nested_irq); | |
400 | ||
fe200ae4 TG |
401 | static bool irq_check_poll(struct irq_desc *desc) |
402 | { | |
6954b75b | 403 | if (!(desc->istate & IRQS_POLL_INPROGRESS)) |
fe200ae4 TG |
404 | return false; |
405 | return irq_wait_for_poll(desc); | |
406 | } | |
407 | ||
dd87eb3a TG |
408 | /** |
409 | * handle_simple_irq - Simple and software-decoded IRQs. | |
410 | * @irq: the interrupt number | |
411 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
412 | * |
413 | * Simple interrupts are either sent from a demultiplexing interrupt | |
414 | * handler or come from hardware, where no interrupt hardware control | |
415 | * is necessary. | |
416 | * | |
417 | * Note: The caller is expected to handle the ack, clear, mask and | |
418 | * unmask issues if necessary. | |
419 | */ | |
7ad5b3a5 | 420 | void |
7d12e780 | 421 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 422 | { |
239007b8 | 423 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
424 | |
425 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
fe200ae4 TG |
426 | if (!irq_check_poll(desc)) |
427 | goto out_unlock; | |
428 | ||
971e5b35 | 429 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
d6c88a50 | 430 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a | 431 | |
107781e7 | 432 | if (unlikely(!desc->action || (desc->status & IRQ_DISABLED))) |
dd87eb3a TG |
433 | goto out_unlock; |
434 | ||
107781e7 | 435 | handle_irq_event(desc); |
dd87eb3a | 436 | |
dd87eb3a | 437 | out_unlock: |
239007b8 | 438 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
439 | } |
440 | ||
441 | /** | |
442 | * handle_level_irq - Level type irq handler | |
443 | * @irq: the interrupt number | |
444 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
445 | * |
446 | * Level type interrupts are active as long as the hardware line has | |
447 | * the active level. This may require to mask the interrupt and unmask | |
448 | * it after the associated handler has acknowledged the device, so the | |
449 | * interrupt line is back to inactive. | |
450 | */ | |
7ad5b3a5 | 451 | void |
7d12e780 | 452 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 453 | { |
239007b8 | 454 | raw_spin_lock(&desc->lock); |
9205e31d | 455 | mask_ack_irq(desc); |
dd87eb3a TG |
456 | |
457 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
fe200ae4 TG |
458 | if (!irq_check_poll(desc)) |
459 | goto out_unlock; | |
460 | ||
dd87eb3a | 461 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
d6c88a50 | 462 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
463 | |
464 | /* | |
465 | * If its disabled or no action available | |
466 | * keep it masked and get out of here | |
467 | */ | |
1529866c | 468 | if (unlikely(!desc->action || (desc->status & IRQ_DISABLED))) |
86998aa6 | 469 | goto out_unlock; |
dd87eb3a | 470 | |
1529866c | 471 | handle_irq_event(desc); |
b25c340c | 472 | |
0b1adaa0 | 473 | if (!(desc->status & (IRQ_DISABLED | IRQ_ONESHOT))) |
0eda58b7 | 474 | unmask_irq(desc); |
86998aa6 | 475 | out_unlock: |
239007b8 | 476 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 477 | } |
14819ea1 | 478 | EXPORT_SYMBOL_GPL(handle_level_irq); |
dd87eb3a TG |
479 | |
480 | /** | |
47c2a3aa | 481 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
482 | * @irq: the interrupt number |
483 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 484 | * |
47c2a3aa | 485 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
486 | * call when the interrupt has been serviced. This enables support |
487 | * for modern forms of interrupt handlers, which handle the flow | |
488 | * details in hardware, transparently. | |
489 | */ | |
7ad5b3a5 | 490 | void |
7d12e780 | 491 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 492 | { |
239007b8 | 493 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
494 | |
495 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
fe200ae4 TG |
496 | if (!irq_check_poll(desc)) |
497 | goto out; | |
dd87eb3a TG |
498 | |
499 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
d6c88a50 | 500 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
501 | |
502 | /* | |
503 | * If its disabled or no action available | |
76d21601 | 504 | * then mask it and get out of here: |
dd87eb3a | 505 | */ |
a7ae4de5 | 506 | if (unlikely(!desc->action || (desc->status & IRQ_DISABLED))) { |
98bb244b | 507 | desc->status |= IRQ_PENDING; |
e2c0f8ff | 508 | mask_irq(desc); |
dd87eb3a | 509 | goto out; |
98bb244b | 510 | } |
a7ae4de5 | 511 | handle_irq_event(desc); |
dd87eb3a | 512 | out: |
0c5c1557 | 513 | desc->irq_data.chip->irq_eoi(&desc->irq_data); |
239007b8 | 514 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
515 | } |
516 | ||
517 | /** | |
518 | * handle_edge_irq - edge type IRQ handler | |
519 | * @irq: the interrupt number | |
520 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
521 | * |
522 | * Interrupt occures on the falling and/or rising edge of a hardware | |
523 | * signal. The occurence is latched into the irq controller hardware | |
524 | * and must be acked in order to be reenabled. After the ack another | |
525 | * interrupt can happen on the same source even before the first one | |
dfff0615 | 526 | * is handled by the associated event handler. If this happens it |
dd87eb3a TG |
527 | * might be necessary to disable (mask) the interrupt depending on the |
528 | * controller hardware. This requires to reenable the interrupt inside | |
529 | * of the loop which handles the interrupts which have arrived while | |
530 | * the handler was running. If all pending interrupts are handled, the | |
531 | * loop is left. | |
532 | */ | |
7ad5b3a5 | 533 | void |
7d12e780 | 534 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 535 | { |
239007b8 | 536 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
537 | |
538 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
539 | ||
540 | /* | |
541 | * If we're currently running this IRQ, or its disabled, | |
542 | * we shouldn't process the IRQ. Mark it pending, handle | |
543 | * the necessary masking and go out | |
544 | */ | |
545 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || | |
546 | !desc->action)) { | |
fe200ae4 | 547 | if (!irq_check_poll(desc)) { |
d78f8dd3 | 548 | desc->status |= IRQ_PENDING; |
fe200ae4 TG |
549 | mask_ack_irq(desc); |
550 | goto out_unlock; | |
551 | } | |
dd87eb3a | 552 | } |
d6c88a50 | 553 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
554 | |
555 | /* Start handling the irq */ | |
22a49163 | 556 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
dd87eb3a | 557 | |
dd87eb3a | 558 | do { |
a60a5dc2 | 559 | if (unlikely(!desc->action)) { |
e2c0f8ff | 560 | mask_irq(desc); |
dd87eb3a TG |
561 | goto out_unlock; |
562 | } | |
563 | ||
564 | /* | |
565 | * When another irq arrived while we were handling | |
566 | * one, we could have masked the irq. | |
567 | * Renable it, if it was not disabled in meantime. | |
568 | */ | |
569 | if (unlikely((desc->status & | |
570 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == | |
571 | (IRQ_PENDING | IRQ_MASKED))) { | |
0eda58b7 | 572 | unmask_irq(desc); |
dd87eb3a TG |
573 | } |
574 | ||
a60a5dc2 | 575 | handle_irq_event(desc); |
dd87eb3a TG |
576 | |
577 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); | |
578 | ||
dd87eb3a | 579 | out_unlock: |
239007b8 | 580 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
581 | } |
582 | ||
dd87eb3a | 583 | /** |
24b26d42 | 584 | * handle_percpu_irq - Per CPU local irq handler |
dd87eb3a TG |
585 | * @irq: the interrupt number |
586 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
587 | * |
588 | * Per CPU interrupts on SMP machines without locking requirements | |
589 | */ | |
7ad5b3a5 | 590 | void |
7d12e780 | 591 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 592 | { |
35e857cb | 593 | struct irq_chip *chip = irq_desc_get_chip(desc); |
dd87eb3a | 594 | |
d6c88a50 | 595 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a | 596 | |
849f061c TG |
597 | if (chip->irq_ack) |
598 | chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 599 | |
849f061c | 600 | handle_irq_event_percpu(desc, desc->action); |
dd87eb3a | 601 | |
849f061c TG |
602 | if (chip->irq_eoi) |
603 | chip->irq_eoi(&desc->irq_data); | |
dd87eb3a TG |
604 | } |
605 | ||
dd87eb3a | 606 | void |
a460e745 IM |
607 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
608 | const char *name) | |
dd87eb3a | 609 | { |
d3c60047 | 610 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
611 | unsigned long flags; |
612 | ||
7d94f7ca | 613 | if (!desc) { |
dd87eb3a TG |
614 | printk(KERN_ERR |
615 | "Trying to install type control for IRQ%d\n", irq); | |
616 | return; | |
617 | } | |
618 | ||
dd87eb3a TG |
619 | if (!handle) |
620 | handle = handle_bad_irq; | |
6b8ff312 | 621 | else if (desc->irq_data.chip == &no_irq_chip) { |
f8b5473f | 622 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
b039db8e | 623 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
f8b5473f TG |
624 | /* |
625 | * Some ARM implementations install a handler for really dumb | |
626 | * interrupt hardware without setting an irq_chip. This worked | |
627 | * with the ARM no_irq_chip but the check in setup_irq would | |
628 | * prevent us to setup the interrupt at all. Switch it to | |
629 | * dummy_irq_chip for easy transition. | |
630 | */ | |
6b8ff312 | 631 | desc->irq_data.chip = &dummy_irq_chip; |
f8b5473f | 632 | } |
dd87eb3a | 633 | |
3876ec9e | 634 | chip_bus_lock(desc); |
239007b8 | 635 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a TG |
636 | |
637 | /* Uninstall? */ | |
638 | if (handle == handle_bad_irq) { | |
6b8ff312 | 639 | if (desc->irq_data.chip != &no_irq_chip) |
9205e31d | 640 | mask_ack_irq(desc); |
dd87eb3a TG |
641 | desc->status |= IRQ_DISABLED; |
642 | desc->depth = 1; | |
643 | } | |
644 | desc->handle_irq = handle; | |
a460e745 | 645 | desc->name = name; |
dd87eb3a TG |
646 | |
647 | if (handle != handle_bad_irq && is_chained) { | |
dd87eb3a | 648 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; |
46999238 | 649 | irq_startup(desc); |
dd87eb3a | 650 | } |
239007b8 | 651 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3876ec9e | 652 | chip_bus_sync_unlock(desc); |
dd87eb3a | 653 | } |
14819ea1 | 654 | EXPORT_SYMBOL_GPL(__set_irq_handler); |
dd87eb3a TG |
655 | |
656 | void | |
657 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
57a58a94 | 658 | irq_flow_handler_t handle) |
dd87eb3a | 659 | { |
35e857cb | 660 | irq_set_chip(irq, chip); |
a460e745 | 661 | __set_irq_handler(irq, handle, 0, NULL); |
dd87eb3a TG |
662 | } |
663 | ||
a460e745 IM |
664 | void |
665 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | |
666 | irq_flow_handler_t handle, const char *name) | |
dd87eb3a | 667 | { |
35e857cb | 668 | irq_set_chip(irq, chip); |
a460e745 | 669 | __set_irq_handler(irq, handle, 0, name); |
dd87eb3a | 670 | } |
46f4f8f6 | 671 | |
44247184 | 672 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
46f4f8f6 | 673 | { |
d3c60047 | 674 | struct irq_desc *desc = irq_to_desc(irq); |
46f4f8f6 RB |
675 | unsigned long flags; |
676 | ||
44247184 | 677 | if (!desc) |
46f4f8f6 | 678 | return; |
46f4f8f6 | 679 | |
44247184 TG |
680 | /* Sanitize flags */ |
681 | set &= IRQF_MODIFY_MASK; | |
682 | clr &= IRQF_MODIFY_MASK; | |
46f4f8f6 | 683 | |
239007b8 | 684 | raw_spin_lock_irqsave(&desc->lock, flags); |
44247184 TG |
685 | desc->status &= ~clr; |
686 | desc->status |= set; | |
239007b8 | 687 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
46f4f8f6 | 688 | } |