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dd87eb3a
TG
1/*
2 * linux/kernel/irq/chip.c
3 *
4 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
5 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 *
7 * This file contains the core interrupt handling code, for irq-chip
8 * based architectures.
9 *
c0c6e085 10 * Detailed information is available in Documentation/core-api/genericirq.rst
dd87eb3a
TG
11 */
12
13#include <linux/irq.h>
7fe3730d 14#include <linux/msi.h>
dd87eb3a
TG
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/kernel_stat.h>
f8264e34 18#include <linux/irqdomain.h>
dd87eb3a 19
f069686e
SR
20#include <trace/events/irq.h>
21
dd87eb3a
TG
22#include "internals.h"
23
e509bd7d
MW
24static irqreturn_t bad_chained_irq(int irq, void *dev_id)
25{
26 WARN_ONCE(1, "Chained irq %d should not call an action\n", irq);
27 return IRQ_NONE;
28}
29
30/*
31 * Chained handlers should never call action on their IRQ. This default
32 * action will emit warning if such thing happens.
33 */
34struct irqaction chained_action = {
35 .handler = bad_chained_irq,
36};
37
dd87eb3a 38/**
a0cd9ca2 39 * irq_set_chip - set the irq chip for an irq
dd87eb3a
TG
40 * @irq: irq number
41 * @chip: pointer to irq chip description structure
42 */
a0cd9ca2 43int irq_set_chip(unsigned int irq, struct irq_chip *chip)
dd87eb3a 44{
dd87eb3a 45 unsigned long flags;
31d9d9b6 46 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 47
02725e74 48 if (!desc)
dd87eb3a 49 return -EINVAL;
dd87eb3a
TG
50
51 if (!chip)
52 chip = &no_irq_chip;
53
6b8ff312 54 desc->irq_data.chip = chip;
02725e74 55 irq_put_desc_unlock(desc, flags);
d72274e5
DD
56 /*
57 * For !CONFIG_SPARSE_IRQ make the irq show up in
f63b6a05 58 * allocated_irqs.
d72274e5 59 */
f63b6a05 60 irq_mark_irq(irq);
dd87eb3a
TG
61 return 0;
62}
a0cd9ca2 63EXPORT_SYMBOL(irq_set_chip);
dd87eb3a
TG
64
65/**
a0cd9ca2 66 * irq_set_type - set the irq trigger type for an irq
dd87eb3a 67 * @irq: irq number
0c5d1eb7 68 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
dd87eb3a 69 */
a0cd9ca2 70int irq_set_irq_type(unsigned int irq, unsigned int type)
dd87eb3a 71{
dd87eb3a 72 unsigned long flags;
31d9d9b6 73 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
02725e74 74 int ret = 0;
dd87eb3a 75
02725e74
TG
76 if (!desc)
77 return -EINVAL;
dd87eb3a 78
a1ff541a 79 ret = __irq_set_trigger(desc, type);
02725e74 80 irq_put_desc_busunlock(desc, flags);
dd87eb3a
TG
81 return ret;
82}
a0cd9ca2 83EXPORT_SYMBOL(irq_set_irq_type);
dd87eb3a
TG
84
85/**
a0cd9ca2 86 * irq_set_handler_data - set irq handler data for an irq
dd87eb3a
TG
87 * @irq: Interrupt number
88 * @data: Pointer to interrupt specific data
89 *
90 * Set the hardware irq controller data for an irq
91 */
a0cd9ca2 92int irq_set_handler_data(unsigned int irq, void *data)
dd87eb3a 93{
dd87eb3a 94 unsigned long flags;
31d9d9b6 95 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 96
02725e74 97 if (!desc)
dd87eb3a 98 return -EINVAL;
af7080e0 99 desc->irq_common_data.handler_data = data;
02725e74 100 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
101 return 0;
102}
a0cd9ca2 103EXPORT_SYMBOL(irq_set_handler_data);
dd87eb3a 104
5b912c10 105/**
51906e77
AG
106 * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset
107 * @irq_base: Interrupt number base
108 * @irq_offset: Interrupt number offset
109 * @entry: Pointer to MSI descriptor data
5b912c10 110 *
51906e77 111 * Set the MSI descriptor entry for an irq at offset
5b912c10 112 */
51906e77
AG
113int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
114 struct msi_desc *entry)
5b912c10 115{
5b912c10 116 unsigned long flags;
51906e77 117 struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
5b912c10 118
02725e74 119 if (!desc)
5b912c10 120 return -EINVAL;
b237721c 121 desc->irq_common_data.msi_desc = entry;
51906e77
AG
122 if (entry && !irq_offset)
123 entry->irq = irq_base;
02725e74 124 irq_put_desc_unlock(desc, flags);
5b912c10
EB
125 return 0;
126}
127
51906e77
AG
128/**
129 * irq_set_msi_desc - set MSI descriptor data for an irq
130 * @irq: Interrupt number
131 * @entry: Pointer to MSI descriptor data
132 *
133 * Set the MSI descriptor entry for an irq
134 */
135int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
136{
137 return irq_set_msi_desc_off(irq, 0, entry);
138}
139
dd87eb3a 140/**
a0cd9ca2 141 * irq_set_chip_data - set irq chip data for an irq
dd87eb3a
TG
142 * @irq: Interrupt number
143 * @data: Pointer to chip specific data
144 *
145 * Set the hardware irq chip data for an irq
146 */
a0cd9ca2 147int irq_set_chip_data(unsigned int irq, void *data)
dd87eb3a 148{
dd87eb3a 149 unsigned long flags;
31d9d9b6 150 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 151
02725e74 152 if (!desc)
dd87eb3a 153 return -EINVAL;
6b8ff312 154 desc->irq_data.chip_data = data;
02725e74 155 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
156 return 0;
157}
a0cd9ca2 158EXPORT_SYMBOL(irq_set_chip_data);
dd87eb3a 159
f303a6dd
TG
160struct irq_data *irq_get_irq_data(unsigned int irq)
161{
162 struct irq_desc *desc = irq_to_desc(irq);
163
164 return desc ? &desc->irq_data : NULL;
165}
166EXPORT_SYMBOL_GPL(irq_get_irq_data);
167
c1594b77
TG
168static void irq_state_clr_disabled(struct irq_desc *desc)
169{
801a0e9a 170 irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
171}
172
6e40262e
TG
173static void irq_state_clr_masked(struct irq_desc *desc)
174{
32f4125e 175 irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
176}
177
201d7f47
TG
178static void irq_state_clr_started(struct irq_desc *desc)
179{
180 irqd_clear(&desc->irq_data, IRQD_IRQ_STARTED);
181}
182
183static void irq_state_set_started(struct irq_desc *desc)
184{
185 irqd_set(&desc->irq_data, IRQD_IRQ_STARTED);
186}
187
761ea388
TG
188enum {
189 IRQ_STARTUP_NORMAL,
190 IRQ_STARTUP_MANAGED,
191 IRQ_STARTUP_ABORT,
192};
193
194#ifdef CONFIG_SMP
195static int
196__irq_startup_managed(struct irq_desc *desc, struct cpumask *aff, bool force)
197{
198 struct irq_data *d = irq_desc_get_irq_data(desc);
199
200 if (!irqd_affinity_is_managed(d))
201 return IRQ_STARTUP_NORMAL;
202
203 irqd_clr_managed_shutdown(d);
204
9cb067ef 205 if (cpumask_any_and(aff, cpu_online_mask) >= nr_cpu_ids) {
761ea388
TG
206 /*
207 * Catch code which fiddles with enable_irq() on a managed
208 * and potentially shutdown IRQ. Chained interrupt
209 * installment or irq auto probing should not happen on
c942cee4 210 * managed irqs either.
761ea388
TG
211 */
212 if (WARN_ON_ONCE(force))
c942cee4 213 return IRQ_STARTUP_ABORT;
761ea388
TG
214 /*
215 * The interrupt was requested, but there is no online CPU
216 * in it's affinity mask. Put it into managed shutdown
217 * state and let the cpu hotplug mechanism start it up once
218 * a CPU in the mask becomes available.
219 */
761ea388
TG
220 return IRQ_STARTUP_ABORT;
221 }
c942cee4 222 irq_domain_activate_irq(d);
761ea388
TG
223 return IRQ_STARTUP_MANAGED;
224}
225#else
2372a519 226static __always_inline int
761ea388
TG
227__irq_startup_managed(struct irq_desc *desc, struct cpumask *aff, bool force)
228{
229 return IRQ_STARTUP_NORMAL;
230}
231#endif
232
708d174b
TG
233static int __irq_startup(struct irq_desc *desc)
234{
235 struct irq_data *d = irq_desc_get_irq_data(desc);
236 int ret = 0;
237
c942cee4
TG
238 /* Warn if this interrupt is not activated but try nevertheless */
239 WARN_ON_ONCE(!irqd_is_activated(d));
240
708d174b
TG
241 if (d->chip->irq_startup) {
242 ret = d->chip->irq_startup(d);
243 irq_state_clr_disabled(desc);
244 irq_state_clr_masked(desc);
245 } else {
246 irq_enable(desc);
247 }
248 irq_state_set_started(desc);
249 return ret;
250}
251
4cde9c6b 252int irq_startup(struct irq_desc *desc, bool resend, bool force)
46999238 253{
761ea388
TG
254 struct irq_data *d = irq_desc_get_irq_data(desc);
255 struct cpumask *aff = irq_data_get_affinity_mask(d);
b4bc724e
TG
256 int ret = 0;
257
46999238
TG
258 desc->depth = 0;
259
761ea388 260 if (irqd_is_started(d)) {
b4bc724e 261 irq_enable(desc);
201d7f47 262 } else {
761ea388
TG
263 switch (__irq_startup_managed(desc, aff, force)) {
264 case IRQ_STARTUP_NORMAL:
265 ret = __irq_startup(desc);
266 irq_setup_affinity(desc);
267 break;
268 case IRQ_STARTUP_MANAGED:
269 ret = __irq_startup(desc);
270 irq_set_affinity_locked(d, aff, false);
271 break;
272 case IRQ_STARTUP_ABORT:
c942cee4 273 irqd_set_managed_shutdown(d);
761ea388
TG
274 return 0;
275 }
3aae994f 276 }
b4bc724e 277 if (resend)
0798abeb 278 check_irq_resend(desc);
201d7f47 279
b4bc724e 280 return ret;
46999238
TG
281}
282
c942cee4
TG
283int irq_activate(struct irq_desc *desc)
284{
285 struct irq_data *d = irq_desc_get_irq_data(desc);
286
287 if (!irqd_affinity_is_managed(d))
288 irq_domain_activate_irq(d);
289 return 0;
290}
291
292void irq_activate_and_startup(struct irq_desc *desc, bool resend)
293{
294 if (WARN_ON(irq_activate(desc)))
295 return;
296 irq_startup(desc, resend, IRQ_START_FORCE);
297}
298
201d7f47
TG
299static void __irq_disable(struct irq_desc *desc, bool mask);
300
46999238
TG
301void irq_shutdown(struct irq_desc *desc)
302{
201d7f47
TG
303 if (irqd_is_started(&desc->irq_data)) {
304 desc->depth = 1;
305 if (desc->irq_data.chip->irq_shutdown) {
306 desc->irq_data.chip->irq_shutdown(&desc->irq_data);
307 irq_state_set_disabled(desc);
308 irq_state_set_masked(desc);
309 } else {
310 __irq_disable(desc, true);
311 }
312 irq_state_clr_started(desc);
313 }
314 /*
315 * This must be called even if the interrupt was never started up,
316 * because the activation can happen before the interrupt is
317 * available for request/startup. It has it's own state tracking so
318 * it's safe to call it unconditionally.
319 */
f8264e34 320 irq_domain_deactivate_irq(&desc->irq_data);
46999238
TG
321}
322
87923470
TG
323void irq_enable(struct irq_desc *desc)
324{
bf22ff45
JC
325 if (!irqd_irq_disabled(&desc->irq_data)) {
326 unmask_irq(desc);
327 } else {
328 irq_state_clr_disabled(desc);
329 if (desc->irq_data.chip->irq_enable) {
330 desc->irq_data.chip->irq_enable(&desc->irq_data);
331 irq_state_clr_masked(desc);
332 } else {
333 unmask_irq(desc);
334 }
335 }
dd87eb3a
TG
336}
337
201d7f47
TG
338static void __irq_disable(struct irq_desc *desc, bool mask)
339{
bf22ff45
JC
340 if (irqd_irq_disabled(&desc->irq_data)) {
341 if (mask)
342 mask_irq(desc);
343 } else {
344 irq_state_set_disabled(desc);
345 if (desc->irq_data.chip->irq_disable) {
346 desc->irq_data.chip->irq_disable(&desc->irq_data);
347 irq_state_set_masked(desc);
348 } else if (mask) {
349 mask_irq(desc);
350 }
201d7f47
TG
351 }
352}
353
d671a605 354/**
f788e7bf 355 * irq_disable - Mark interrupt disabled
d671a605
AF
356 * @desc: irq descriptor which should be disabled
357 *
358 * If the chip does not implement the irq_disable callback, we
359 * use a lazy disable approach. That means we mark the interrupt
360 * disabled, but leave the hardware unmasked. That's an
361 * optimization because we avoid the hardware access for the
362 * common case where no interrupt happens after we marked it
363 * disabled. If an interrupt happens, then the interrupt flow
364 * handler masks the line at the hardware level and marks it
365 * pending.
e9849777
TG
366 *
367 * If the interrupt chip does not implement the irq_disable callback,
368 * a driver can disable the lazy approach for a particular irq line by
369 * calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can
370 * be used for devices which cannot disable the interrupt at the
371 * device level under certain circumstances and have to use
372 * disable_irq[_nosync] instead.
d671a605 373 */
50f7c032 374void irq_disable(struct irq_desc *desc)
89d694b9 375{
201d7f47 376 __irq_disable(desc, irq_settings_disable_unlazy(desc));
89d694b9
TG
377}
378
31d9d9b6
MZ
379void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu)
380{
381 if (desc->irq_data.chip->irq_enable)
382 desc->irq_data.chip->irq_enable(&desc->irq_data);
383 else
384 desc->irq_data.chip->irq_unmask(&desc->irq_data);
385 cpumask_set_cpu(cpu, desc->percpu_enabled);
386}
387
388void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu)
389{
390 if (desc->irq_data.chip->irq_disable)
391 desc->irq_data.chip->irq_disable(&desc->irq_data);
392 else
393 desc->irq_data.chip->irq_mask(&desc->irq_data);
394 cpumask_clear_cpu(cpu, desc->percpu_enabled);
395}
396
9205e31d 397static inline void mask_ack_irq(struct irq_desc *desc)
dd87eb3a 398{
bf22ff45 399 if (desc->irq_data.chip->irq_mask_ack) {
9205e31d 400 desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
bf22ff45
JC
401 irq_state_set_masked(desc);
402 } else {
403 mask_irq(desc);
22a49163
TG
404 if (desc->irq_data.chip->irq_ack)
405 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 406 }
0b1adaa0
TG
407}
408
d4d5e089 409void mask_irq(struct irq_desc *desc)
0b1adaa0 410{
bf22ff45
JC
411 if (irqd_irq_masked(&desc->irq_data))
412 return;
413
e2c0f8ff
TG
414 if (desc->irq_data.chip->irq_mask) {
415 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 416 irq_state_set_masked(desc);
0b1adaa0
TG
417 }
418}
419
d4d5e089 420void unmask_irq(struct irq_desc *desc)
0b1adaa0 421{
bf22ff45
JC
422 if (!irqd_irq_masked(&desc->irq_data))
423 return;
424
0eda58b7
TG
425 if (desc->irq_data.chip->irq_unmask) {
426 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 427 irq_state_clr_masked(desc);
0b1adaa0 428 }
dd87eb3a
TG
429}
430
328a4978
TG
431void unmask_threaded_irq(struct irq_desc *desc)
432{
433 struct irq_chip *chip = desc->irq_data.chip;
434
435 if (chip->flags & IRQCHIP_EOI_THREADED)
436 chip->irq_eoi(&desc->irq_data);
437
bf22ff45 438 unmask_irq(desc);
328a4978
TG
439}
440
399b5da2
TG
441/*
442 * handle_nested_irq - Handle a nested irq from a irq thread
443 * @irq: the interrupt number
444 *
445 * Handle interrupts which are nested into a threaded interrupt
446 * handler. The handler function is called inside the calling
447 * threads context.
448 */
449void handle_nested_irq(unsigned int irq)
450{
451 struct irq_desc *desc = irq_to_desc(irq);
452 struct irqaction *action;
453 irqreturn_t action_ret;
454
455 might_sleep();
456
239007b8 457 raw_spin_lock_irq(&desc->lock);
399b5da2 458
293a7a0a 459 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
399b5da2
TG
460
461 action = desc->action;
23812b9d
NJ
462 if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) {
463 desc->istate |= IRQS_PENDING;
399b5da2 464 goto out_unlock;
23812b9d 465 }
399b5da2 466
a946e8c7 467 kstat_incr_irqs_this_cpu(desc);
32f4125e 468 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
239007b8 469 raw_spin_unlock_irq(&desc->lock);
399b5da2 470
45e52022
CK
471 action_ret = IRQ_NONE;
472 for_each_action_of_desc(desc, action)
473 action_ret |= action->thread_fn(action->irq, action->dev_id);
474
399b5da2 475 if (!noirqdebug)
0dcdbc97 476 note_interrupt(desc, action_ret);
399b5da2 477
239007b8 478 raw_spin_lock_irq(&desc->lock);
32f4125e 479 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
399b5da2
TG
480
481out_unlock:
239007b8 482 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
483}
484EXPORT_SYMBOL_GPL(handle_nested_irq);
485
fe200ae4
TG
486static bool irq_check_poll(struct irq_desc *desc)
487{
6954b75b 488 if (!(desc->istate & IRQS_POLL_INPROGRESS))
fe200ae4
TG
489 return false;
490 return irq_wait_for_poll(desc);
491}
492
c7bd3ec0
TG
493static bool irq_may_run(struct irq_desc *desc)
494{
9ce7a258
TG
495 unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED;
496
497 /*
498 * If the interrupt is not in progress and is not an armed
499 * wakeup interrupt, proceed.
500 */
501 if (!irqd_has_set(&desc->irq_data, mask))
c7bd3ec0 502 return true;
9ce7a258
TG
503
504 /*
505 * If the interrupt is an armed wakeup source, mark it pending
506 * and suspended, disable it and notify the pm core about the
507 * event.
508 */
509 if (irq_pm_check_wakeup(desc))
510 return false;
511
512 /*
513 * Handle a potential concurrent poll on a different core.
514 */
c7bd3ec0
TG
515 return irq_check_poll(desc);
516}
517
dd87eb3a
TG
518/**
519 * handle_simple_irq - Simple and software-decoded IRQs.
dd87eb3a 520 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
521 *
522 * Simple interrupts are either sent from a demultiplexing interrupt
523 * handler or come from hardware, where no interrupt hardware control
524 * is necessary.
525 *
526 * Note: The caller is expected to handle the ack, clear, mask and
527 * unmask issues if necessary.
528 */
bd0b9ac4 529void handle_simple_irq(struct irq_desc *desc)
dd87eb3a 530{
239007b8 531 raw_spin_lock(&desc->lock);
dd87eb3a 532
c7bd3ec0
TG
533 if (!irq_may_run(desc))
534 goto out_unlock;
fe200ae4 535
163ef309 536 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a 537
23812b9d
NJ
538 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
539 desc->istate |= IRQS_PENDING;
dd87eb3a 540 goto out_unlock;
23812b9d 541 }
dd87eb3a 542
a946e8c7 543 kstat_incr_irqs_this_cpu(desc);
107781e7 544 handle_irq_event(desc);
dd87eb3a 545
dd87eb3a 546out_unlock:
239007b8 547 raw_spin_unlock(&desc->lock);
dd87eb3a 548}
edf76f83 549EXPORT_SYMBOL_GPL(handle_simple_irq);
dd87eb3a 550
edd14cfe
KB
551/**
552 * handle_untracked_irq - Simple and software-decoded IRQs.
553 * @desc: the interrupt description structure for this irq
554 *
555 * Untracked interrupts are sent from a demultiplexing interrupt
556 * handler when the demultiplexer does not know which device it its
557 * multiplexed irq domain generated the interrupt. IRQ's handled
558 * through here are not subjected to stats tracking, randomness, or
559 * spurious interrupt detection.
560 *
561 * Note: Like handle_simple_irq, the caller is expected to handle
562 * the ack, clear, mask and unmask issues if necessary.
563 */
564void handle_untracked_irq(struct irq_desc *desc)
565{
566 unsigned int flags = 0;
567
568 raw_spin_lock(&desc->lock);
569
570 if (!irq_may_run(desc))
571 goto out_unlock;
572
573 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
574
575 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
576 desc->istate |= IRQS_PENDING;
577 goto out_unlock;
578 }
579
580 desc->istate &= ~IRQS_PENDING;
581 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
582 raw_spin_unlock(&desc->lock);
583
584 __handle_irq_event_percpu(desc, &flags);
585
586 raw_spin_lock(&desc->lock);
587 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
588
589out_unlock:
590 raw_spin_unlock(&desc->lock);
591}
592EXPORT_SYMBOL_GPL(handle_untracked_irq);
593
ac563761
TG
594/*
595 * Called unconditionally from handle_level_irq() and only for oneshot
596 * interrupts from handle_fasteoi_irq()
597 */
598static void cond_unmask_irq(struct irq_desc *desc)
599{
600 /*
601 * We need to unmask in the following cases:
602 * - Standard level irq (IRQF_ONESHOT is not set)
603 * - Oneshot irq which did not wake the thread (caused by a
604 * spurious interrupt or a primary handler handling it
605 * completely).
606 */
607 if (!irqd_irq_disabled(&desc->irq_data) &&
608 irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot)
609 unmask_irq(desc);
610}
611
dd87eb3a
TG
612/**
613 * handle_level_irq - Level type irq handler
dd87eb3a 614 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
615 *
616 * Level type interrupts are active as long as the hardware line has
617 * the active level. This may require to mask the interrupt and unmask
618 * it after the associated handler has acknowledged the device, so the
619 * interrupt line is back to inactive.
620 */
bd0b9ac4 621void handle_level_irq(struct irq_desc *desc)
dd87eb3a 622{
239007b8 623 raw_spin_lock(&desc->lock);
9205e31d 624 mask_ack_irq(desc);
dd87eb3a 625
c7bd3ec0
TG
626 if (!irq_may_run(desc))
627 goto out_unlock;
fe200ae4 628
163ef309 629 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
630
631 /*
632 * If its disabled or no action available
633 * keep it masked and get out of here
634 */
d4dc0f90
TG
635 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
636 desc->istate |= IRQS_PENDING;
86998aa6 637 goto out_unlock;
d4dc0f90 638 }
dd87eb3a 639
a946e8c7 640 kstat_incr_irqs_this_cpu(desc);
1529866c 641 handle_irq_event(desc);
b25c340c 642
ac563761
TG
643 cond_unmask_irq(desc);
644
86998aa6 645out_unlock:
239007b8 646 raw_spin_unlock(&desc->lock);
dd87eb3a 647}
14819ea1 648EXPORT_SYMBOL_GPL(handle_level_irq);
dd87eb3a 649
78129576
TG
650#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
651static inline void preflow_handler(struct irq_desc *desc)
652{
653 if (desc->preflow_handler)
654 desc->preflow_handler(&desc->irq_data);
655}
656#else
657static inline void preflow_handler(struct irq_desc *desc) { }
658#endif
659
328a4978
TG
660static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
661{
662 if (!(desc->istate & IRQS_ONESHOT)) {
663 chip->irq_eoi(&desc->irq_data);
664 return;
665 }
666 /*
667 * We need to unmask in the following cases:
668 * - Oneshot irq which did not wake the thread (caused by a
669 * spurious interrupt or a primary handler handling it
670 * completely).
671 */
672 if (!irqd_irq_disabled(&desc->irq_data) &&
673 irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) {
674 chip->irq_eoi(&desc->irq_data);
675 unmask_irq(desc);
676 } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) {
677 chip->irq_eoi(&desc->irq_data);
678 }
679}
680
dd87eb3a 681/**
47c2a3aa 682 * handle_fasteoi_irq - irq handler for transparent controllers
dd87eb3a 683 * @desc: the interrupt description structure for this irq
dd87eb3a 684 *
47c2a3aa 685 * Only a single callback will be issued to the chip: an ->eoi()
dd87eb3a
TG
686 * call when the interrupt has been serviced. This enables support
687 * for modern forms of interrupt handlers, which handle the flow
688 * details in hardware, transparently.
689 */
bd0b9ac4 690void handle_fasteoi_irq(struct irq_desc *desc)
dd87eb3a 691{
328a4978
TG
692 struct irq_chip *chip = desc->irq_data.chip;
693
239007b8 694 raw_spin_lock(&desc->lock);
dd87eb3a 695
c7bd3ec0
TG
696 if (!irq_may_run(desc))
697 goto out;
dd87eb3a 698
163ef309 699 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
700
701 /*
702 * If its disabled or no action available
76d21601 703 * then mask it and get out of here:
dd87eb3a 704 */
32f4125e 705 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
2a0d6fb3 706 desc->istate |= IRQS_PENDING;
e2c0f8ff 707 mask_irq(desc);
dd87eb3a 708 goto out;
98bb244b 709 }
c69e3758 710
a946e8c7 711 kstat_incr_irqs_this_cpu(desc);
c69e3758
TG
712 if (desc->istate & IRQS_ONESHOT)
713 mask_irq(desc);
714
78129576 715 preflow_handler(desc);
a7ae4de5 716 handle_irq_event(desc);
77694b40 717
328a4978 718 cond_unmask_eoi_irq(desc, chip);
ac563761 719
239007b8 720 raw_spin_unlock(&desc->lock);
77694b40
TG
721 return;
722out:
328a4978
TG
723 if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
724 chip->irq_eoi(&desc->irq_data);
725 raw_spin_unlock(&desc->lock);
dd87eb3a 726}
7cad45ee 727EXPORT_SYMBOL_GPL(handle_fasteoi_irq);
dd87eb3a
TG
728
729/**
730 * handle_edge_irq - edge type IRQ handler
dd87eb3a 731 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
732 *
733 * Interrupt occures on the falling and/or rising edge of a hardware
25985edc 734 * signal. The occurrence is latched into the irq controller hardware
dd87eb3a
TG
735 * and must be acked in order to be reenabled. After the ack another
736 * interrupt can happen on the same source even before the first one
dfff0615 737 * is handled by the associated event handler. If this happens it
dd87eb3a
TG
738 * might be necessary to disable (mask) the interrupt depending on the
739 * controller hardware. This requires to reenable the interrupt inside
740 * of the loop which handles the interrupts which have arrived while
741 * the handler was running. If all pending interrupts are handled, the
742 * loop is left.
743 */
bd0b9ac4 744void handle_edge_irq(struct irq_desc *desc)
dd87eb3a 745{
239007b8 746 raw_spin_lock(&desc->lock);
dd87eb3a 747
163ef309 748 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
c3d7acd0 749
c7bd3ec0
TG
750 if (!irq_may_run(desc)) {
751 desc->istate |= IRQS_PENDING;
752 mask_ack_irq(desc);
753 goto out_unlock;
dd87eb3a 754 }
c3d7acd0 755
dd87eb3a 756 /*
c3d7acd0
TG
757 * If its disabled or no action available then mask it and get
758 * out of here.
dd87eb3a 759 */
c3d7acd0
TG
760 if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
761 desc->istate |= IRQS_PENDING;
762 mask_ack_irq(desc);
763 goto out_unlock;
dd87eb3a 764 }
c3d7acd0 765
b51bf95c 766 kstat_incr_irqs_this_cpu(desc);
dd87eb3a
TG
767
768 /* Start handling the irq */
22a49163 769 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 770
dd87eb3a 771 do {
a60a5dc2 772 if (unlikely(!desc->action)) {
e2c0f8ff 773 mask_irq(desc);
dd87eb3a
TG
774 goto out_unlock;
775 }
776
777 /*
778 * When another irq arrived while we were handling
779 * one, we could have masked the irq.
780 * Renable it, if it was not disabled in meantime.
781 */
2a0d6fb3 782 if (unlikely(desc->istate & IRQS_PENDING)) {
32f4125e
TG
783 if (!irqd_irq_disabled(&desc->irq_data) &&
784 irqd_irq_masked(&desc->irq_data))
c1594b77 785 unmask_irq(desc);
dd87eb3a
TG
786 }
787
a60a5dc2 788 handle_irq_event(desc);
dd87eb3a 789
2a0d6fb3 790 } while ((desc->istate & IRQS_PENDING) &&
32f4125e 791 !irqd_irq_disabled(&desc->irq_data));
dd87eb3a 792
dd87eb3a 793out_unlock:
239007b8 794 raw_spin_unlock(&desc->lock);
dd87eb3a 795}
3911ff30 796EXPORT_SYMBOL(handle_edge_irq);
dd87eb3a 797
0521c8fb
TG
798#ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
799/**
800 * handle_edge_eoi_irq - edge eoi type IRQ handler
0521c8fb
TG
801 * @desc: the interrupt description structure for this irq
802 *
803 * Similar as the above handle_edge_irq, but using eoi and w/o the
804 * mask/unmask logic.
805 */
bd0b9ac4 806void handle_edge_eoi_irq(struct irq_desc *desc)
0521c8fb
TG
807{
808 struct irq_chip *chip = irq_desc_get_chip(desc);
809
810 raw_spin_lock(&desc->lock);
811
812 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
c3d7acd0 813
c7bd3ec0
TG
814 if (!irq_may_run(desc)) {
815 desc->istate |= IRQS_PENDING;
816 goto out_eoi;
0521c8fb 817 }
c3d7acd0 818
0521c8fb 819 /*
c3d7acd0
TG
820 * If its disabled or no action available then mask it and get
821 * out of here.
0521c8fb 822 */
c3d7acd0
TG
823 if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
824 desc->istate |= IRQS_PENDING;
825 goto out_eoi;
0521c8fb 826 }
c3d7acd0 827
b51bf95c 828 kstat_incr_irqs_this_cpu(desc);
0521c8fb
TG
829
830 do {
831 if (unlikely(!desc->action))
832 goto out_eoi;
833
834 handle_irq_event(desc);
835
836 } while ((desc->istate & IRQS_PENDING) &&
837 !irqd_irq_disabled(&desc->irq_data));
838
ac0e0447 839out_eoi:
0521c8fb
TG
840 chip->irq_eoi(&desc->irq_data);
841 raw_spin_unlock(&desc->lock);
842}
843#endif
844
dd87eb3a 845/**
24b26d42 846 * handle_percpu_irq - Per CPU local irq handler
dd87eb3a 847 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
848 *
849 * Per CPU interrupts on SMP machines without locking requirements
850 */
bd0b9ac4 851void handle_percpu_irq(struct irq_desc *desc)
dd87eb3a 852{
35e857cb 853 struct irq_chip *chip = irq_desc_get_chip(desc);
dd87eb3a 854
b51bf95c 855 kstat_incr_irqs_this_cpu(desc);
dd87eb3a 856
849f061c
TG
857 if (chip->irq_ack)
858 chip->irq_ack(&desc->irq_data);
dd87eb3a 859
71f64340 860 handle_irq_event_percpu(desc);
dd87eb3a 861
849f061c
TG
862 if (chip->irq_eoi)
863 chip->irq_eoi(&desc->irq_data);
dd87eb3a
TG
864}
865
31d9d9b6
MZ
866/**
867 * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
31d9d9b6
MZ
868 * @desc: the interrupt description structure for this irq
869 *
870 * Per CPU interrupts on SMP machines without locking requirements. Same as
871 * handle_percpu_irq() above but with the following extras:
872 *
873 * action->percpu_dev_id is a pointer to percpu variables which
874 * contain the real device id for the cpu on which this handler is
875 * called
876 */
bd0b9ac4 877void handle_percpu_devid_irq(struct irq_desc *desc)
31d9d9b6
MZ
878{
879 struct irq_chip *chip = irq_desc_get_chip(desc);
880 struct irqaction *action = desc->action;
bd0b9ac4 881 unsigned int irq = irq_desc_get_irq(desc);
31d9d9b6
MZ
882 irqreturn_t res;
883
b51bf95c 884 kstat_incr_irqs_this_cpu(desc);
31d9d9b6
MZ
885
886 if (chip->irq_ack)
887 chip->irq_ack(&desc->irq_data);
888
fc590c22
TG
889 if (likely(action)) {
890 trace_irq_handler_entry(irq, action);
891 res = action->handler(irq, raw_cpu_ptr(action->percpu_dev_id));
892 trace_irq_handler_exit(irq, action, res);
893 } else {
894 unsigned int cpu = smp_processor_id();
895 bool enabled = cpumask_test_cpu(cpu, desc->percpu_enabled);
896
897 if (enabled)
898 irq_percpu_disable(desc, cpu);
899
900 pr_err_once("Spurious%s percpu IRQ%u on CPU%u\n",
901 enabled ? " and unmasked" : "", irq, cpu);
902 }
31d9d9b6
MZ
903
904 if (chip->irq_eoi)
905 chip->irq_eoi(&desc->irq_data);
906}
907
b8129a1f 908static void
3b0f95be
RK
909__irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle,
910 int is_chained, const char *name)
dd87eb3a 911{
091738a2 912 if (!handle) {
dd87eb3a 913 handle = handle_bad_irq;
091738a2 914 } else {
f86eff22
MZ
915 struct irq_data *irq_data = &desc->irq_data;
916#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
917 /*
918 * With hierarchical domains we might run into a
919 * situation where the outermost chip is not yet set
920 * up, but the inner chips are there. Instead of
921 * bailing we install the handler, but obviously we
922 * cannot enable/startup the interrupt at this point.
923 */
924 while (irq_data) {
925 if (irq_data->chip != &no_irq_chip)
926 break;
927 /*
928 * Bail out if the outer chip is not set up
929 * and the interrrupt supposed to be started
930 * right away.
931 */
932 if (WARN_ON(is_chained))
3b0f95be 933 return;
f86eff22
MZ
934 /* Try the parent */
935 irq_data = irq_data->parent_data;
936 }
937#endif
938 if (WARN_ON(!irq_data || irq_data->chip == &no_irq_chip))
3b0f95be 939 return;
f8b5473f 940 }
dd87eb3a 941
dd87eb3a
TG
942 /* Uninstall? */
943 if (handle == handle_bad_irq) {
6b8ff312 944 if (desc->irq_data.chip != &no_irq_chip)
9205e31d 945 mask_ack_irq(desc);
801a0e9a 946 irq_state_set_disabled(desc);
e509bd7d
MW
947 if (is_chained)
948 desc->action = NULL;
dd87eb3a
TG
949 desc->depth = 1;
950 }
951 desc->handle_irq = handle;
a460e745 952 desc->name = name;
dd87eb3a
TG
953
954 if (handle != handle_bad_irq && is_chained) {
1984e075
MZ
955 unsigned int type = irqd_get_trigger_type(&desc->irq_data);
956
1e12c4a9
MZ
957 /*
958 * We're about to start this interrupt immediately,
959 * hence the need to set the trigger configuration.
960 * But the .set_type callback may have overridden the
961 * flow handler, ignoring that we're dealing with a
962 * chained interrupt. Reset it immediately because we
963 * do know better.
964 */
1984e075
MZ
965 if (type != IRQ_TYPE_NONE) {
966 __irq_set_trigger(desc, type);
967 desc->handle_irq = handle;
968 }
1e12c4a9 969
1ccb4e61
TG
970 irq_settings_set_noprobe(desc);
971 irq_settings_set_norequest(desc);
7f1b1244 972 irq_settings_set_nothread(desc);
e509bd7d 973 desc->action = &chained_action;
c942cee4 974 irq_activate_and_startup(desc, IRQ_RESEND);
dd87eb3a 975 }
3b0f95be
RK
976}
977
978void
979__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
980 const char *name)
981{
982 unsigned long flags;
983 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
984
985 if (!desc)
986 return;
987
988 __irq_do_set_handler(desc, handle, is_chained, name);
02725e74 989 irq_put_desc_busunlock(desc, flags);
dd87eb3a 990}
3836ca08 991EXPORT_SYMBOL_GPL(__irq_set_handler);
dd87eb3a 992
3b0f95be
RK
993void
994irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
995 void *data)
996{
997 unsigned long flags;
998 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
999
1000 if (!desc)
1001 return;
1002
af7080e0 1003 desc->irq_common_data.handler_data = data;
2c4569ca 1004 __irq_do_set_handler(desc, handle, 1, NULL);
3b0f95be
RK
1005
1006 irq_put_desc_busunlock(desc, flags);
1007}
1008EXPORT_SYMBOL_GPL(irq_set_chained_handler_and_data);
1009
dd87eb3a 1010void
3836ca08 1011irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
a460e745 1012 irq_flow_handler_t handle, const char *name)
dd87eb3a 1013{
35e857cb 1014 irq_set_chip(irq, chip);
3836ca08 1015 __irq_set_handler(irq, handle, 0, name);
dd87eb3a 1016}
b3ae66f2 1017EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name);
46f4f8f6 1018
44247184 1019void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
46f4f8f6 1020{
e8f24189 1021 unsigned long flags, trigger, tmp;
31d9d9b6 1022 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
46f4f8f6 1023
44247184 1024 if (!desc)
46f4f8f6 1025 return;
04c848d3
TG
1026
1027 /*
1028 * Warn when a driver sets the no autoenable flag on an already
1029 * active interrupt.
1030 */
1031 WARN_ON_ONCE(!desc->depth && (set & _IRQ_NOAUTOEN));
1032
a005677b
TG
1033 irq_settings_clr_and_set(desc, clr, set);
1034
e8f24189
MZ
1035 trigger = irqd_get_trigger_type(&desc->irq_data);
1036
876dbd4c 1037 irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
e1ef8241 1038 IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
a005677b
TG
1039 if (irq_settings_has_no_balance_set(desc))
1040 irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
1041 if (irq_settings_is_per_cpu(desc))
1042 irqd_set(&desc->irq_data, IRQD_PER_CPU);
e1ef8241
TG
1043 if (irq_settings_can_move_pcntxt(desc))
1044 irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
0ef5ca1e
TG
1045 if (irq_settings_is_level(desc))
1046 irqd_set(&desc->irq_data, IRQD_LEVEL);
a005677b 1047
e8f24189
MZ
1048 tmp = irq_settings_get_trigger_mask(desc);
1049 if (tmp != IRQ_TYPE_NONE)
1050 trigger = tmp;
1051
1052 irqd_set(&desc->irq_data, trigger);
876dbd4c 1053
02725e74 1054 irq_put_desc_unlock(desc, flags);
46f4f8f6 1055}
edf76f83 1056EXPORT_SYMBOL_GPL(irq_modify_status);
0fdb4b25
DD
1057
1058/**
1059 * irq_cpu_online - Invoke all irq_cpu_online functions.
1060 *
1061 * Iterate through all irqs and invoke the chip.irq_cpu_online()
1062 * for each.
1063 */
1064void irq_cpu_online(void)
1065{
1066 struct irq_desc *desc;
1067 struct irq_chip *chip;
1068 unsigned long flags;
1069 unsigned int irq;
1070
1071 for_each_active_irq(irq) {
1072 desc = irq_to_desc(irq);
1073 if (!desc)
1074 continue;
1075
1076 raw_spin_lock_irqsave(&desc->lock, flags);
1077
1078 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
1079 if (chip && chip->irq_cpu_online &&
1080 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 1081 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
1082 chip->irq_cpu_online(&desc->irq_data);
1083
1084 raw_spin_unlock_irqrestore(&desc->lock, flags);
1085 }
1086}
1087
1088/**
1089 * irq_cpu_offline - Invoke all irq_cpu_offline functions.
1090 *
1091 * Iterate through all irqs and invoke the chip.irq_cpu_offline()
1092 * for each.
1093 */
1094void irq_cpu_offline(void)
1095{
1096 struct irq_desc *desc;
1097 struct irq_chip *chip;
1098 unsigned long flags;
1099 unsigned int irq;
1100
1101 for_each_active_irq(irq) {
1102 desc = irq_to_desc(irq);
1103 if (!desc)
1104 continue;
1105
1106 raw_spin_lock_irqsave(&desc->lock, flags);
1107
1108 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
1109 if (chip && chip->irq_cpu_offline &&
1110 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 1111 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
1112 chip->irq_cpu_offline(&desc->irq_data);
1113
1114 raw_spin_unlock_irqrestore(&desc->lock, flags);
1115 }
1116}
85f08c17
JL
1117
1118#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
7703b08c
DD
1119
1120#ifdef CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS
1121/**
1122 * handle_fasteoi_ack_irq - irq handler for edge hierarchy
1123 * stacked on transparent controllers
1124 *
1125 * @desc: the interrupt description structure for this irq
1126 *
1127 * Like handle_fasteoi_irq(), but for use with hierarchy where
1128 * the irq_chip also needs to have its ->irq_ack() function
1129 * called.
1130 */
1131void handle_fasteoi_ack_irq(struct irq_desc *desc)
1132{
1133 struct irq_chip *chip = desc->irq_data.chip;
1134
1135 raw_spin_lock(&desc->lock);
1136
1137 if (!irq_may_run(desc))
1138 goto out;
1139
1140 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
1141
1142 /*
1143 * If its disabled or no action available
1144 * then mask it and get out of here:
1145 */
1146 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
1147 desc->istate |= IRQS_PENDING;
1148 mask_irq(desc);
1149 goto out;
1150 }
1151
1152 kstat_incr_irqs_this_cpu(desc);
1153 if (desc->istate & IRQS_ONESHOT)
1154 mask_irq(desc);
1155
1156 /* Start handling the irq */
1157 desc->irq_data.chip->irq_ack(&desc->irq_data);
1158
1159 preflow_handler(desc);
1160 handle_irq_event(desc);
1161
1162 cond_unmask_eoi_irq(desc, chip);
1163
1164 raw_spin_unlock(&desc->lock);
1165 return;
1166out:
1167 if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
1168 chip->irq_eoi(&desc->irq_data);
1169 raw_spin_unlock(&desc->lock);
1170}
1171EXPORT_SYMBOL_GPL(handle_fasteoi_ack_irq);
1172
1173/**
1174 * handle_fasteoi_mask_irq - irq handler for level hierarchy
1175 * stacked on transparent controllers
1176 *
1177 * @desc: the interrupt description structure for this irq
1178 *
1179 * Like handle_fasteoi_irq(), but for use with hierarchy where
1180 * the irq_chip also needs to have its ->irq_mask_ack() function
1181 * called.
1182 */
1183void handle_fasteoi_mask_irq(struct irq_desc *desc)
1184{
1185 struct irq_chip *chip = desc->irq_data.chip;
1186
1187 raw_spin_lock(&desc->lock);
1188 mask_ack_irq(desc);
1189
1190 if (!irq_may_run(desc))
1191 goto out;
1192
1193 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
1194
1195 /*
1196 * If its disabled or no action available
1197 * then mask it and get out of here:
1198 */
1199 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
1200 desc->istate |= IRQS_PENDING;
1201 mask_irq(desc);
1202 goto out;
1203 }
1204
1205 kstat_incr_irqs_this_cpu(desc);
1206 if (desc->istate & IRQS_ONESHOT)
1207 mask_irq(desc);
1208
1209 preflow_handler(desc);
1210 handle_irq_event(desc);
1211
1212 cond_unmask_eoi_irq(desc, chip);
1213
1214 raw_spin_unlock(&desc->lock);
1215 return;
1216out:
1217 if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
1218 chip->irq_eoi(&desc->irq_data);
1219 raw_spin_unlock(&desc->lock);
1220}
1221EXPORT_SYMBOL_GPL(handle_fasteoi_mask_irq);
1222
1223#endif /* CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS */
1224
3cfeffc2
SA
1225/**
1226 * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if
1227 * NULL)
1228 * @data: Pointer to interrupt specific data
1229 */
1230void irq_chip_enable_parent(struct irq_data *data)
1231{
1232 data = data->parent_data;
1233 if (data->chip->irq_enable)
1234 data->chip->irq_enable(data);
1235 else
1236 data->chip->irq_unmask(data);
1237}
65efd9a4 1238EXPORT_SYMBOL_GPL(irq_chip_enable_parent);
3cfeffc2
SA
1239
1240/**
1241 * irq_chip_disable_parent - Disable the parent interrupt (defaults to mask if
1242 * NULL)
1243 * @data: Pointer to interrupt specific data
1244 */
1245void irq_chip_disable_parent(struct irq_data *data)
1246{
1247 data = data->parent_data;
1248 if (data->chip->irq_disable)
1249 data->chip->irq_disable(data);
1250 else
1251 data->chip->irq_mask(data);
1252}
65efd9a4 1253EXPORT_SYMBOL_GPL(irq_chip_disable_parent);
3cfeffc2 1254
85f08c17
JL
1255/**
1256 * irq_chip_ack_parent - Acknowledge the parent interrupt
1257 * @data: Pointer to interrupt specific data
1258 */
1259void irq_chip_ack_parent(struct irq_data *data)
1260{
1261 data = data->parent_data;
1262 data->chip->irq_ack(data);
1263}
a4289dc2 1264EXPORT_SYMBOL_GPL(irq_chip_ack_parent);
85f08c17 1265
56e8abab
YC
1266/**
1267 * irq_chip_mask_parent - Mask the parent interrupt
1268 * @data: Pointer to interrupt specific data
1269 */
1270void irq_chip_mask_parent(struct irq_data *data)
1271{
1272 data = data->parent_data;
1273 data->chip->irq_mask(data);
1274}
52b2a05f 1275EXPORT_SYMBOL_GPL(irq_chip_mask_parent);
56e8abab
YC
1276
1277/**
1278 * irq_chip_unmask_parent - Unmask the parent interrupt
1279 * @data: Pointer to interrupt specific data
1280 */
1281void irq_chip_unmask_parent(struct irq_data *data)
1282{
1283 data = data->parent_data;
1284 data->chip->irq_unmask(data);
1285}
52b2a05f 1286EXPORT_SYMBOL_GPL(irq_chip_unmask_parent);
56e8abab
YC
1287
1288/**
1289 * irq_chip_eoi_parent - Invoke EOI on the parent interrupt
1290 * @data: Pointer to interrupt specific data
1291 */
1292void irq_chip_eoi_parent(struct irq_data *data)
1293{
1294 data = data->parent_data;
1295 data->chip->irq_eoi(data);
1296}
52b2a05f 1297EXPORT_SYMBOL_GPL(irq_chip_eoi_parent);
56e8abab
YC
1298
1299/**
1300 * irq_chip_set_affinity_parent - Set affinity on the parent interrupt
1301 * @data: Pointer to interrupt specific data
1302 * @dest: The affinity mask to set
1303 * @force: Flag to enforce setting (disable online checks)
1304 *
1305 * Conditinal, as the underlying parent chip might not implement it.
1306 */
1307int irq_chip_set_affinity_parent(struct irq_data *data,
1308 const struct cpumask *dest, bool force)
1309{
1310 data = data->parent_data;
1311 if (data->chip->irq_set_affinity)
1312 return data->chip->irq_set_affinity(data, dest, force);
b7560de1
GS
1313
1314 return -ENOSYS;
1315}
65efd9a4 1316EXPORT_SYMBOL_GPL(irq_chip_set_affinity_parent);
b7560de1
GS
1317
1318/**
1319 * irq_chip_set_type_parent - Set IRQ type on the parent interrupt
1320 * @data: Pointer to interrupt specific data
1321 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
1322 *
1323 * Conditional, as the underlying parent chip might not implement it.
1324 */
1325int irq_chip_set_type_parent(struct irq_data *data, unsigned int type)
1326{
1327 data = data->parent_data;
1328
1329 if (data->chip->irq_set_type)
1330 return data->chip->irq_set_type(data, type);
56e8abab
YC
1331
1332 return -ENOSYS;
1333}
52b2a05f 1334EXPORT_SYMBOL_GPL(irq_chip_set_type_parent);
56e8abab 1335
85f08c17
JL
1336/**
1337 * irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware
1338 * @data: Pointer to interrupt specific data
1339 *
1340 * Iterate through the domain hierarchy of the interrupt and check
1341 * whether a hw retrigger function exists. If yes, invoke it.
1342 */
1343int irq_chip_retrigger_hierarchy(struct irq_data *data)
1344{
1345 for (data = data->parent_data; data; data = data->parent_data)
1346 if (data->chip && data->chip->irq_retrigger)
1347 return data->chip->irq_retrigger(data);
1348
6d4affea 1349 return 0;
85f08c17 1350}
08b55e2a 1351
0a4377de
JL
1352/**
1353 * irq_chip_set_vcpu_affinity_parent - Set vcpu affinity on the parent interrupt
1354 * @data: Pointer to interrupt specific data
8505a81b 1355 * @vcpu_info: The vcpu affinity information
0a4377de
JL
1356 */
1357int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info)
1358{
1359 data = data->parent_data;
1360 if (data->chip->irq_set_vcpu_affinity)
1361 return data->chip->irq_set_vcpu_affinity(data, vcpu_info);
1362
1363 return -ENOSYS;
1364}
1365
08b55e2a
MZ
1366/**
1367 * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
1368 * @data: Pointer to interrupt specific data
1369 * @on: Whether to set or reset the wake-up capability of this irq
1370 *
1371 * Conditional, as the underlying parent chip might not implement it.
1372 */
1373int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
1374{
1375 data = data->parent_data;
1376 if (data->chip->irq_set_wake)
1377 return data->chip->irq_set_wake(data, on);
1378
1379 return -ENOSYS;
1380}
85f08c17 1381#endif
515085ef
JL
1382
1383/**
1384 * irq_chip_compose_msi_msg - Componse msi message for a irq chip
1385 * @data: Pointer to interrupt specific data
1386 * @msg: Pointer to the MSI message
1387 *
1388 * For hierarchical domains we find the first chip in the hierarchy
1389 * which implements the irq_compose_msi_msg callback. For non
1390 * hierarchical we use the top level chip.
1391 */
1392int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
1393{
1394 struct irq_data *pos = NULL;
1395
1396#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
1397 for (; data; data = data->parent_data)
1398#endif
1399 if (data->chip && data->chip->irq_compose_msi_msg)
1400 pos = data;
1401 if (!pos)
1402 return -ENOSYS;
1403
1404 pos->chip->irq_compose_msi_msg(pos, msg);
1405
1406 return 0;
1407}
be45beb2
JH
1408
1409/**
1410 * irq_chip_pm_get - Enable power for an IRQ chip
1411 * @data: Pointer to interrupt specific data
1412 *
1413 * Enable the power to the IRQ chip referenced by the interrupt data
1414 * structure.
1415 */
1416int irq_chip_pm_get(struct irq_data *data)
1417{
1418 int retval;
1419
1420 if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) {
1421 retval = pm_runtime_get_sync(data->chip->parent_device);
1422 if (retval < 0) {
1423 pm_runtime_put_noidle(data->chip->parent_device);
1424 return retval;
1425 }
1426 }
1427
1428 return 0;
1429}
1430
1431/**
1432 * irq_chip_pm_put - Disable power for an IRQ chip
1433 * @data: Pointer to interrupt specific data
1434 *
1435 * Disable the power to the IRQ chip referenced by the interrupt data
1436 * structure, belongs. Note that power will only be disabled, once this
1437 * function has been called for all IRQs that have called irq_chip_pm_get().
1438 */
1439int irq_chip_pm_put(struct irq_data *data)
1440{
1441 int retval = 0;
1442
1443 if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device)
1444 retval = pm_runtime_put(data->chip->parent_device);
1445
1446 return (retval < 0) ? retval : 0;
1447}