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Commit | Line | Data |
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dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
18 | ||
19 | #include "internals.h" | |
20 | ||
21 | /** | |
a0cd9ca2 | 22 | * irq_set_chip - set the irq chip for an irq |
dd87eb3a TG |
23 | * @irq: irq number |
24 | * @chip: pointer to irq chip description structure | |
25 | */ | |
a0cd9ca2 | 26 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) |
dd87eb3a | 27 | { |
dd87eb3a | 28 | unsigned long flags; |
02725e74 | 29 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); |
dd87eb3a | 30 | |
02725e74 | 31 | if (!desc) |
dd87eb3a | 32 | return -EINVAL; |
dd87eb3a TG |
33 | |
34 | if (!chip) | |
35 | chip = &no_irq_chip; | |
36 | ||
6b8ff312 | 37 | desc->irq_data.chip = chip; |
02725e74 | 38 | irq_put_desc_unlock(desc, flags); |
d72274e5 DD |
39 | /* |
40 | * For !CONFIG_SPARSE_IRQ make the irq show up in | |
41 | * allocated_irqs. For the CONFIG_SPARSE_IRQ case, it is | |
42 | * already marked, and this call is harmless. | |
43 | */ | |
44 | irq_reserve_irq(irq); | |
dd87eb3a TG |
45 | return 0; |
46 | } | |
a0cd9ca2 | 47 | EXPORT_SYMBOL(irq_set_chip); |
dd87eb3a TG |
48 | |
49 | /** | |
a0cd9ca2 | 50 | * irq_set_type - set the irq trigger type for an irq |
dd87eb3a | 51 | * @irq: irq number |
0c5d1eb7 | 52 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a | 53 | */ |
a0cd9ca2 | 54 | int irq_set_irq_type(unsigned int irq, unsigned int type) |
dd87eb3a | 55 | { |
dd87eb3a | 56 | unsigned long flags; |
02725e74 TG |
57 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags); |
58 | int ret = 0; | |
dd87eb3a | 59 | |
02725e74 TG |
60 | if (!desc) |
61 | return -EINVAL; | |
dd87eb3a | 62 | |
f2b662da | 63 | type &= IRQ_TYPE_SENSE_MASK; |
02725e74 TG |
64 | if (type != IRQ_TYPE_NONE) |
65 | ret = __irq_set_trigger(desc, irq, type); | |
66 | irq_put_desc_busunlock(desc, flags); | |
dd87eb3a TG |
67 | return ret; |
68 | } | |
a0cd9ca2 | 69 | EXPORT_SYMBOL(irq_set_irq_type); |
dd87eb3a TG |
70 | |
71 | /** | |
a0cd9ca2 | 72 | * irq_set_handler_data - set irq handler data for an irq |
dd87eb3a TG |
73 | * @irq: Interrupt number |
74 | * @data: Pointer to interrupt specific data | |
75 | * | |
76 | * Set the hardware irq controller data for an irq | |
77 | */ | |
a0cd9ca2 | 78 | int irq_set_handler_data(unsigned int irq, void *data) |
dd87eb3a | 79 | { |
dd87eb3a | 80 | unsigned long flags; |
02725e74 | 81 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); |
dd87eb3a | 82 | |
02725e74 | 83 | if (!desc) |
dd87eb3a | 84 | return -EINVAL; |
6b8ff312 | 85 | desc->irq_data.handler_data = data; |
02725e74 | 86 | irq_put_desc_unlock(desc, flags); |
dd87eb3a TG |
87 | return 0; |
88 | } | |
a0cd9ca2 | 89 | EXPORT_SYMBOL(irq_set_handler_data); |
dd87eb3a | 90 | |
5b912c10 | 91 | /** |
a0cd9ca2 | 92 | * irq_set_msi_desc - set MSI descriptor data for an irq |
5b912c10 | 93 | * @irq: Interrupt number |
472900b8 | 94 | * @entry: Pointer to MSI descriptor data |
5b912c10 | 95 | * |
24b26d42 | 96 | * Set the MSI descriptor entry for an irq |
5b912c10 | 97 | */ |
a0cd9ca2 | 98 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) |
5b912c10 | 99 | { |
5b912c10 | 100 | unsigned long flags; |
02725e74 | 101 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); |
5b912c10 | 102 | |
02725e74 | 103 | if (!desc) |
5b912c10 | 104 | return -EINVAL; |
6b8ff312 | 105 | desc->irq_data.msi_desc = entry; |
7fe3730d ME |
106 | if (entry) |
107 | entry->irq = irq; | |
02725e74 | 108 | irq_put_desc_unlock(desc, flags); |
5b912c10 EB |
109 | return 0; |
110 | } | |
111 | ||
dd87eb3a | 112 | /** |
a0cd9ca2 | 113 | * irq_set_chip_data - set irq chip data for an irq |
dd87eb3a TG |
114 | * @irq: Interrupt number |
115 | * @data: Pointer to chip specific data | |
116 | * | |
117 | * Set the hardware irq chip data for an irq | |
118 | */ | |
a0cd9ca2 | 119 | int irq_set_chip_data(unsigned int irq, void *data) |
dd87eb3a | 120 | { |
dd87eb3a | 121 | unsigned long flags; |
02725e74 | 122 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); |
dd87eb3a | 123 | |
02725e74 | 124 | if (!desc) |
dd87eb3a | 125 | return -EINVAL; |
6b8ff312 | 126 | desc->irq_data.chip_data = data; |
02725e74 | 127 | irq_put_desc_unlock(desc, flags); |
dd87eb3a TG |
128 | return 0; |
129 | } | |
a0cd9ca2 | 130 | EXPORT_SYMBOL(irq_set_chip_data); |
dd87eb3a | 131 | |
f303a6dd TG |
132 | struct irq_data *irq_get_irq_data(unsigned int irq) |
133 | { | |
134 | struct irq_desc *desc = irq_to_desc(irq); | |
135 | ||
136 | return desc ? &desc->irq_data : NULL; | |
137 | } | |
138 | EXPORT_SYMBOL_GPL(irq_get_irq_data); | |
139 | ||
c1594b77 TG |
140 | static void irq_state_clr_disabled(struct irq_desc *desc) |
141 | { | |
801a0e9a | 142 | irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED); |
c1594b77 TG |
143 | } |
144 | ||
145 | static void irq_state_set_disabled(struct irq_desc *desc) | |
146 | { | |
801a0e9a | 147 | irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); |
c1594b77 TG |
148 | } |
149 | ||
6e40262e TG |
150 | static void irq_state_clr_masked(struct irq_desc *desc) |
151 | { | |
32f4125e | 152 | irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED); |
6e40262e TG |
153 | } |
154 | ||
155 | static void irq_state_set_masked(struct irq_desc *desc) | |
156 | { | |
32f4125e | 157 | irqd_set(&desc->irq_data, IRQD_IRQ_MASKED); |
6e40262e TG |
158 | } |
159 | ||
46999238 TG |
160 | int irq_startup(struct irq_desc *desc) |
161 | { | |
c1594b77 | 162 | irq_state_clr_disabled(desc); |
46999238 TG |
163 | desc->depth = 0; |
164 | ||
3aae994f TG |
165 | if (desc->irq_data.chip->irq_startup) { |
166 | int ret = desc->irq_data.chip->irq_startup(&desc->irq_data); | |
6e40262e | 167 | irq_state_clr_masked(desc); |
3aae994f TG |
168 | return ret; |
169 | } | |
46999238 | 170 | |
87923470 | 171 | irq_enable(desc); |
46999238 TG |
172 | return 0; |
173 | } | |
174 | ||
175 | void irq_shutdown(struct irq_desc *desc) | |
176 | { | |
c1594b77 | 177 | irq_state_set_disabled(desc); |
46999238 | 178 | desc->depth = 1; |
50f7c032 TG |
179 | if (desc->irq_data.chip->irq_shutdown) |
180 | desc->irq_data.chip->irq_shutdown(&desc->irq_data); | |
181 | if (desc->irq_data.chip->irq_disable) | |
182 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
183 | else | |
184 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
6e40262e | 185 | irq_state_set_masked(desc); |
46999238 TG |
186 | } |
187 | ||
87923470 TG |
188 | void irq_enable(struct irq_desc *desc) |
189 | { | |
c1594b77 | 190 | irq_state_clr_disabled(desc); |
50f7c032 TG |
191 | if (desc->irq_data.chip->irq_enable) |
192 | desc->irq_data.chip->irq_enable(&desc->irq_data); | |
193 | else | |
194 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
6e40262e | 195 | irq_state_clr_masked(desc); |
dd87eb3a TG |
196 | } |
197 | ||
50f7c032 | 198 | void irq_disable(struct irq_desc *desc) |
89d694b9 | 199 | { |
c1594b77 | 200 | irq_state_set_disabled(desc); |
50f7c032 TG |
201 | if (desc->irq_data.chip->irq_disable) { |
202 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
a61d8258 | 203 | irq_state_set_masked(desc); |
50f7c032 | 204 | } |
89d694b9 TG |
205 | } |
206 | ||
9205e31d | 207 | static inline void mask_ack_irq(struct irq_desc *desc) |
dd87eb3a | 208 | { |
9205e31d TG |
209 | if (desc->irq_data.chip->irq_mask_ack) |
210 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | |
dd87eb3a | 211 | else { |
e2c0f8ff | 212 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
22a49163 TG |
213 | if (desc->irq_data.chip->irq_ack) |
214 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 215 | } |
6e40262e | 216 | irq_state_set_masked(desc); |
0b1adaa0 TG |
217 | } |
218 | ||
d4d5e089 | 219 | void mask_irq(struct irq_desc *desc) |
0b1adaa0 | 220 | { |
e2c0f8ff TG |
221 | if (desc->irq_data.chip->irq_mask) { |
222 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
6e40262e | 223 | irq_state_set_masked(desc); |
0b1adaa0 TG |
224 | } |
225 | } | |
226 | ||
d4d5e089 | 227 | void unmask_irq(struct irq_desc *desc) |
0b1adaa0 | 228 | { |
0eda58b7 TG |
229 | if (desc->irq_data.chip->irq_unmask) { |
230 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
6e40262e | 231 | irq_state_clr_masked(desc); |
0b1adaa0 | 232 | } |
dd87eb3a TG |
233 | } |
234 | ||
399b5da2 TG |
235 | /* |
236 | * handle_nested_irq - Handle a nested irq from a irq thread | |
237 | * @irq: the interrupt number | |
238 | * | |
239 | * Handle interrupts which are nested into a threaded interrupt | |
240 | * handler. The handler function is called inside the calling | |
241 | * threads context. | |
242 | */ | |
243 | void handle_nested_irq(unsigned int irq) | |
244 | { | |
245 | struct irq_desc *desc = irq_to_desc(irq); | |
246 | struct irqaction *action; | |
247 | irqreturn_t action_ret; | |
248 | ||
249 | might_sleep(); | |
250 | ||
239007b8 | 251 | raw_spin_lock_irq(&desc->lock); |
399b5da2 TG |
252 | |
253 | kstat_incr_irqs_this_cpu(irq, desc); | |
254 | ||
255 | action = desc->action; | |
32f4125e | 256 | if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) |
399b5da2 TG |
257 | goto out_unlock; |
258 | ||
32f4125e | 259 | irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
239007b8 | 260 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
261 | |
262 | action_ret = action->thread_fn(action->irq, action->dev_id); | |
263 | if (!noirqdebug) | |
264 | note_interrupt(irq, desc, action_ret); | |
265 | ||
239007b8 | 266 | raw_spin_lock_irq(&desc->lock); |
32f4125e | 267 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
399b5da2 TG |
268 | |
269 | out_unlock: | |
239007b8 | 270 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
271 | } |
272 | EXPORT_SYMBOL_GPL(handle_nested_irq); | |
273 | ||
fe200ae4 TG |
274 | static bool irq_check_poll(struct irq_desc *desc) |
275 | { | |
6954b75b | 276 | if (!(desc->istate & IRQS_POLL_INPROGRESS)) |
fe200ae4 TG |
277 | return false; |
278 | return irq_wait_for_poll(desc); | |
279 | } | |
280 | ||
dd87eb3a TG |
281 | /** |
282 | * handle_simple_irq - Simple and software-decoded IRQs. | |
283 | * @irq: the interrupt number | |
284 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
285 | * |
286 | * Simple interrupts are either sent from a demultiplexing interrupt | |
287 | * handler or come from hardware, where no interrupt hardware control | |
288 | * is necessary. | |
289 | * | |
290 | * Note: The caller is expected to handle the ack, clear, mask and | |
291 | * unmask issues if necessary. | |
292 | */ | |
7ad5b3a5 | 293 | void |
7d12e780 | 294 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 295 | { |
239007b8 | 296 | raw_spin_lock(&desc->lock); |
dd87eb3a | 297 | |
32f4125e | 298 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) |
fe200ae4 TG |
299 | if (!irq_check_poll(desc)) |
300 | goto out_unlock; | |
301 | ||
163ef309 | 302 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
d6c88a50 | 303 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a | 304 | |
32f4125e | 305 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) |
dd87eb3a TG |
306 | goto out_unlock; |
307 | ||
107781e7 | 308 | handle_irq_event(desc); |
dd87eb3a | 309 | |
dd87eb3a | 310 | out_unlock: |
239007b8 | 311 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
312 | } |
313 | ||
314 | /** | |
315 | * handle_level_irq - Level type irq handler | |
316 | * @irq: the interrupt number | |
317 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
318 | * |
319 | * Level type interrupts are active as long as the hardware line has | |
320 | * the active level. This may require to mask the interrupt and unmask | |
321 | * it after the associated handler has acknowledged the device, so the | |
322 | * interrupt line is back to inactive. | |
323 | */ | |
7ad5b3a5 | 324 | void |
7d12e780 | 325 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 326 | { |
239007b8 | 327 | raw_spin_lock(&desc->lock); |
9205e31d | 328 | mask_ack_irq(desc); |
dd87eb3a | 329 | |
32f4125e | 330 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) |
fe200ae4 TG |
331 | if (!irq_check_poll(desc)) |
332 | goto out_unlock; | |
333 | ||
163ef309 | 334 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
d6c88a50 | 335 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
336 | |
337 | /* | |
338 | * If its disabled or no action available | |
339 | * keep it masked and get out of here | |
340 | */ | |
32f4125e | 341 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) |
86998aa6 | 342 | goto out_unlock; |
dd87eb3a | 343 | |
1529866c | 344 | handle_irq_event(desc); |
b25c340c | 345 | |
32f4125e | 346 | if (!irqd_irq_disabled(&desc->irq_data) && !(desc->istate & IRQS_ONESHOT)) |
0eda58b7 | 347 | unmask_irq(desc); |
86998aa6 | 348 | out_unlock: |
239007b8 | 349 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 350 | } |
14819ea1 | 351 | EXPORT_SYMBOL_GPL(handle_level_irq); |
dd87eb3a | 352 | |
78129576 TG |
353 | #ifdef CONFIG_IRQ_PREFLOW_FASTEOI |
354 | static inline void preflow_handler(struct irq_desc *desc) | |
355 | { | |
356 | if (desc->preflow_handler) | |
357 | desc->preflow_handler(&desc->irq_data); | |
358 | } | |
359 | #else | |
360 | static inline void preflow_handler(struct irq_desc *desc) { } | |
361 | #endif | |
362 | ||
dd87eb3a | 363 | /** |
47c2a3aa | 364 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
365 | * @irq: the interrupt number |
366 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 367 | * |
47c2a3aa | 368 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
369 | * call when the interrupt has been serviced. This enables support |
370 | * for modern forms of interrupt handlers, which handle the flow | |
371 | * details in hardware, transparently. | |
372 | */ | |
7ad5b3a5 | 373 | void |
7d12e780 | 374 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 375 | { |
239007b8 | 376 | raw_spin_lock(&desc->lock); |
dd87eb3a | 377 | |
32f4125e | 378 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) |
fe200ae4 TG |
379 | if (!irq_check_poll(desc)) |
380 | goto out; | |
dd87eb3a | 381 | |
163ef309 | 382 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
d6c88a50 | 383 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
384 | |
385 | /* | |
386 | * If its disabled or no action available | |
76d21601 | 387 | * then mask it and get out of here: |
dd87eb3a | 388 | */ |
32f4125e | 389 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
2a0d6fb3 | 390 | desc->istate |= IRQS_PENDING; |
e2c0f8ff | 391 | mask_irq(desc); |
dd87eb3a | 392 | goto out; |
98bb244b | 393 | } |
c69e3758 TG |
394 | |
395 | if (desc->istate & IRQS_ONESHOT) | |
396 | mask_irq(desc); | |
397 | ||
78129576 | 398 | preflow_handler(desc); |
a7ae4de5 | 399 | handle_irq_event(desc); |
77694b40 TG |
400 | |
401 | out_eoi: | |
0c5c1557 | 402 | desc->irq_data.chip->irq_eoi(&desc->irq_data); |
77694b40 | 403 | out_unlock: |
239007b8 | 404 | raw_spin_unlock(&desc->lock); |
77694b40 TG |
405 | return; |
406 | out: | |
407 | if (!(desc->irq_data.chip->flags & IRQCHIP_EOI_IF_HANDLED)) | |
408 | goto out_eoi; | |
409 | goto out_unlock; | |
dd87eb3a TG |
410 | } |
411 | ||
412 | /** | |
413 | * handle_edge_irq - edge type IRQ handler | |
414 | * @irq: the interrupt number | |
415 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
416 | * |
417 | * Interrupt occures on the falling and/or rising edge of a hardware | |
25985edc | 418 | * signal. The occurrence is latched into the irq controller hardware |
dd87eb3a TG |
419 | * and must be acked in order to be reenabled. After the ack another |
420 | * interrupt can happen on the same source even before the first one | |
dfff0615 | 421 | * is handled by the associated event handler. If this happens it |
dd87eb3a TG |
422 | * might be necessary to disable (mask) the interrupt depending on the |
423 | * controller hardware. This requires to reenable the interrupt inside | |
424 | * of the loop which handles the interrupts which have arrived while | |
425 | * the handler was running. If all pending interrupts are handled, the | |
426 | * loop is left. | |
427 | */ | |
7ad5b3a5 | 428 | void |
7d12e780 | 429 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 430 | { |
239007b8 | 431 | raw_spin_lock(&desc->lock); |
dd87eb3a | 432 | |
163ef309 | 433 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
dd87eb3a TG |
434 | /* |
435 | * If we're currently running this IRQ, or its disabled, | |
436 | * we shouldn't process the IRQ. Mark it pending, handle | |
437 | * the necessary masking and go out | |
438 | */ | |
32f4125e TG |
439 | if (unlikely(irqd_irq_disabled(&desc->irq_data) || |
440 | irqd_irq_inprogress(&desc->irq_data) || !desc->action)) { | |
fe200ae4 | 441 | if (!irq_check_poll(desc)) { |
2a0d6fb3 | 442 | desc->istate |= IRQS_PENDING; |
fe200ae4 TG |
443 | mask_ack_irq(desc); |
444 | goto out_unlock; | |
445 | } | |
dd87eb3a | 446 | } |
d6c88a50 | 447 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
448 | |
449 | /* Start handling the irq */ | |
22a49163 | 450 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
dd87eb3a | 451 | |
dd87eb3a | 452 | do { |
a60a5dc2 | 453 | if (unlikely(!desc->action)) { |
e2c0f8ff | 454 | mask_irq(desc); |
dd87eb3a TG |
455 | goto out_unlock; |
456 | } | |
457 | ||
458 | /* | |
459 | * When another irq arrived while we were handling | |
460 | * one, we could have masked the irq. | |
461 | * Renable it, if it was not disabled in meantime. | |
462 | */ | |
2a0d6fb3 | 463 | if (unlikely(desc->istate & IRQS_PENDING)) { |
32f4125e TG |
464 | if (!irqd_irq_disabled(&desc->irq_data) && |
465 | irqd_irq_masked(&desc->irq_data)) | |
c1594b77 | 466 | unmask_irq(desc); |
dd87eb3a TG |
467 | } |
468 | ||
a60a5dc2 | 469 | handle_irq_event(desc); |
dd87eb3a | 470 | |
2a0d6fb3 | 471 | } while ((desc->istate & IRQS_PENDING) && |
32f4125e | 472 | !irqd_irq_disabled(&desc->irq_data)); |
dd87eb3a | 473 | |
dd87eb3a | 474 | out_unlock: |
239007b8 | 475 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
476 | } |
477 | ||
0521c8fb TG |
478 | #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER |
479 | /** | |
480 | * handle_edge_eoi_irq - edge eoi type IRQ handler | |
481 | * @irq: the interrupt number | |
482 | * @desc: the interrupt description structure for this irq | |
483 | * | |
484 | * Similar as the above handle_edge_irq, but using eoi and w/o the | |
485 | * mask/unmask logic. | |
486 | */ | |
487 | void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc) | |
488 | { | |
489 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
490 | ||
491 | raw_spin_lock(&desc->lock); | |
492 | ||
493 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | |
494 | /* | |
495 | * If we're currently running this IRQ, or its disabled, | |
496 | * we shouldn't process the IRQ. Mark it pending, handle | |
497 | * the necessary masking and go out | |
498 | */ | |
499 | if (unlikely(irqd_irq_disabled(&desc->irq_data) || | |
500 | irqd_irq_inprogress(&desc->irq_data) || !desc->action)) { | |
501 | if (!irq_check_poll(desc)) { | |
502 | desc->istate |= IRQS_PENDING; | |
503 | goto out_eoi; | |
504 | } | |
505 | } | |
506 | kstat_incr_irqs_this_cpu(irq, desc); | |
507 | ||
508 | do { | |
509 | if (unlikely(!desc->action)) | |
510 | goto out_eoi; | |
511 | ||
512 | handle_irq_event(desc); | |
513 | ||
514 | } while ((desc->istate & IRQS_PENDING) && | |
515 | !irqd_irq_disabled(&desc->irq_data)); | |
516 | ||
ac0e0447 | 517 | out_eoi: |
0521c8fb TG |
518 | chip->irq_eoi(&desc->irq_data); |
519 | raw_spin_unlock(&desc->lock); | |
520 | } | |
521 | #endif | |
522 | ||
dd87eb3a | 523 | /** |
24b26d42 | 524 | * handle_percpu_irq - Per CPU local irq handler |
dd87eb3a TG |
525 | * @irq: the interrupt number |
526 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
527 | * |
528 | * Per CPU interrupts on SMP machines without locking requirements | |
529 | */ | |
7ad5b3a5 | 530 | void |
7d12e780 | 531 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 532 | { |
35e857cb | 533 | struct irq_chip *chip = irq_desc_get_chip(desc); |
dd87eb3a | 534 | |
d6c88a50 | 535 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a | 536 | |
849f061c TG |
537 | if (chip->irq_ack) |
538 | chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 539 | |
849f061c | 540 | handle_irq_event_percpu(desc, desc->action); |
dd87eb3a | 541 | |
849f061c TG |
542 | if (chip->irq_eoi) |
543 | chip->irq_eoi(&desc->irq_data); | |
dd87eb3a TG |
544 | } |
545 | ||
dd87eb3a | 546 | void |
3836ca08 | 547 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
a460e745 | 548 | const char *name) |
dd87eb3a | 549 | { |
dd87eb3a | 550 | unsigned long flags; |
02725e74 | 551 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags); |
dd87eb3a | 552 | |
02725e74 | 553 | if (!desc) |
dd87eb3a | 554 | return; |
dd87eb3a | 555 | |
091738a2 | 556 | if (!handle) { |
dd87eb3a | 557 | handle = handle_bad_irq; |
091738a2 TG |
558 | } else { |
559 | if (WARN_ON(desc->irq_data.chip == &no_irq_chip)) | |
02725e74 | 560 | goto out; |
f8b5473f | 561 | } |
dd87eb3a | 562 | |
dd87eb3a TG |
563 | /* Uninstall? */ |
564 | if (handle == handle_bad_irq) { | |
6b8ff312 | 565 | if (desc->irq_data.chip != &no_irq_chip) |
9205e31d | 566 | mask_ack_irq(desc); |
801a0e9a | 567 | irq_state_set_disabled(desc); |
dd87eb3a TG |
568 | desc->depth = 1; |
569 | } | |
570 | desc->handle_irq = handle; | |
a460e745 | 571 | desc->name = name; |
dd87eb3a TG |
572 | |
573 | if (handle != handle_bad_irq && is_chained) { | |
1ccb4e61 TG |
574 | irq_settings_set_noprobe(desc); |
575 | irq_settings_set_norequest(desc); | |
46999238 | 576 | irq_startup(desc); |
dd87eb3a | 577 | } |
02725e74 TG |
578 | out: |
579 | irq_put_desc_busunlock(desc, flags); | |
dd87eb3a | 580 | } |
3836ca08 | 581 | EXPORT_SYMBOL_GPL(__irq_set_handler); |
dd87eb3a TG |
582 | |
583 | void | |
3836ca08 | 584 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 | 585 | irq_flow_handler_t handle, const char *name) |
dd87eb3a | 586 | { |
35e857cb | 587 | irq_set_chip(irq, chip); |
3836ca08 | 588 | __irq_set_handler(irq, handle, 0, name); |
dd87eb3a | 589 | } |
46f4f8f6 | 590 | |
44247184 | 591 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
46f4f8f6 | 592 | { |
46f4f8f6 | 593 | unsigned long flags; |
02725e74 | 594 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); |
46f4f8f6 | 595 | |
44247184 | 596 | if (!desc) |
46f4f8f6 | 597 | return; |
a005677b TG |
598 | irq_settings_clr_and_set(desc, clr, set); |
599 | ||
876dbd4c | 600 | irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | |
e1ef8241 | 601 | IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); |
a005677b TG |
602 | if (irq_settings_has_no_balance_set(desc)) |
603 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | |
604 | if (irq_settings_is_per_cpu(desc)) | |
605 | irqd_set(&desc->irq_data, IRQD_PER_CPU); | |
e1ef8241 TG |
606 | if (irq_settings_can_move_pcntxt(desc)) |
607 | irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); | |
0ef5ca1e TG |
608 | if (irq_settings_is_level(desc)) |
609 | irqd_set(&desc->irq_data, IRQD_LEVEL); | |
a005677b | 610 | |
876dbd4c TG |
611 | irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); |
612 | ||
02725e74 | 613 | irq_put_desc_unlock(desc, flags); |
46f4f8f6 | 614 | } |
0fdb4b25 DD |
615 | |
616 | /** | |
617 | * irq_cpu_online - Invoke all irq_cpu_online functions. | |
618 | * | |
619 | * Iterate through all irqs and invoke the chip.irq_cpu_online() | |
620 | * for each. | |
621 | */ | |
622 | void irq_cpu_online(void) | |
623 | { | |
624 | struct irq_desc *desc; | |
625 | struct irq_chip *chip; | |
626 | unsigned long flags; | |
627 | unsigned int irq; | |
628 | ||
629 | for_each_active_irq(irq) { | |
630 | desc = irq_to_desc(irq); | |
631 | if (!desc) | |
632 | continue; | |
633 | ||
634 | raw_spin_lock_irqsave(&desc->lock, flags); | |
635 | ||
636 | chip = irq_data_get_irq_chip(&desc->irq_data); | |
b3d42232 TG |
637 | if (chip && chip->irq_cpu_online && |
638 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | |
32f4125e | 639 | !irqd_irq_disabled(&desc->irq_data))) |
0fdb4b25 DD |
640 | chip->irq_cpu_online(&desc->irq_data); |
641 | ||
642 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
643 | } | |
644 | } | |
645 | ||
646 | /** | |
647 | * irq_cpu_offline - Invoke all irq_cpu_offline functions. | |
648 | * | |
649 | * Iterate through all irqs and invoke the chip.irq_cpu_offline() | |
650 | * for each. | |
651 | */ | |
652 | void irq_cpu_offline(void) | |
653 | { | |
654 | struct irq_desc *desc; | |
655 | struct irq_chip *chip; | |
656 | unsigned long flags; | |
657 | unsigned int irq; | |
658 | ||
659 | for_each_active_irq(irq) { | |
660 | desc = irq_to_desc(irq); | |
661 | if (!desc) | |
662 | continue; | |
663 | ||
664 | raw_spin_lock_irqsave(&desc->lock, flags); | |
665 | ||
666 | chip = irq_data_get_irq_chip(&desc->irq_data); | |
b3d42232 TG |
667 | if (chip && chip->irq_cpu_offline && |
668 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | |
32f4125e | 669 | !irqd_irq_disabled(&desc->irq_data))) |
0fdb4b25 DD |
670 | chip->irq_cpu_offline(&desc->irq_data); |
671 | ||
672 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
673 | } | |
674 | } |