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[mirror_ubuntu-artful-kernel.git] / kernel / irq / chip.c
CommitLineData
dd87eb3a
TG
1/*
2 * linux/kernel/irq/chip.c
3 *
4 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
5 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 *
7 * This file contains the core interrupt handling code, for irq-chip
8 * based architectures.
9 *
10 * Detailed information is available in Documentation/DocBook/genericirq
11 */
12
13#include <linux/irq.h>
7fe3730d 14#include <linux/msi.h>
dd87eb3a
TG
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/kernel_stat.h>
18
f069686e
SR
19#include <trace/events/irq.h>
20
dd87eb3a
TG
21#include "internals.h"
22
23/**
a0cd9ca2 24 * irq_set_chip - set the irq chip for an irq
dd87eb3a
TG
25 * @irq: irq number
26 * @chip: pointer to irq chip description structure
27 */
a0cd9ca2 28int irq_set_chip(unsigned int irq, struct irq_chip *chip)
dd87eb3a 29{
dd87eb3a 30 unsigned long flags;
31d9d9b6 31 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 32
02725e74 33 if (!desc)
dd87eb3a 34 return -EINVAL;
dd87eb3a
TG
35
36 if (!chip)
37 chip = &no_irq_chip;
38
6b8ff312 39 desc->irq_data.chip = chip;
02725e74 40 irq_put_desc_unlock(desc, flags);
d72274e5
DD
41 /*
42 * For !CONFIG_SPARSE_IRQ make the irq show up in
f63b6a05 43 * allocated_irqs.
d72274e5 44 */
f63b6a05 45 irq_mark_irq(irq);
dd87eb3a
TG
46 return 0;
47}
a0cd9ca2 48EXPORT_SYMBOL(irq_set_chip);
dd87eb3a
TG
49
50/**
a0cd9ca2 51 * irq_set_type - set the irq trigger type for an irq
dd87eb3a 52 * @irq: irq number
0c5d1eb7 53 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
dd87eb3a 54 */
a0cd9ca2 55int irq_set_irq_type(unsigned int irq, unsigned int type)
dd87eb3a 56{
dd87eb3a 57 unsigned long flags;
31d9d9b6 58 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
02725e74 59 int ret = 0;
dd87eb3a 60
02725e74
TG
61 if (!desc)
62 return -EINVAL;
dd87eb3a 63
f2b662da 64 type &= IRQ_TYPE_SENSE_MASK;
a09b659c 65 ret = __irq_set_trigger(desc, irq, type);
02725e74 66 irq_put_desc_busunlock(desc, flags);
dd87eb3a
TG
67 return ret;
68}
a0cd9ca2 69EXPORT_SYMBOL(irq_set_irq_type);
dd87eb3a
TG
70
71/**
a0cd9ca2 72 * irq_set_handler_data - set irq handler data for an irq
dd87eb3a
TG
73 * @irq: Interrupt number
74 * @data: Pointer to interrupt specific data
75 *
76 * Set the hardware irq controller data for an irq
77 */
a0cd9ca2 78int irq_set_handler_data(unsigned int irq, void *data)
dd87eb3a 79{
dd87eb3a 80 unsigned long flags;
31d9d9b6 81 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 82
02725e74 83 if (!desc)
dd87eb3a 84 return -EINVAL;
6b8ff312 85 desc->irq_data.handler_data = data;
02725e74 86 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
87 return 0;
88}
a0cd9ca2 89EXPORT_SYMBOL(irq_set_handler_data);
dd87eb3a 90
5b912c10 91/**
51906e77
AG
92 * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset
93 * @irq_base: Interrupt number base
94 * @irq_offset: Interrupt number offset
95 * @entry: Pointer to MSI descriptor data
5b912c10 96 *
51906e77 97 * Set the MSI descriptor entry for an irq at offset
5b912c10 98 */
51906e77
AG
99int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
100 struct msi_desc *entry)
5b912c10 101{
5b912c10 102 unsigned long flags;
51906e77 103 struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
5b912c10 104
02725e74 105 if (!desc)
5b912c10 106 return -EINVAL;
6b8ff312 107 desc->irq_data.msi_desc = entry;
51906e77
AG
108 if (entry && !irq_offset)
109 entry->irq = irq_base;
02725e74 110 irq_put_desc_unlock(desc, flags);
5b912c10
EB
111 return 0;
112}
113
51906e77
AG
114/**
115 * irq_set_msi_desc - set MSI descriptor data for an irq
116 * @irq: Interrupt number
117 * @entry: Pointer to MSI descriptor data
118 *
119 * Set the MSI descriptor entry for an irq
120 */
121int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
122{
123 return irq_set_msi_desc_off(irq, 0, entry);
124}
125
dd87eb3a 126/**
a0cd9ca2 127 * irq_set_chip_data - set irq chip data for an irq
dd87eb3a
TG
128 * @irq: Interrupt number
129 * @data: Pointer to chip specific data
130 *
131 * Set the hardware irq chip data for an irq
132 */
a0cd9ca2 133int irq_set_chip_data(unsigned int irq, void *data)
dd87eb3a 134{
dd87eb3a 135 unsigned long flags;
31d9d9b6 136 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 137
02725e74 138 if (!desc)
dd87eb3a 139 return -EINVAL;
6b8ff312 140 desc->irq_data.chip_data = data;
02725e74 141 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
142 return 0;
143}
a0cd9ca2 144EXPORT_SYMBOL(irq_set_chip_data);
dd87eb3a 145
f303a6dd
TG
146struct irq_data *irq_get_irq_data(unsigned int irq)
147{
148 struct irq_desc *desc = irq_to_desc(irq);
149
150 return desc ? &desc->irq_data : NULL;
151}
152EXPORT_SYMBOL_GPL(irq_get_irq_data);
153
c1594b77
TG
154static void irq_state_clr_disabled(struct irq_desc *desc)
155{
801a0e9a 156 irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
157}
158
159static void irq_state_set_disabled(struct irq_desc *desc)
160{
801a0e9a 161 irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
162}
163
6e40262e
TG
164static void irq_state_clr_masked(struct irq_desc *desc)
165{
32f4125e 166 irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
167}
168
169static void irq_state_set_masked(struct irq_desc *desc)
170{
32f4125e 171 irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
172}
173
b4bc724e 174int irq_startup(struct irq_desc *desc, bool resend)
46999238 175{
b4bc724e
TG
176 int ret = 0;
177
c1594b77 178 irq_state_clr_disabled(desc);
46999238
TG
179 desc->depth = 0;
180
3aae994f 181 if (desc->irq_data.chip->irq_startup) {
b4bc724e 182 ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
6e40262e 183 irq_state_clr_masked(desc);
b4bc724e
TG
184 } else {
185 irq_enable(desc);
3aae994f 186 }
b4bc724e
TG
187 if (resend)
188 check_irq_resend(desc, desc->irq_data.irq);
189 return ret;
46999238
TG
190}
191
192void irq_shutdown(struct irq_desc *desc)
193{
c1594b77 194 irq_state_set_disabled(desc);
46999238 195 desc->depth = 1;
50f7c032
TG
196 if (desc->irq_data.chip->irq_shutdown)
197 desc->irq_data.chip->irq_shutdown(&desc->irq_data);
ed585a65 198 else if (desc->irq_data.chip->irq_disable)
50f7c032
TG
199 desc->irq_data.chip->irq_disable(&desc->irq_data);
200 else
201 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 202 irq_state_set_masked(desc);
46999238
TG
203}
204
87923470
TG
205void irq_enable(struct irq_desc *desc)
206{
c1594b77 207 irq_state_clr_disabled(desc);
50f7c032
TG
208 if (desc->irq_data.chip->irq_enable)
209 desc->irq_data.chip->irq_enable(&desc->irq_data);
210 else
211 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 212 irq_state_clr_masked(desc);
dd87eb3a
TG
213}
214
d671a605 215/**
f788e7bf 216 * irq_disable - Mark interrupt disabled
d671a605
AF
217 * @desc: irq descriptor which should be disabled
218 *
219 * If the chip does not implement the irq_disable callback, we
220 * use a lazy disable approach. That means we mark the interrupt
221 * disabled, but leave the hardware unmasked. That's an
222 * optimization because we avoid the hardware access for the
223 * common case where no interrupt happens after we marked it
224 * disabled. If an interrupt happens, then the interrupt flow
225 * handler masks the line at the hardware level and marks it
226 * pending.
227 */
50f7c032 228void irq_disable(struct irq_desc *desc)
89d694b9 229{
c1594b77 230 irq_state_set_disabled(desc);
50f7c032
TG
231 if (desc->irq_data.chip->irq_disable) {
232 desc->irq_data.chip->irq_disable(&desc->irq_data);
a61d8258 233 irq_state_set_masked(desc);
50f7c032 234 }
89d694b9
TG
235}
236
31d9d9b6
MZ
237void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu)
238{
239 if (desc->irq_data.chip->irq_enable)
240 desc->irq_data.chip->irq_enable(&desc->irq_data);
241 else
242 desc->irq_data.chip->irq_unmask(&desc->irq_data);
243 cpumask_set_cpu(cpu, desc->percpu_enabled);
244}
245
246void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu)
247{
248 if (desc->irq_data.chip->irq_disable)
249 desc->irq_data.chip->irq_disable(&desc->irq_data);
250 else
251 desc->irq_data.chip->irq_mask(&desc->irq_data);
252 cpumask_clear_cpu(cpu, desc->percpu_enabled);
253}
254
9205e31d 255static inline void mask_ack_irq(struct irq_desc *desc)
dd87eb3a 256{
9205e31d
TG
257 if (desc->irq_data.chip->irq_mask_ack)
258 desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
dd87eb3a 259 else {
e2c0f8ff 260 desc->irq_data.chip->irq_mask(&desc->irq_data);
22a49163
TG
261 if (desc->irq_data.chip->irq_ack)
262 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 263 }
6e40262e 264 irq_state_set_masked(desc);
0b1adaa0
TG
265}
266
d4d5e089 267void mask_irq(struct irq_desc *desc)
0b1adaa0 268{
e2c0f8ff
TG
269 if (desc->irq_data.chip->irq_mask) {
270 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 271 irq_state_set_masked(desc);
0b1adaa0
TG
272 }
273}
274
d4d5e089 275void unmask_irq(struct irq_desc *desc)
0b1adaa0 276{
0eda58b7
TG
277 if (desc->irq_data.chip->irq_unmask) {
278 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 279 irq_state_clr_masked(desc);
0b1adaa0 280 }
dd87eb3a
TG
281}
282
328a4978
TG
283void unmask_threaded_irq(struct irq_desc *desc)
284{
285 struct irq_chip *chip = desc->irq_data.chip;
286
287 if (chip->flags & IRQCHIP_EOI_THREADED)
288 chip->irq_eoi(&desc->irq_data);
289
290 if (chip->irq_unmask) {
291 chip->irq_unmask(&desc->irq_data);
292 irq_state_clr_masked(desc);
293 }
294}
295
399b5da2
TG
296/*
297 * handle_nested_irq - Handle a nested irq from a irq thread
298 * @irq: the interrupt number
299 *
300 * Handle interrupts which are nested into a threaded interrupt
301 * handler. The handler function is called inside the calling
302 * threads context.
303 */
304void handle_nested_irq(unsigned int irq)
305{
306 struct irq_desc *desc = irq_to_desc(irq);
307 struct irqaction *action;
308 irqreturn_t action_ret;
309
310 might_sleep();
311
239007b8 312 raw_spin_lock_irq(&desc->lock);
399b5da2 313
293a7a0a 314 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
399b5da2
TG
315 kstat_incr_irqs_this_cpu(irq, desc);
316
317 action = desc->action;
23812b9d
NJ
318 if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) {
319 desc->istate |= IRQS_PENDING;
399b5da2 320 goto out_unlock;
23812b9d 321 }
399b5da2 322
32f4125e 323 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
239007b8 324 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
325
326 action_ret = action->thread_fn(action->irq, action->dev_id);
327 if (!noirqdebug)
328 note_interrupt(irq, desc, action_ret);
329
239007b8 330 raw_spin_lock_irq(&desc->lock);
32f4125e 331 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
399b5da2
TG
332
333out_unlock:
239007b8 334 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
335}
336EXPORT_SYMBOL_GPL(handle_nested_irq);
337
fe200ae4
TG
338static bool irq_check_poll(struct irq_desc *desc)
339{
6954b75b 340 if (!(desc->istate & IRQS_POLL_INPROGRESS))
fe200ae4
TG
341 return false;
342 return irq_wait_for_poll(desc);
343}
344
dd87eb3a
TG
345/**
346 * handle_simple_irq - Simple and software-decoded IRQs.
347 * @irq: the interrupt number
348 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
349 *
350 * Simple interrupts are either sent from a demultiplexing interrupt
351 * handler or come from hardware, where no interrupt hardware control
352 * is necessary.
353 *
354 * Note: The caller is expected to handle the ack, clear, mask and
355 * unmask issues if necessary.
356 */
7ad5b3a5 357void
7d12e780 358handle_simple_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 359{
239007b8 360 raw_spin_lock(&desc->lock);
dd87eb3a 361
32f4125e 362 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
363 if (!irq_check_poll(desc))
364 goto out_unlock;
365
163ef309 366 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 367 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 368
23812b9d
NJ
369 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
370 desc->istate |= IRQS_PENDING;
dd87eb3a 371 goto out_unlock;
23812b9d 372 }
dd87eb3a 373
107781e7 374 handle_irq_event(desc);
dd87eb3a 375
dd87eb3a 376out_unlock:
239007b8 377 raw_spin_unlock(&desc->lock);
dd87eb3a 378}
edf76f83 379EXPORT_SYMBOL_GPL(handle_simple_irq);
dd87eb3a 380
ac563761
TG
381/*
382 * Called unconditionally from handle_level_irq() and only for oneshot
383 * interrupts from handle_fasteoi_irq()
384 */
385static void cond_unmask_irq(struct irq_desc *desc)
386{
387 /*
388 * We need to unmask in the following cases:
389 * - Standard level irq (IRQF_ONESHOT is not set)
390 * - Oneshot irq which did not wake the thread (caused by a
391 * spurious interrupt or a primary handler handling it
392 * completely).
393 */
394 if (!irqd_irq_disabled(&desc->irq_data) &&
395 irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot)
396 unmask_irq(desc);
397}
398
dd87eb3a
TG
399/**
400 * handle_level_irq - Level type irq handler
401 * @irq: the interrupt number
402 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
403 *
404 * Level type interrupts are active as long as the hardware line has
405 * the active level. This may require to mask the interrupt and unmask
406 * it after the associated handler has acknowledged the device, so the
407 * interrupt line is back to inactive.
408 */
7ad5b3a5 409void
7d12e780 410handle_level_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 411{
239007b8 412 raw_spin_lock(&desc->lock);
9205e31d 413 mask_ack_irq(desc);
dd87eb3a 414
32f4125e 415 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
416 if (!irq_check_poll(desc))
417 goto out_unlock;
418
163ef309 419 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 420 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
421
422 /*
423 * If its disabled or no action available
424 * keep it masked and get out of here
425 */
d4dc0f90
TG
426 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
427 desc->istate |= IRQS_PENDING;
86998aa6 428 goto out_unlock;
d4dc0f90 429 }
dd87eb3a 430
1529866c 431 handle_irq_event(desc);
b25c340c 432
ac563761
TG
433 cond_unmask_irq(desc);
434
86998aa6 435out_unlock:
239007b8 436 raw_spin_unlock(&desc->lock);
dd87eb3a 437}
14819ea1 438EXPORT_SYMBOL_GPL(handle_level_irq);
dd87eb3a 439
78129576
TG
440#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
441static inline void preflow_handler(struct irq_desc *desc)
442{
443 if (desc->preflow_handler)
444 desc->preflow_handler(&desc->irq_data);
445}
446#else
447static inline void preflow_handler(struct irq_desc *desc) { }
448#endif
449
328a4978
TG
450static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
451{
452 if (!(desc->istate & IRQS_ONESHOT)) {
453 chip->irq_eoi(&desc->irq_data);
454 return;
455 }
456 /*
457 * We need to unmask in the following cases:
458 * - Oneshot irq which did not wake the thread (caused by a
459 * spurious interrupt or a primary handler handling it
460 * completely).
461 */
462 if (!irqd_irq_disabled(&desc->irq_data) &&
463 irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) {
464 chip->irq_eoi(&desc->irq_data);
465 unmask_irq(desc);
466 } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) {
467 chip->irq_eoi(&desc->irq_data);
468 }
469}
470
dd87eb3a 471/**
47c2a3aa 472 * handle_fasteoi_irq - irq handler for transparent controllers
dd87eb3a
TG
473 * @irq: the interrupt number
474 * @desc: the interrupt description structure for this irq
dd87eb3a 475 *
47c2a3aa 476 * Only a single callback will be issued to the chip: an ->eoi()
dd87eb3a
TG
477 * call when the interrupt has been serviced. This enables support
478 * for modern forms of interrupt handlers, which handle the flow
479 * details in hardware, transparently.
480 */
7ad5b3a5 481void
7d12e780 482handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 483{
328a4978
TG
484 struct irq_chip *chip = desc->irq_data.chip;
485
239007b8 486 raw_spin_lock(&desc->lock);
dd87eb3a 487
32f4125e 488 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
489 if (!irq_check_poll(desc))
490 goto out;
dd87eb3a 491
163ef309 492 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 493 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
494
495 /*
496 * If its disabled or no action available
76d21601 497 * then mask it and get out of here:
dd87eb3a 498 */
32f4125e 499 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
2a0d6fb3 500 desc->istate |= IRQS_PENDING;
e2c0f8ff 501 mask_irq(desc);
dd87eb3a 502 goto out;
98bb244b 503 }
c69e3758
TG
504
505 if (desc->istate & IRQS_ONESHOT)
506 mask_irq(desc);
507
78129576 508 preflow_handler(desc);
a7ae4de5 509 handle_irq_event(desc);
77694b40 510
328a4978 511 cond_unmask_eoi_irq(desc, chip);
ac563761 512
239007b8 513 raw_spin_unlock(&desc->lock);
77694b40
TG
514 return;
515out:
328a4978
TG
516 if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
517 chip->irq_eoi(&desc->irq_data);
518 raw_spin_unlock(&desc->lock);
dd87eb3a
TG
519}
520
521/**
522 * handle_edge_irq - edge type IRQ handler
523 * @irq: the interrupt number
524 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
525 *
526 * Interrupt occures on the falling and/or rising edge of a hardware
25985edc 527 * signal. The occurrence is latched into the irq controller hardware
dd87eb3a
TG
528 * and must be acked in order to be reenabled. After the ack another
529 * interrupt can happen on the same source even before the first one
dfff0615 530 * is handled by the associated event handler. If this happens it
dd87eb3a
TG
531 * might be necessary to disable (mask) the interrupt depending on the
532 * controller hardware. This requires to reenable the interrupt inside
533 * of the loop which handles the interrupts which have arrived while
534 * the handler was running. If all pending interrupts are handled, the
535 * loop is left.
536 */
7ad5b3a5 537void
7d12e780 538handle_edge_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 539{
239007b8 540 raw_spin_lock(&desc->lock);
dd87eb3a 541
163ef309 542 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
543 /*
544 * If we're currently running this IRQ, or its disabled,
545 * we shouldn't process the IRQ. Mark it pending, handle
546 * the necessary masking and go out
547 */
32f4125e
TG
548 if (unlikely(irqd_irq_disabled(&desc->irq_data) ||
549 irqd_irq_inprogress(&desc->irq_data) || !desc->action)) {
fe200ae4 550 if (!irq_check_poll(desc)) {
2a0d6fb3 551 desc->istate |= IRQS_PENDING;
fe200ae4
TG
552 mask_ack_irq(desc);
553 goto out_unlock;
554 }
dd87eb3a 555 }
d6c88a50 556 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
557
558 /* Start handling the irq */
22a49163 559 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 560
dd87eb3a 561 do {
a60a5dc2 562 if (unlikely(!desc->action)) {
e2c0f8ff 563 mask_irq(desc);
dd87eb3a
TG
564 goto out_unlock;
565 }
566
567 /*
568 * When another irq arrived while we were handling
569 * one, we could have masked the irq.
570 * Renable it, if it was not disabled in meantime.
571 */
2a0d6fb3 572 if (unlikely(desc->istate & IRQS_PENDING)) {
32f4125e
TG
573 if (!irqd_irq_disabled(&desc->irq_data) &&
574 irqd_irq_masked(&desc->irq_data))
c1594b77 575 unmask_irq(desc);
dd87eb3a
TG
576 }
577
a60a5dc2 578 handle_irq_event(desc);
dd87eb3a 579
2a0d6fb3 580 } while ((desc->istate & IRQS_PENDING) &&
32f4125e 581 !irqd_irq_disabled(&desc->irq_data));
dd87eb3a 582
dd87eb3a 583out_unlock:
239007b8 584 raw_spin_unlock(&desc->lock);
dd87eb3a 585}
3911ff30 586EXPORT_SYMBOL(handle_edge_irq);
dd87eb3a 587
0521c8fb
TG
588#ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
589/**
590 * handle_edge_eoi_irq - edge eoi type IRQ handler
591 * @irq: the interrupt number
592 * @desc: the interrupt description structure for this irq
593 *
594 * Similar as the above handle_edge_irq, but using eoi and w/o the
595 * mask/unmask logic.
596 */
597void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc)
598{
599 struct irq_chip *chip = irq_desc_get_chip(desc);
600
601 raw_spin_lock(&desc->lock);
602
603 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
604 /*
605 * If we're currently running this IRQ, or its disabled,
606 * we shouldn't process the IRQ. Mark it pending, handle
607 * the necessary masking and go out
608 */
609 if (unlikely(irqd_irq_disabled(&desc->irq_data) ||
610 irqd_irq_inprogress(&desc->irq_data) || !desc->action)) {
611 if (!irq_check_poll(desc)) {
612 desc->istate |= IRQS_PENDING;
613 goto out_eoi;
614 }
615 }
616 kstat_incr_irqs_this_cpu(irq, desc);
617
618 do {
619 if (unlikely(!desc->action))
620 goto out_eoi;
621
622 handle_irq_event(desc);
623
624 } while ((desc->istate & IRQS_PENDING) &&
625 !irqd_irq_disabled(&desc->irq_data));
626
ac0e0447 627out_eoi:
0521c8fb
TG
628 chip->irq_eoi(&desc->irq_data);
629 raw_spin_unlock(&desc->lock);
630}
631#endif
632
dd87eb3a 633/**
24b26d42 634 * handle_percpu_irq - Per CPU local irq handler
dd87eb3a
TG
635 * @irq: the interrupt number
636 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
637 *
638 * Per CPU interrupts on SMP machines without locking requirements
639 */
7ad5b3a5 640void
7d12e780 641handle_percpu_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 642{
35e857cb 643 struct irq_chip *chip = irq_desc_get_chip(desc);
dd87eb3a 644
d6c88a50 645 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 646
849f061c
TG
647 if (chip->irq_ack)
648 chip->irq_ack(&desc->irq_data);
dd87eb3a 649
849f061c 650 handle_irq_event_percpu(desc, desc->action);
dd87eb3a 651
849f061c
TG
652 if (chip->irq_eoi)
653 chip->irq_eoi(&desc->irq_data);
dd87eb3a
TG
654}
655
31d9d9b6
MZ
656/**
657 * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
658 * @irq: the interrupt number
659 * @desc: the interrupt description structure for this irq
660 *
661 * Per CPU interrupts on SMP machines without locking requirements. Same as
662 * handle_percpu_irq() above but with the following extras:
663 *
664 * action->percpu_dev_id is a pointer to percpu variables which
665 * contain the real device id for the cpu on which this handler is
666 * called
667 */
668void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc)
669{
670 struct irq_chip *chip = irq_desc_get_chip(desc);
671 struct irqaction *action = desc->action;
672 void *dev_id = __this_cpu_ptr(action->percpu_dev_id);
673 irqreturn_t res;
674
675 kstat_incr_irqs_this_cpu(irq, desc);
676
677 if (chip->irq_ack)
678 chip->irq_ack(&desc->irq_data);
679
680 trace_irq_handler_entry(irq, action);
681 res = action->handler(irq, dev_id);
682 trace_irq_handler_exit(irq, action, res);
683
684 if (chip->irq_eoi)
685 chip->irq_eoi(&desc->irq_data);
686}
687
dd87eb3a 688void
3836ca08 689__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
a460e745 690 const char *name)
dd87eb3a 691{
dd87eb3a 692 unsigned long flags;
31d9d9b6 693 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
dd87eb3a 694
02725e74 695 if (!desc)
dd87eb3a 696 return;
dd87eb3a 697
091738a2 698 if (!handle) {
dd87eb3a 699 handle = handle_bad_irq;
091738a2
TG
700 } else {
701 if (WARN_ON(desc->irq_data.chip == &no_irq_chip))
02725e74 702 goto out;
f8b5473f 703 }
dd87eb3a 704
dd87eb3a
TG
705 /* Uninstall? */
706 if (handle == handle_bad_irq) {
6b8ff312 707 if (desc->irq_data.chip != &no_irq_chip)
9205e31d 708 mask_ack_irq(desc);
801a0e9a 709 irq_state_set_disabled(desc);
dd87eb3a
TG
710 desc->depth = 1;
711 }
712 desc->handle_irq = handle;
a460e745 713 desc->name = name;
dd87eb3a
TG
714
715 if (handle != handle_bad_irq && is_chained) {
1ccb4e61
TG
716 irq_settings_set_noprobe(desc);
717 irq_settings_set_norequest(desc);
7f1b1244 718 irq_settings_set_nothread(desc);
b4bc724e 719 irq_startup(desc, true);
dd87eb3a 720 }
02725e74
TG
721out:
722 irq_put_desc_busunlock(desc, flags);
dd87eb3a 723}
3836ca08 724EXPORT_SYMBOL_GPL(__irq_set_handler);
dd87eb3a
TG
725
726void
3836ca08 727irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
a460e745 728 irq_flow_handler_t handle, const char *name)
dd87eb3a 729{
35e857cb 730 irq_set_chip(irq, chip);
3836ca08 731 __irq_set_handler(irq, handle, 0, name);
dd87eb3a 732}
b3ae66f2 733EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name);
46f4f8f6 734
44247184 735void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
46f4f8f6 736{
46f4f8f6 737 unsigned long flags;
31d9d9b6 738 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
46f4f8f6 739
44247184 740 if (!desc)
46f4f8f6 741 return;
a005677b
TG
742 irq_settings_clr_and_set(desc, clr, set);
743
876dbd4c 744 irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
e1ef8241 745 IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
a005677b
TG
746 if (irq_settings_has_no_balance_set(desc))
747 irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
748 if (irq_settings_is_per_cpu(desc))
749 irqd_set(&desc->irq_data, IRQD_PER_CPU);
e1ef8241
TG
750 if (irq_settings_can_move_pcntxt(desc))
751 irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
0ef5ca1e
TG
752 if (irq_settings_is_level(desc))
753 irqd_set(&desc->irq_data, IRQD_LEVEL);
a005677b 754
876dbd4c
TG
755 irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc));
756
02725e74 757 irq_put_desc_unlock(desc, flags);
46f4f8f6 758}
edf76f83 759EXPORT_SYMBOL_GPL(irq_modify_status);
0fdb4b25
DD
760
761/**
762 * irq_cpu_online - Invoke all irq_cpu_online functions.
763 *
764 * Iterate through all irqs and invoke the chip.irq_cpu_online()
765 * for each.
766 */
767void irq_cpu_online(void)
768{
769 struct irq_desc *desc;
770 struct irq_chip *chip;
771 unsigned long flags;
772 unsigned int irq;
773
774 for_each_active_irq(irq) {
775 desc = irq_to_desc(irq);
776 if (!desc)
777 continue;
778
779 raw_spin_lock_irqsave(&desc->lock, flags);
780
781 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
782 if (chip && chip->irq_cpu_online &&
783 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 784 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
785 chip->irq_cpu_online(&desc->irq_data);
786
787 raw_spin_unlock_irqrestore(&desc->lock, flags);
788 }
789}
790
791/**
792 * irq_cpu_offline - Invoke all irq_cpu_offline functions.
793 *
794 * Iterate through all irqs and invoke the chip.irq_cpu_offline()
795 * for each.
796 */
797void irq_cpu_offline(void)
798{
799 struct irq_desc *desc;
800 struct irq_chip *chip;
801 unsigned long flags;
802 unsigned int irq;
803
804 for_each_active_irq(irq) {
805 desc = irq_to_desc(irq);
806 if (!desc)
807 continue;
808
809 raw_spin_lock_irqsave(&desc->lock, flags);
810
811 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
812 if (chip && chip->irq_cpu_offline &&
813 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 814 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
815 chip->irq_cpu_offline(&desc->irq_data);
816
817 raw_spin_unlock_irqrestore(&desc->lock, flags);
818 }
819}