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Commit | Line | Data |
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dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
18 | ||
19 | #include "internals.h" | |
20 | ||
21 | /** | |
a0cd9ca2 | 22 | * irq_set_chip - set the irq chip for an irq |
dd87eb3a TG |
23 | * @irq: irq number |
24 | * @chip: pointer to irq chip description structure | |
25 | */ | |
a0cd9ca2 | 26 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) |
dd87eb3a | 27 | { |
d3c60047 | 28 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
29 | unsigned long flags; |
30 | ||
7d94f7ca | 31 | if (!desc) { |
261c40c1 | 32 | WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq); |
dd87eb3a TG |
33 | return -EINVAL; |
34 | } | |
35 | ||
36 | if (!chip) | |
37 | chip = &no_irq_chip; | |
38 | ||
239007b8 | 39 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a | 40 | irq_chip_set_defaults(chip); |
6b8ff312 | 41 | desc->irq_data.chip = chip; |
239007b8 | 42 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
43 | |
44 | return 0; | |
45 | } | |
a0cd9ca2 | 46 | EXPORT_SYMBOL(irq_set_chip); |
dd87eb3a TG |
47 | |
48 | /** | |
a0cd9ca2 | 49 | * irq_set_type - set the irq trigger type for an irq |
dd87eb3a | 50 | * @irq: irq number |
0c5d1eb7 | 51 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a | 52 | */ |
a0cd9ca2 | 53 | int irq_set_irq_type(unsigned int irq, unsigned int type) |
dd87eb3a | 54 | { |
d3c60047 | 55 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
56 | unsigned long flags; |
57 | int ret = -ENXIO; | |
58 | ||
7d94f7ca | 59 | if (!desc) { |
dd87eb3a TG |
60 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); |
61 | return -ENODEV; | |
62 | } | |
63 | ||
f2b662da | 64 | type &= IRQ_TYPE_SENSE_MASK; |
0c5d1eb7 DB |
65 | if (type == IRQ_TYPE_NONE) |
66 | return 0; | |
67 | ||
43abe43c | 68 | chip_bus_lock(desc); |
239007b8 | 69 | raw_spin_lock_irqsave(&desc->lock, flags); |
0b3682ba | 70 | ret = __irq_set_trigger(desc, irq, type); |
239007b8 | 71 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
43abe43c | 72 | chip_bus_sync_unlock(desc); |
dd87eb3a TG |
73 | return ret; |
74 | } | |
a0cd9ca2 | 75 | EXPORT_SYMBOL(irq_set_irq_type); |
dd87eb3a TG |
76 | |
77 | /** | |
a0cd9ca2 | 78 | * irq_set_handler_data - set irq handler data for an irq |
dd87eb3a TG |
79 | * @irq: Interrupt number |
80 | * @data: Pointer to interrupt specific data | |
81 | * | |
82 | * Set the hardware irq controller data for an irq | |
83 | */ | |
a0cd9ca2 | 84 | int irq_set_handler_data(unsigned int irq, void *data) |
dd87eb3a | 85 | { |
d3c60047 | 86 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
87 | unsigned long flags; |
88 | ||
7d94f7ca | 89 | if (!desc) { |
dd87eb3a TG |
90 | printk(KERN_ERR |
91 | "Trying to install controller data for IRQ%d\n", irq); | |
92 | return -EINVAL; | |
93 | } | |
94 | ||
239007b8 | 95 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 96 | desc->irq_data.handler_data = data; |
239007b8 | 97 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
98 | return 0; |
99 | } | |
a0cd9ca2 | 100 | EXPORT_SYMBOL(irq_set_handler_data); |
dd87eb3a | 101 | |
5b912c10 | 102 | /** |
a0cd9ca2 | 103 | * irq_set_msi_desc - set MSI descriptor data for an irq |
5b912c10 | 104 | * @irq: Interrupt number |
472900b8 | 105 | * @entry: Pointer to MSI descriptor data |
5b912c10 | 106 | * |
24b26d42 | 107 | * Set the MSI descriptor entry for an irq |
5b912c10 | 108 | */ |
a0cd9ca2 | 109 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) |
5b912c10 | 110 | { |
d3c60047 | 111 | struct irq_desc *desc = irq_to_desc(irq); |
5b912c10 EB |
112 | unsigned long flags; |
113 | ||
7d94f7ca | 114 | if (!desc) { |
5b912c10 EB |
115 | printk(KERN_ERR |
116 | "Trying to install msi data for IRQ%d\n", irq); | |
117 | return -EINVAL; | |
118 | } | |
7d94f7ca | 119 | |
239007b8 | 120 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 121 | desc->irq_data.msi_desc = entry; |
7fe3730d ME |
122 | if (entry) |
123 | entry->irq = irq; | |
239007b8 | 124 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
5b912c10 EB |
125 | return 0; |
126 | } | |
127 | ||
dd87eb3a | 128 | /** |
a0cd9ca2 | 129 | * irq_set_chip_data - set irq chip data for an irq |
dd87eb3a TG |
130 | * @irq: Interrupt number |
131 | * @data: Pointer to chip specific data | |
132 | * | |
133 | * Set the hardware irq chip data for an irq | |
134 | */ | |
a0cd9ca2 | 135 | int irq_set_chip_data(unsigned int irq, void *data) |
dd87eb3a | 136 | { |
d3c60047 | 137 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
138 | unsigned long flags; |
139 | ||
7d94f7ca YL |
140 | if (!desc) { |
141 | printk(KERN_ERR | |
142 | "Trying to install chip data for IRQ%d\n", irq); | |
143 | return -EINVAL; | |
144 | } | |
145 | ||
6b8ff312 | 146 | if (!desc->irq_data.chip) { |
dd87eb3a TG |
147 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); |
148 | return -EINVAL; | |
149 | } | |
150 | ||
239007b8 | 151 | raw_spin_lock_irqsave(&desc->lock, flags); |
6b8ff312 | 152 | desc->irq_data.chip_data = data; |
239007b8 | 153 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
154 | |
155 | return 0; | |
156 | } | |
a0cd9ca2 | 157 | EXPORT_SYMBOL(irq_set_chip_data); |
dd87eb3a | 158 | |
f303a6dd TG |
159 | struct irq_data *irq_get_irq_data(unsigned int irq) |
160 | { | |
161 | struct irq_desc *desc = irq_to_desc(irq); | |
162 | ||
163 | return desc ? &desc->irq_data : NULL; | |
164 | } | |
165 | EXPORT_SYMBOL_GPL(irq_get_irq_data); | |
166 | ||
399b5da2 TG |
167 | /** |
168 | * set_irq_nested_thread - Set/Reset the IRQ_NESTED_THREAD flag of an irq | |
169 | * | |
170 | * @irq: Interrupt number | |
171 | * @nest: 0 to clear / 1 to set the IRQ_NESTED_THREAD flag | |
172 | * | |
173 | * The IRQ_NESTED_THREAD flag indicates that on | |
174 | * request_threaded_irq() no separate interrupt thread should be | |
175 | * created for the irq as the handler are called nested in the | |
176 | * context of a demultiplexing interrupt handler thread. | |
177 | */ | |
178 | void set_irq_nested_thread(unsigned int irq, int nest) | |
179 | { | |
180 | struct irq_desc *desc = irq_to_desc(irq); | |
181 | unsigned long flags; | |
182 | ||
183 | if (!desc) | |
184 | return; | |
185 | ||
239007b8 | 186 | raw_spin_lock_irqsave(&desc->lock, flags); |
399b5da2 TG |
187 | if (nest) |
188 | desc->status |= IRQ_NESTED_THREAD; | |
189 | else | |
190 | desc->status &= ~IRQ_NESTED_THREAD; | |
239007b8 | 191 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
399b5da2 TG |
192 | } |
193 | EXPORT_SYMBOL_GPL(set_irq_nested_thread); | |
194 | ||
46999238 TG |
195 | int irq_startup(struct irq_desc *desc) |
196 | { | |
197 | desc->status &= ~(IRQ_MASKED | IRQ_DISABLED); | |
198 | desc->depth = 0; | |
199 | ||
200 | if (desc->irq_data.chip->irq_startup) | |
201 | return desc->irq_data.chip->irq_startup(&desc->irq_data); | |
202 | ||
87923470 | 203 | irq_enable(desc); |
46999238 TG |
204 | return 0; |
205 | } | |
206 | ||
207 | void irq_shutdown(struct irq_desc *desc) | |
208 | { | |
209 | desc->status |= IRQ_MASKED | IRQ_DISABLED; | |
210 | desc->depth = 1; | |
211 | desc->irq_data.chip->irq_shutdown(&desc->irq_data); | |
212 | } | |
213 | ||
87923470 TG |
214 | void irq_enable(struct irq_desc *desc) |
215 | { | |
216 | desc->irq_data.chip->irq_enable(&desc->irq_data); | |
217 | } | |
218 | ||
219 | void irq_disable(struct irq_desc *desc) | |
220 | { | |
221 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
222 | } | |
223 | ||
dd87eb3a TG |
224 | /* |
225 | * default enable function | |
226 | */ | |
c5f75634 | 227 | static void default_enable(struct irq_data *data) |
dd87eb3a | 228 | { |
c5f75634 | 229 | struct irq_desc *desc = irq_data_to_desc(data); |
dd87eb3a | 230 | |
0eda58b7 | 231 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
dd87eb3a TG |
232 | desc->status &= ~IRQ_MASKED; |
233 | } | |
234 | ||
235 | /* | |
236 | * default disable function | |
237 | */ | |
bc310dda | 238 | static void default_disable(struct irq_data *data) |
dd87eb3a | 239 | { |
dd87eb3a TG |
240 | } |
241 | ||
89d694b9 TG |
242 | /* |
243 | * default shutdown function | |
244 | */ | |
bc310dda | 245 | static void default_shutdown(struct irq_data *data) |
89d694b9 | 246 | { |
bc310dda | 247 | struct irq_desc *desc = irq_data_to_desc(data); |
89d694b9 | 248 | |
e2c0f8ff | 249 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
89d694b9 TG |
250 | } |
251 | ||
bd151412 | 252 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
3876ec9e | 253 | /* Temporary migration helpers */ |
e2c0f8ff TG |
254 | static void compat_irq_mask(struct irq_data *data) |
255 | { | |
256 | data->chip->mask(data->irq); | |
257 | } | |
258 | ||
0eda58b7 TG |
259 | static void compat_irq_unmask(struct irq_data *data) |
260 | { | |
261 | data->chip->unmask(data->irq); | |
262 | } | |
263 | ||
22a49163 TG |
264 | static void compat_irq_ack(struct irq_data *data) |
265 | { | |
266 | data->chip->ack(data->irq); | |
267 | } | |
268 | ||
9205e31d TG |
269 | static void compat_irq_mask_ack(struct irq_data *data) |
270 | { | |
271 | data->chip->mask_ack(data->irq); | |
272 | } | |
273 | ||
0c5c1557 TG |
274 | static void compat_irq_eoi(struct irq_data *data) |
275 | { | |
276 | data->chip->eoi(data->irq); | |
277 | } | |
278 | ||
c5f75634 TG |
279 | static void compat_irq_enable(struct irq_data *data) |
280 | { | |
281 | data->chip->enable(data->irq); | |
282 | } | |
283 | ||
bc310dda TG |
284 | static void compat_irq_disable(struct irq_data *data) |
285 | { | |
286 | data->chip->disable(data->irq); | |
287 | } | |
288 | ||
289 | static void compat_irq_shutdown(struct irq_data *data) | |
290 | { | |
291 | data->chip->shutdown(data->irq); | |
292 | } | |
293 | ||
37e12df7 TG |
294 | static unsigned int compat_irq_startup(struct irq_data *data) |
295 | { | |
296 | return data->chip->startup(data->irq); | |
297 | } | |
298 | ||
c96b3b3c TG |
299 | static int compat_irq_set_affinity(struct irq_data *data, |
300 | const struct cpumask *dest, bool force) | |
301 | { | |
302 | return data->chip->set_affinity(data->irq, dest); | |
303 | } | |
304 | ||
b2ba2c30 TG |
305 | static int compat_irq_set_type(struct irq_data *data, unsigned int type) |
306 | { | |
307 | return data->chip->set_type(data->irq, type); | |
308 | } | |
309 | ||
2f7e99bb TG |
310 | static int compat_irq_set_wake(struct irq_data *data, unsigned int on) |
311 | { | |
312 | return data->chip->set_wake(data->irq, on); | |
313 | } | |
314 | ||
21e2b8c6 TG |
315 | static int compat_irq_retrigger(struct irq_data *data) |
316 | { | |
317 | return data->chip->retrigger(data->irq); | |
318 | } | |
319 | ||
3876ec9e TG |
320 | static void compat_bus_lock(struct irq_data *data) |
321 | { | |
322 | data->chip->bus_lock(data->irq); | |
323 | } | |
324 | ||
325 | static void compat_bus_sync_unlock(struct irq_data *data) | |
326 | { | |
327 | data->chip->bus_sync_unlock(data->irq); | |
328 | } | |
bd151412 | 329 | #endif |
3876ec9e | 330 | |
dd87eb3a TG |
331 | /* |
332 | * Fixup enable/disable function pointers | |
333 | */ | |
334 | void irq_chip_set_defaults(struct irq_chip *chip) | |
335 | { | |
bd151412 | 336 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
c5f75634 TG |
337 | /* |
338 | * Compat fixup functions need to be before we set the | |
339 | * defaults for enable/disable/startup/shutdown | |
340 | */ | |
341 | if (chip->enable) | |
342 | chip->irq_enable = compat_irq_enable; | |
bc310dda TG |
343 | if (chip->disable) |
344 | chip->irq_disable = compat_irq_disable; | |
345 | if (chip->shutdown) | |
346 | chip->irq_shutdown = compat_irq_shutdown; | |
37e12df7 TG |
347 | if (chip->startup) |
348 | chip->irq_startup = compat_irq_startup; | |
bd151412 | 349 | #endif |
c5f75634 TG |
350 | /* |
351 | * The real defaults | |
352 | */ | |
353 | if (!chip->irq_enable) | |
354 | chip->irq_enable = default_enable; | |
bc310dda TG |
355 | if (!chip->irq_disable) |
356 | chip->irq_disable = default_disable; | |
89d694b9 | 357 | /* |
bc310dda TG |
358 | * We use chip->irq_disable, when the user provided its own. When |
359 | * we have default_disable set for chip->irq_disable, then we need | |
89d694b9 TG |
360 | * to use default_shutdown, otherwise the irq line is not |
361 | * disabled on free_irq(): | |
362 | */ | |
bc310dda TG |
363 | if (!chip->irq_shutdown) |
364 | chip->irq_shutdown = chip->irq_disable != default_disable ? | |
365 | chip->irq_disable : default_shutdown; | |
bd151412 TG |
366 | |
367 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED | |
b86432b4 ZY |
368 | if (!chip->end) |
369 | chip->end = dummy_irq_chip.end; | |
3876ec9e | 370 | |
bc310dda TG |
371 | /* |
372 | * Now fix up the remaining compat handlers | |
373 | */ | |
3876ec9e TG |
374 | if (chip->bus_lock) |
375 | chip->irq_bus_lock = compat_bus_lock; | |
376 | if (chip->bus_sync_unlock) | |
377 | chip->irq_bus_sync_unlock = compat_bus_sync_unlock; | |
e2c0f8ff TG |
378 | if (chip->mask) |
379 | chip->irq_mask = compat_irq_mask; | |
0eda58b7 TG |
380 | if (chip->unmask) |
381 | chip->irq_unmask = compat_irq_unmask; | |
22a49163 TG |
382 | if (chip->ack) |
383 | chip->irq_ack = compat_irq_ack; | |
9205e31d TG |
384 | if (chip->mask_ack) |
385 | chip->irq_mask_ack = compat_irq_mask_ack; | |
0c5c1557 TG |
386 | if (chip->eoi) |
387 | chip->irq_eoi = compat_irq_eoi; | |
c96b3b3c TG |
388 | if (chip->set_affinity) |
389 | chip->irq_set_affinity = compat_irq_set_affinity; | |
b2ba2c30 TG |
390 | if (chip->set_type) |
391 | chip->irq_set_type = compat_irq_set_type; | |
2f7e99bb TG |
392 | if (chip->set_wake) |
393 | chip->irq_set_wake = compat_irq_set_wake; | |
21e2b8c6 TG |
394 | if (chip->retrigger) |
395 | chip->irq_retrigger = compat_irq_retrigger; | |
bd151412 | 396 | #endif |
dd87eb3a TG |
397 | } |
398 | ||
9205e31d | 399 | static inline void mask_ack_irq(struct irq_desc *desc) |
dd87eb3a | 400 | { |
9205e31d TG |
401 | if (desc->irq_data.chip->irq_mask_ack) |
402 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | |
dd87eb3a | 403 | else { |
e2c0f8ff | 404 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
22a49163 TG |
405 | if (desc->irq_data.chip->irq_ack) |
406 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 407 | } |
0b1adaa0 TG |
408 | desc->status |= IRQ_MASKED; |
409 | } | |
410 | ||
e2c0f8ff | 411 | static inline void mask_irq(struct irq_desc *desc) |
0b1adaa0 | 412 | { |
e2c0f8ff TG |
413 | if (desc->irq_data.chip->irq_mask) { |
414 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
0b1adaa0 TG |
415 | desc->status |= IRQ_MASKED; |
416 | } | |
417 | } | |
418 | ||
0eda58b7 | 419 | static inline void unmask_irq(struct irq_desc *desc) |
0b1adaa0 | 420 | { |
0eda58b7 TG |
421 | if (desc->irq_data.chip->irq_unmask) { |
422 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
0b1adaa0 TG |
423 | desc->status &= ~IRQ_MASKED; |
424 | } | |
dd87eb3a TG |
425 | } |
426 | ||
399b5da2 TG |
427 | /* |
428 | * handle_nested_irq - Handle a nested irq from a irq thread | |
429 | * @irq: the interrupt number | |
430 | * | |
431 | * Handle interrupts which are nested into a threaded interrupt | |
432 | * handler. The handler function is called inside the calling | |
433 | * threads context. | |
434 | */ | |
435 | void handle_nested_irq(unsigned int irq) | |
436 | { | |
437 | struct irq_desc *desc = irq_to_desc(irq); | |
438 | struct irqaction *action; | |
439 | irqreturn_t action_ret; | |
440 | ||
441 | might_sleep(); | |
442 | ||
239007b8 | 443 | raw_spin_lock_irq(&desc->lock); |
399b5da2 TG |
444 | |
445 | kstat_incr_irqs_this_cpu(irq, desc); | |
446 | ||
447 | action = desc->action; | |
448 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) | |
449 | goto out_unlock; | |
450 | ||
451 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 452 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
453 | |
454 | action_ret = action->thread_fn(action->irq, action->dev_id); | |
455 | if (!noirqdebug) | |
456 | note_interrupt(irq, desc, action_ret); | |
457 | ||
239007b8 | 458 | raw_spin_lock_irq(&desc->lock); |
399b5da2 TG |
459 | desc->status &= ~IRQ_INPROGRESS; |
460 | ||
461 | out_unlock: | |
239007b8 | 462 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
463 | } |
464 | EXPORT_SYMBOL_GPL(handle_nested_irq); | |
465 | ||
fe200ae4 TG |
466 | static bool irq_check_poll(struct irq_desc *desc) |
467 | { | |
468 | if (!(desc->status & IRQ_POLL_INPROGRESS)) | |
469 | return false; | |
470 | return irq_wait_for_poll(desc); | |
471 | } | |
472 | ||
dd87eb3a TG |
473 | /** |
474 | * handle_simple_irq - Simple and software-decoded IRQs. | |
475 | * @irq: the interrupt number | |
476 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
477 | * |
478 | * Simple interrupts are either sent from a demultiplexing interrupt | |
479 | * handler or come from hardware, where no interrupt hardware control | |
480 | * is necessary. | |
481 | * | |
482 | * Note: The caller is expected to handle the ack, clear, mask and | |
483 | * unmask issues if necessary. | |
484 | */ | |
7ad5b3a5 | 485 | void |
7d12e780 | 486 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
487 | { |
488 | struct irqaction *action; | |
489 | irqreturn_t action_ret; | |
dd87eb3a | 490 | |
239007b8 | 491 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
492 | |
493 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
fe200ae4 TG |
494 | if (!irq_check_poll(desc)) |
495 | goto out_unlock; | |
496 | ||
971e5b35 | 497 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
d6c88a50 | 498 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
499 | |
500 | action = desc->action; | |
971e5b35 | 501 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
dd87eb3a TG |
502 | goto out_unlock; |
503 | ||
504 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 505 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 506 | |
7d12e780 | 507 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 508 | if (!noirqdebug) |
7d12e780 | 509 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 510 | |
239007b8 | 511 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
512 | desc->status &= ~IRQ_INPROGRESS; |
513 | out_unlock: | |
239007b8 | 514 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
515 | } |
516 | ||
517 | /** | |
518 | * handle_level_irq - Level type irq handler | |
519 | * @irq: the interrupt number | |
520 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
521 | * |
522 | * Level type interrupts are active as long as the hardware line has | |
523 | * the active level. This may require to mask the interrupt and unmask | |
524 | * it after the associated handler has acknowledged the device, so the | |
525 | * interrupt line is back to inactive. | |
526 | */ | |
7ad5b3a5 | 527 | void |
7d12e780 | 528 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 529 | { |
dd87eb3a TG |
530 | struct irqaction *action; |
531 | irqreturn_t action_ret; | |
532 | ||
239007b8 | 533 | raw_spin_lock(&desc->lock); |
9205e31d | 534 | mask_ack_irq(desc); |
dd87eb3a TG |
535 | |
536 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
fe200ae4 TG |
537 | if (!irq_check_poll(desc)) |
538 | goto out_unlock; | |
539 | ||
dd87eb3a | 540 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
d6c88a50 | 541 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
542 | |
543 | /* | |
544 | * If its disabled or no action available | |
545 | * keep it masked and get out of here | |
546 | */ | |
547 | action = desc->action; | |
49663421 | 548 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
86998aa6 | 549 | goto out_unlock; |
dd87eb3a TG |
550 | |
551 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 552 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 553 | |
7d12e780 | 554 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 555 | if (!noirqdebug) |
7d12e780 | 556 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 557 | |
239007b8 | 558 | raw_spin_lock(&desc->lock); |
dd87eb3a | 559 | desc->status &= ~IRQ_INPROGRESS; |
b25c340c | 560 | |
0b1adaa0 | 561 | if (!(desc->status & (IRQ_DISABLED | IRQ_ONESHOT))) |
0eda58b7 | 562 | unmask_irq(desc); |
86998aa6 | 563 | out_unlock: |
239007b8 | 564 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 565 | } |
14819ea1 | 566 | EXPORT_SYMBOL_GPL(handle_level_irq); |
dd87eb3a TG |
567 | |
568 | /** | |
47c2a3aa | 569 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
570 | * @irq: the interrupt number |
571 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 572 | * |
47c2a3aa | 573 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
574 | * call when the interrupt has been serviced. This enables support |
575 | * for modern forms of interrupt handlers, which handle the flow | |
576 | * details in hardware, transparently. | |
577 | */ | |
7ad5b3a5 | 578 | void |
7d12e780 | 579 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 580 | { |
dd87eb3a TG |
581 | struct irqaction *action; |
582 | irqreturn_t action_ret; | |
583 | ||
239007b8 | 584 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
585 | |
586 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
fe200ae4 TG |
587 | if (!irq_check_poll(desc)) |
588 | goto out; | |
dd87eb3a TG |
589 | |
590 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
d6c88a50 | 591 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
592 | |
593 | /* | |
594 | * If its disabled or no action available | |
76d21601 | 595 | * then mask it and get out of here: |
dd87eb3a TG |
596 | */ |
597 | action = desc->action; | |
98bb244b BH |
598 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
599 | desc->status |= IRQ_PENDING; | |
e2c0f8ff | 600 | mask_irq(desc); |
dd87eb3a | 601 | goto out; |
98bb244b | 602 | } |
dd87eb3a TG |
603 | |
604 | desc->status |= IRQ_INPROGRESS; | |
98bb244b | 605 | desc->status &= ~IRQ_PENDING; |
239007b8 | 606 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 607 | |
7d12e780 | 608 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 609 | if (!noirqdebug) |
7d12e780 | 610 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 611 | |
239007b8 | 612 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
613 | desc->status &= ~IRQ_INPROGRESS; |
614 | out: | |
0c5c1557 | 615 | desc->irq_data.chip->irq_eoi(&desc->irq_data); |
dd87eb3a | 616 | |
239007b8 | 617 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
618 | } |
619 | ||
620 | /** | |
621 | * handle_edge_irq - edge type IRQ handler | |
622 | * @irq: the interrupt number | |
623 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
624 | * |
625 | * Interrupt occures on the falling and/or rising edge of a hardware | |
626 | * signal. The occurence is latched into the irq controller hardware | |
627 | * and must be acked in order to be reenabled. After the ack another | |
628 | * interrupt can happen on the same source even before the first one | |
dfff0615 | 629 | * is handled by the associated event handler. If this happens it |
dd87eb3a TG |
630 | * might be necessary to disable (mask) the interrupt depending on the |
631 | * controller hardware. This requires to reenable the interrupt inside | |
632 | * of the loop which handles the interrupts which have arrived while | |
633 | * the handler was running. If all pending interrupts are handled, the | |
634 | * loop is left. | |
635 | */ | |
7ad5b3a5 | 636 | void |
7d12e780 | 637 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 638 | { |
239007b8 | 639 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
640 | |
641 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
642 | ||
643 | /* | |
644 | * If we're currently running this IRQ, or its disabled, | |
645 | * we shouldn't process the IRQ. Mark it pending, handle | |
646 | * the necessary masking and go out | |
647 | */ | |
648 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || | |
649 | !desc->action)) { | |
fe200ae4 TG |
650 | if (!irq_check_poll(desc)) { |
651 | desc->status |= (IRQ_PENDING | IRQ_MASKED); | |
652 | mask_ack_irq(desc); | |
653 | goto out_unlock; | |
654 | } | |
dd87eb3a | 655 | } |
d6c88a50 | 656 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
657 | |
658 | /* Start handling the irq */ | |
22a49163 | 659 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
dd87eb3a TG |
660 | |
661 | /* Mark the IRQ currently in progress.*/ | |
662 | desc->status |= IRQ_INPROGRESS; | |
663 | ||
664 | do { | |
665 | struct irqaction *action = desc->action; | |
666 | irqreturn_t action_ret; | |
667 | ||
668 | if (unlikely(!action)) { | |
e2c0f8ff | 669 | mask_irq(desc); |
dd87eb3a TG |
670 | goto out_unlock; |
671 | } | |
672 | ||
673 | /* | |
674 | * When another irq arrived while we were handling | |
675 | * one, we could have masked the irq. | |
676 | * Renable it, if it was not disabled in meantime. | |
677 | */ | |
678 | if (unlikely((desc->status & | |
679 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == | |
680 | (IRQ_PENDING | IRQ_MASKED))) { | |
0eda58b7 | 681 | unmask_irq(desc); |
dd87eb3a TG |
682 | } |
683 | ||
684 | desc->status &= ~IRQ_PENDING; | |
239007b8 | 685 | raw_spin_unlock(&desc->lock); |
7d12e780 | 686 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 687 | if (!noirqdebug) |
7d12e780 | 688 | note_interrupt(irq, desc, action_ret); |
239007b8 | 689 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
690 | |
691 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); | |
692 | ||
693 | desc->status &= ~IRQ_INPROGRESS; | |
694 | out_unlock: | |
239007b8 | 695 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
696 | } |
697 | ||
dd87eb3a | 698 | /** |
24b26d42 | 699 | * handle_percpu_irq - Per CPU local irq handler |
dd87eb3a TG |
700 | * @irq: the interrupt number |
701 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
702 | * |
703 | * Per CPU interrupts on SMP machines without locking requirements | |
704 | */ | |
7ad5b3a5 | 705 | void |
7d12e780 | 706 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
707 | { |
708 | irqreturn_t action_ret; | |
709 | ||
d6c88a50 | 710 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a | 711 | |
22a49163 TG |
712 | if (desc->irq_data.chip->irq_ack) |
713 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 714 | |
7d12e780 | 715 | action_ret = handle_IRQ_event(irq, desc->action); |
dd87eb3a | 716 | if (!noirqdebug) |
7d12e780 | 717 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 718 | |
0c5c1557 TG |
719 | if (desc->irq_data.chip->irq_eoi) |
720 | desc->irq_data.chip->irq_eoi(&desc->irq_data); | |
dd87eb3a TG |
721 | } |
722 | ||
dd87eb3a | 723 | void |
a460e745 IM |
724 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
725 | const char *name) | |
dd87eb3a | 726 | { |
d3c60047 | 727 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
728 | unsigned long flags; |
729 | ||
7d94f7ca | 730 | if (!desc) { |
dd87eb3a TG |
731 | printk(KERN_ERR |
732 | "Trying to install type control for IRQ%d\n", irq); | |
733 | return; | |
734 | } | |
735 | ||
dd87eb3a TG |
736 | if (!handle) |
737 | handle = handle_bad_irq; | |
6b8ff312 | 738 | else if (desc->irq_data.chip == &no_irq_chip) { |
f8b5473f | 739 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
b039db8e | 740 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
f8b5473f TG |
741 | /* |
742 | * Some ARM implementations install a handler for really dumb | |
743 | * interrupt hardware without setting an irq_chip. This worked | |
744 | * with the ARM no_irq_chip but the check in setup_irq would | |
745 | * prevent us to setup the interrupt at all. Switch it to | |
746 | * dummy_irq_chip for easy transition. | |
747 | */ | |
6b8ff312 | 748 | desc->irq_data.chip = &dummy_irq_chip; |
f8b5473f | 749 | } |
dd87eb3a | 750 | |
3876ec9e | 751 | chip_bus_lock(desc); |
239007b8 | 752 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a TG |
753 | |
754 | /* Uninstall? */ | |
755 | if (handle == handle_bad_irq) { | |
6b8ff312 | 756 | if (desc->irq_data.chip != &no_irq_chip) |
9205e31d | 757 | mask_ack_irq(desc); |
dd87eb3a TG |
758 | desc->status |= IRQ_DISABLED; |
759 | desc->depth = 1; | |
760 | } | |
761 | desc->handle_irq = handle; | |
a460e745 | 762 | desc->name = name; |
dd87eb3a TG |
763 | |
764 | if (handle != handle_bad_irq && is_chained) { | |
dd87eb3a | 765 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; |
46999238 | 766 | irq_startup(desc); |
dd87eb3a | 767 | } |
239007b8 | 768 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3876ec9e | 769 | chip_bus_sync_unlock(desc); |
dd87eb3a | 770 | } |
14819ea1 | 771 | EXPORT_SYMBOL_GPL(__set_irq_handler); |
dd87eb3a TG |
772 | |
773 | void | |
774 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
57a58a94 | 775 | irq_flow_handler_t handle) |
dd87eb3a TG |
776 | { |
777 | set_irq_chip(irq, chip); | |
a460e745 | 778 | __set_irq_handler(irq, handle, 0, NULL); |
dd87eb3a TG |
779 | } |
780 | ||
a460e745 IM |
781 | void |
782 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | |
783 | irq_flow_handler_t handle, const char *name) | |
dd87eb3a | 784 | { |
a460e745 IM |
785 | set_irq_chip(irq, chip); |
786 | __set_irq_handler(irq, handle, 0, name); | |
dd87eb3a | 787 | } |
46f4f8f6 | 788 | |
44247184 | 789 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
46f4f8f6 | 790 | { |
d3c60047 | 791 | struct irq_desc *desc = irq_to_desc(irq); |
46f4f8f6 RB |
792 | unsigned long flags; |
793 | ||
44247184 | 794 | if (!desc) |
46f4f8f6 | 795 | return; |
46f4f8f6 | 796 | |
44247184 TG |
797 | /* Sanitize flags */ |
798 | set &= IRQF_MODIFY_MASK; | |
799 | clr &= IRQF_MODIFY_MASK; | |
46f4f8f6 | 800 | |
239007b8 | 801 | raw_spin_lock_irqsave(&desc->lock, flags); |
44247184 TG |
802 | desc->status &= ~clr; |
803 | desc->status |= set; | |
239007b8 | 804 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
46f4f8f6 | 805 | } |