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Commit | Line | Data |
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dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
18 | ||
19 | #include "internals.h" | |
20 | ||
21 | /** | |
a0cd9ca2 | 22 | * irq_set_chip - set the irq chip for an irq |
dd87eb3a TG |
23 | * @irq: irq number |
24 | * @chip: pointer to irq chip description structure | |
25 | */ | |
a0cd9ca2 | 26 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) |
dd87eb3a | 27 | { |
dd87eb3a | 28 | unsigned long flags; |
02725e74 | 29 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); |
dd87eb3a | 30 | |
02725e74 | 31 | if (!desc) |
dd87eb3a | 32 | return -EINVAL; |
dd87eb3a TG |
33 | |
34 | if (!chip) | |
35 | chip = &no_irq_chip; | |
36 | ||
dd87eb3a | 37 | irq_chip_set_defaults(chip); |
6b8ff312 | 38 | desc->irq_data.chip = chip; |
02725e74 | 39 | irq_put_desc_unlock(desc, flags); |
d72274e5 DD |
40 | /* |
41 | * For !CONFIG_SPARSE_IRQ make the irq show up in | |
42 | * allocated_irqs. For the CONFIG_SPARSE_IRQ case, it is | |
43 | * already marked, and this call is harmless. | |
44 | */ | |
45 | irq_reserve_irq(irq); | |
dd87eb3a TG |
46 | return 0; |
47 | } | |
a0cd9ca2 | 48 | EXPORT_SYMBOL(irq_set_chip); |
dd87eb3a TG |
49 | |
50 | /** | |
a0cd9ca2 | 51 | * irq_set_type - set the irq trigger type for an irq |
dd87eb3a | 52 | * @irq: irq number |
0c5d1eb7 | 53 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a | 54 | */ |
a0cd9ca2 | 55 | int irq_set_irq_type(unsigned int irq, unsigned int type) |
dd87eb3a | 56 | { |
dd87eb3a | 57 | unsigned long flags; |
02725e74 TG |
58 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags); |
59 | int ret = 0; | |
dd87eb3a | 60 | |
02725e74 TG |
61 | if (!desc) |
62 | return -EINVAL; | |
dd87eb3a | 63 | |
f2b662da | 64 | type &= IRQ_TYPE_SENSE_MASK; |
02725e74 TG |
65 | if (type != IRQ_TYPE_NONE) |
66 | ret = __irq_set_trigger(desc, irq, type); | |
67 | irq_put_desc_busunlock(desc, flags); | |
dd87eb3a TG |
68 | return ret; |
69 | } | |
a0cd9ca2 | 70 | EXPORT_SYMBOL(irq_set_irq_type); |
dd87eb3a TG |
71 | |
72 | /** | |
a0cd9ca2 | 73 | * irq_set_handler_data - set irq handler data for an irq |
dd87eb3a TG |
74 | * @irq: Interrupt number |
75 | * @data: Pointer to interrupt specific data | |
76 | * | |
77 | * Set the hardware irq controller data for an irq | |
78 | */ | |
a0cd9ca2 | 79 | int irq_set_handler_data(unsigned int irq, void *data) |
dd87eb3a | 80 | { |
dd87eb3a | 81 | unsigned long flags; |
02725e74 | 82 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); |
dd87eb3a | 83 | |
02725e74 | 84 | if (!desc) |
dd87eb3a | 85 | return -EINVAL; |
6b8ff312 | 86 | desc->irq_data.handler_data = data; |
02725e74 | 87 | irq_put_desc_unlock(desc, flags); |
dd87eb3a TG |
88 | return 0; |
89 | } | |
a0cd9ca2 | 90 | EXPORT_SYMBOL(irq_set_handler_data); |
dd87eb3a | 91 | |
5b912c10 | 92 | /** |
a0cd9ca2 | 93 | * irq_set_msi_desc - set MSI descriptor data for an irq |
5b912c10 | 94 | * @irq: Interrupt number |
472900b8 | 95 | * @entry: Pointer to MSI descriptor data |
5b912c10 | 96 | * |
24b26d42 | 97 | * Set the MSI descriptor entry for an irq |
5b912c10 | 98 | */ |
a0cd9ca2 | 99 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) |
5b912c10 | 100 | { |
5b912c10 | 101 | unsigned long flags; |
02725e74 | 102 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); |
5b912c10 | 103 | |
02725e74 | 104 | if (!desc) |
5b912c10 | 105 | return -EINVAL; |
6b8ff312 | 106 | desc->irq_data.msi_desc = entry; |
7fe3730d ME |
107 | if (entry) |
108 | entry->irq = irq; | |
02725e74 | 109 | irq_put_desc_unlock(desc, flags); |
5b912c10 EB |
110 | return 0; |
111 | } | |
112 | ||
dd87eb3a | 113 | /** |
a0cd9ca2 | 114 | * irq_set_chip_data - set irq chip data for an irq |
dd87eb3a TG |
115 | * @irq: Interrupt number |
116 | * @data: Pointer to chip specific data | |
117 | * | |
118 | * Set the hardware irq chip data for an irq | |
119 | */ | |
a0cd9ca2 | 120 | int irq_set_chip_data(unsigned int irq, void *data) |
dd87eb3a | 121 | { |
dd87eb3a | 122 | unsigned long flags; |
02725e74 | 123 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); |
dd87eb3a | 124 | |
02725e74 | 125 | if (!desc) |
dd87eb3a | 126 | return -EINVAL; |
6b8ff312 | 127 | desc->irq_data.chip_data = data; |
02725e74 | 128 | irq_put_desc_unlock(desc, flags); |
dd87eb3a TG |
129 | return 0; |
130 | } | |
a0cd9ca2 | 131 | EXPORT_SYMBOL(irq_set_chip_data); |
dd87eb3a | 132 | |
f303a6dd TG |
133 | struct irq_data *irq_get_irq_data(unsigned int irq) |
134 | { | |
135 | struct irq_desc *desc = irq_to_desc(irq); | |
136 | ||
137 | return desc ? &desc->irq_data : NULL; | |
138 | } | |
139 | EXPORT_SYMBOL_GPL(irq_get_irq_data); | |
140 | ||
c1594b77 TG |
141 | static void irq_state_clr_disabled(struct irq_desc *desc) |
142 | { | |
143 | desc->istate &= ~IRQS_DISABLED; | |
144 | irq_compat_clr_disabled(desc); | |
145 | } | |
146 | ||
147 | static void irq_state_set_disabled(struct irq_desc *desc) | |
148 | { | |
149 | desc->istate |= IRQS_DISABLED; | |
150 | irq_compat_set_disabled(desc); | |
151 | } | |
152 | ||
6e40262e TG |
153 | static void irq_state_clr_masked(struct irq_desc *desc) |
154 | { | |
155 | desc->istate &= ~IRQS_MASKED; | |
156 | irq_compat_clr_masked(desc); | |
157 | } | |
158 | ||
159 | static void irq_state_set_masked(struct irq_desc *desc) | |
160 | { | |
161 | desc->istate |= IRQS_MASKED; | |
162 | irq_compat_set_masked(desc); | |
163 | } | |
164 | ||
46999238 TG |
165 | int irq_startup(struct irq_desc *desc) |
166 | { | |
c1594b77 | 167 | irq_state_clr_disabled(desc); |
46999238 TG |
168 | desc->depth = 0; |
169 | ||
3aae994f TG |
170 | if (desc->irq_data.chip->irq_startup) { |
171 | int ret = desc->irq_data.chip->irq_startup(&desc->irq_data); | |
6e40262e | 172 | irq_state_clr_masked(desc); |
3aae994f TG |
173 | return ret; |
174 | } | |
46999238 | 175 | |
87923470 | 176 | irq_enable(desc); |
46999238 TG |
177 | return 0; |
178 | } | |
179 | ||
180 | void irq_shutdown(struct irq_desc *desc) | |
181 | { | |
c1594b77 | 182 | irq_state_set_disabled(desc); |
46999238 | 183 | desc->depth = 1; |
50f7c032 TG |
184 | if (desc->irq_data.chip->irq_shutdown) |
185 | desc->irq_data.chip->irq_shutdown(&desc->irq_data); | |
186 | if (desc->irq_data.chip->irq_disable) | |
187 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
188 | else | |
189 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
6e40262e | 190 | irq_state_set_masked(desc); |
46999238 TG |
191 | } |
192 | ||
87923470 TG |
193 | void irq_enable(struct irq_desc *desc) |
194 | { | |
c1594b77 | 195 | irq_state_clr_disabled(desc); |
50f7c032 TG |
196 | if (desc->irq_data.chip->irq_enable) |
197 | desc->irq_data.chip->irq_enable(&desc->irq_data); | |
198 | else | |
199 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
6e40262e | 200 | irq_state_clr_masked(desc); |
dd87eb3a TG |
201 | } |
202 | ||
50f7c032 | 203 | void irq_disable(struct irq_desc *desc) |
89d694b9 | 204 | { |
c1594b77 | 205 | irq_state_set_disabled(desc); |
50f7c032 TG |
206 | if (desc->irq_data.chip->irq_disable) { |
207 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
a61d8258 | 208 | irq_state_set_masked(desc); |
50f7c032 | 209 | } |
89d694b9 TG |
210 | } |
211 | ||
bd151412 | 212 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
3876ec9e | 213 | /* Temporary migration helpers */ |
e2c0f8ff TG |
214 | static void compat_irq_mask(struct irq_data *data) |
215 | { | |
216 | data->chip->mask(data->irq); | |
217 | } | |
218 | ||
0eda58b7 TG |
219 | static void compat_irq_unmask(struct irq_data *data) |
220 | { | |
221 | data->chip->unmask(data->irq); | |
222 | } | |
223 | ||
22a49163 TG |
224 | static void compat_irq_ack(struct irq_data *data) |
225 | { | |
226 | data->chip->ack(data->irq); | |
227 | } | |
228 | ||
9205e31d TG |
229 | static void compat_irq_mask_ack(struct irq_data *data) |
230 | { | |
231 | data->chip->mask_ack(data->irq); | |
232 | } | |
233 | ||
0c5c1557 TG |
234 | static void compat_irq_eoi(struct irq_data *data) |
235 | { | |
236 | data->chip->eoi(data->irq); | |
237 | } | |
238 | ||
c5f75634 TG |
239 | static void compat_irq_enable(struct irq_data *data) |
240 | { | |
241 | data->chip->enable(data->irq); | |
242 | } | |
243 | ||
bc310dda TG |
244 | static void compat_irq_disable(struct irq_data *data) |
245 | { | |
246 | data->chip->disable(data->irq); | |
247 | } | |
248 | ||
249 | static void compat_irq_shutdown(struct irq_data *data) | |
250 | { | |
251 | data->chip->shutdown(data->irq); | |
252 | } | |
253 | ||
37e12df7 TG |
254 | static unsigned int compat_irq_startup(struct irq_data *data) |
255 | { | |
256 | return data->chip->startup(data->irq); | |
257 | } | |
258 | ||
c96b3b3c TG |
259 | static int compat_irq_set_affinity(struct irq_data *data, |
260 | const struct cpumask *dest, bool force) | |
261 | { | |
262 | return data->chip->set_affinity(data->irq, dest); | |
263 | } | |
264 | ||
b2ba2c30 TG |
265 | static int compat_irq_set_type(struct irq_data *data, unsigned int type) |
266 | { | |
267 | return data->chip->set_type(data->irq, type); | |
268 | } | |
269 | ||
2f7e99bb TG |
270 | static int compat_irq_set_wake(struct irq_data *data, unsigned int on) |
271 | { | |
272 | return data->chip->set_wake(data->irq, on); | |
273 | } | |
274 | ||
21e2b8c6 TG |
275 | static int compat_irq_retrigger(struct irq_data *data) |
276 | { | |
277 | return data->chip->retrigger(data->irq); | |
278 | } | |
279 | ||
3876ec9e TG |
280 | static void compat_bus_lock(struct irq_data *data) |
281 | { | |
282 | data->chip->bus_lock(data->irq); | |
283 | } | |
284 | ||
285 | static void compat_bus_sync_unlock(struct irq_data *data) | |
286 | { | |
287 | data->chip->bus_sync_unlock(data->irq); | |
288 | } | |
bd151412 | 289 | #endif |
3876ec9e | 290 | |
dd87eb3a TG |
291 | /* |
292 | * Fixup enable/disable function pointers | |
293 | */ | |
294 | void irq_chip_set_defaults(struct irq_chip *chip) | |
295 | { | |
bd151412 | 296 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED |
c5f75634 TG |
297 | if (chip->enable) |
298 | chip->irq_enable = compat_irq_enable; | |
bc310dda TG |
299 | if (chip->disable) |
300 | chip->irq_disable = compat_irq_disable; | |
301 | if (chip->shutdown) | |
302 | chip->irq_shutdown = compat_irq_shutdown; | |
37e12df7 TG |
303 | if (chip->startup) |
304 | chip->irq_startup = compat_irq_startup; | |
b86432b4 ZY |
305 | if (!chip->end) |
306 | chip->end = dummy_irq_chip.end; | |
3876ec9e TG |
307 | if (chip->bus_lock) |
308 | chip->irq_bus_lock = compat_bus_lock; | |
309 | if (chip->bus_sync_unlock) | |
310 | chip->irq_bus_sync_unlock = compat_bus_sync_unlock; | |
e2c0f8ff TG |
311 | if (chip->mask) |
312 | chip->irq_mask = compat_irq_mask; | |
0eda58b7 TG |
313 | if (chip->unmask) |
314 | chip->irq_unmask = compat_irq_unmask; | |
22a49163 TG |
315 | if (chip->ack) |
316 | chip->irq_ack = compat_irq_ack; | |
9205e31d TG |
317 | if (chip->mask_ack) |
318 | chip->irq_mask_ack = compat_irq_mask_ack; | |
0c5c1557 TG |
319 | if (chip->eoi) |
320 | chip->irq_eoi = compat_irq_eoi; | |
c96b3b3c TG |
321 | if (chip->set_affinity) |
322 | chip->irq_set_affinity = compat_irq_set_affinity; | |
b2ba2c30 TG |
323 | if (chip->set_type) |
324 | chip->irq_set_type = compat_irq_set_type; | |
2f7e99bb TG |
325 | if (chip->set_wake) |
326 | chip->irq_set_wake = compat_irq_set_wake; | |
21e2b8c6 TG |
327 | if (chip->retrigger) |
328 | chip->irq_retrigger = compat_irq_retrigger; | |
bd151412 | 329 | #endif |
dd87eb3a TG |
330 | } |
331 | ||
9205e31d | 332 | static inline void mask_ack_irq(struct irq_desc *desc) |
dd87eb3a | 333 | { |
9205e31d TG |
334 | if (desc->irq_data.chip->irq_mask_ack) |
335 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | |
dd87eb3a | 336 | else { |
e2c0f8ff | 337 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
22a49163 TG |
338 | if (desc->irq_data.chip->irq_ack) |
339 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 340 | } |
6e40262e | 341 | irq_state_set_masked(desc); |
0b1adaa0 TG |
342 | } |
343 | ||
d4d5e089 | 344 | void mask_irq(struct irq_desc *desc) |
0b1adaa0 | 345 | { |
e2c0f8ff TG |
346 | if (desc->irq_data.chip->irq_mask) { |
347 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
6e40262e | 348 | irq_state_set_masked(desc); |
0b1adaa0 TG |
349 | } |
350 | } | |
351 | ||
d4d5e089 | 352 | void unmask_irq(struct irq_desc *desc) |
0b1adaa0 | 353 | { |
0eda58b7 TG |
354 | if (desc->irq_data.chip->irq_unmask) { |
355 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
6e40262e | 356 | irq_state_clr_masked(desc); |
0b1adaa0 | 357 | } |
dd87eb3a TG |
358 | } |
359 | ||
399b5da2 TG |
360 | /* |
361 | * handle_nested_irq - Handle a nested irq from a irq thread | |
362 | * @irq: the interrupt number | |
363 | * | |
364 | * Handle interrupts which are nested into a threaded interrupt | |
365 | * handler. The handler function is called inside the calling | |
366 | * threads context. | |
367 | */ | |
368 | void handle_nested_irq(unsigned int irq) | |
369 | { | |
370 | struct irq_desc *desc = irq_to_desc(irq); | |
371 | struct irqaction *action; | |
372 | irqreturn_t action_ret; | |
373 | ||
374 | might_sleep(); | |
375 | ||
239007b8 | 376 | raw_spin_lock_irq(&desc->lock); |
399b5da2 TG |
377 | |
378 | kstat_incr_irqs_this_cpu(irq, desc); | |
379 | ||
380 | action = desc->action; | |
c1594b77 | 381 | if (unlikely(!action || (desc->istate & IRQS_DISABLED))) |
399b5da2 TG |
382 | goto out_unlock; |
383 | ||
009b4c3b TG |
384 | irq_compat_set_progress(desc); |
385 | desc->istate |= IRQS_INPROGRESS; | |
239007b8 | 386 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
387 | |
388 | action_ret = action->thread_fn(action->irq, action->dev_id); | |
389 | if (!noirqdebug) | |
390 | note_interrupt(irq, desc, action_ret); | |
391 | ||
239007b8 | 392 | raw_spin_lock_irq(&desc->lock); |
009b4c3b TG |
393 | desc->istate &= ~IRQS_INPROGRESS; |
394 | irq_compat_clr_progress(desc); | |
399b5da2 TG |
395 | |
396 | out_unlock: | |
239007b8 | 397 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
398 | } |
399 | EXPORT_SYMBOL_GPL(handle_nested_irq); | |
400 | ||
fe200ae4 TG |
401 | static bool irq_check_poll(struct irq_desc *desc) |
402 | { | |
6954b75b | 403 | if (!(desc->istate & IRQS_POLL_INPROGRESS)) |
fe200ae4 TG |
404 | return false; |
405 | return irq_wait_for_poll(desc); | |
406 | } | |
407 | ||
dd87eb3a TG |
408 | /** |
409 | * handle_simple_irq - Simple and software-decoded IRQs. | |
410 | * @irq: the interrupt number | |
411 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
412 | * |
413 | * Simple interrupts are either sent from a demultiplexing interrupt | |
414 | * handler or come from hardware, where no interrupt hardware control | |
415 | * is necessary. | |
416 | * | |
417 | * Note: The caller is expected to handle the ack, clear, mask and | |
418 | * unmask issues if necessary. | |
419 | */ | |
7ad5b3a5 | 420 | void |
7d12e780 | 421 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 422 | { |
239007b8 | 423 | raw_spin_lock(&desc->lock); |
dd87eb3a | 424 | |
009b4c3b | 425 | if (unlikely(desc->istate & IRQS_INPROGRESS)) |
fe200ae4 TG |
426 | if (!irq_check_poll(desc)) |
427 | goto out_unlock; | |
428 | ||
163ef309 | 429 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
d6c88a50 | 430 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a | 431 | |
c1594b77 | 432 | if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED))) |
dd87eb3a TG |
433 | goto out_unlock; |
434 | ||
107781e7 | 435 | handle_irq_event(desc); |
dd87eb3a | 436 | |
dd87eb3a | 437 | out_unlock: |
239007b8 | 438 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
439 | } |
440 | ||
441 | /** | |
442 | * handle_level_irq - Level type irq handler | |
443 | * @irq: the interrupt number | |
444 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
445 | * |
446 | * Level type interrupts are active as long as the hardware line has | |
447 | * the active level. This may require to mask the interrupt and unmask | |
448 | * it after the associated handler has acknowledged the device, so the | |
449 | * interrupt line is back to inactive. | |
450 | */ | |
7ad5b3a5 | 451 | void |
7d12e780 | 452 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 453 | { |
239007b8 | 454 | raw_spin_lock(&desc->lock); |
9205e31d | 455 | mask_ack_irq(desc); |
dd87eb3a | 456 | |
009b4c3b | 457 | if (unlikely(desc->istate & IRQS_INPROGRESS)) |
fe200ae4 TG |
458 | if (!irq_check_poll(desc)) |
459 | goto out_unlock; | |
460 | ||
163ef309 | 461 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
d6c88a50 | 462 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
463 | |
464 | /* | |
465 | * If its disabled or no action available | |
466 | * keep it masked and get out of here | |
467 | */ | |
c1594b77 | 468 | if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED))) |
86998aa6 | 469 | goto out_unlock; |
dd87eb3a | 470 | |
1529866c | 471 | handle_irq_event(desc); |
b25c340c | 472 | |
c1594b77 | 473 | if (!(desc->istate & (IRQS_DISABLED | IRQS_ONESHOT))) |
0eda58b7 | 474 | unmask_irq(desc); |
86998aa6 | 475 | out_unlock: |
239007b8 | 476 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 477 | } |
14819ea1 | 478 | EXPORT_SYMBOL_GPL(handle_level_irq); |
dd87eb3a | 479 | |
78129576 TG |
480 | #ifdef CONFIG_IRQ_PREFLOW_FASTEOI |
481 | static inline void preflow_handler(struct irq_desc *desc) | |
482 | { | |
483 | if (desc->preflow_handler) | |
484 | desc->preflow_handler(&desc->irq_data); | |
485 | } | |
486 | #else | |
487 | static inline void preflow_handler(struct irq_desc *desc) { } | |
488 | #endif | |
489 | ||
dd87eb3a | 490 | /** |
47c2a3aa | 491 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
492 | * @irq: the interrupt number |
493 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 494 | * |
47c2a3aa | 495 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
496 | * call when the interrupt has been serviced. This enables support |
497 | * for modern forms of interrupt handlers, which handle the flow | |
498 | * details in hardware, transparently. | |
499 | */ | |
7ad5b3a5 | 500 | void |
7d12e780 | 501 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 502 | { |
239007b8 | 503 | raw_spin_lock(&desc->lock); |
dd87eb3a | 504 | |
009b4c3b | 505 | if (unlikely(desc->istate & IRQS_INPROGRESS)) |
fe200ae4 TG |
506 | if (!irq_check_poll(desc)) |
507 | goto out; | |
dd87eb3a | 508 | |
163ef309 | 509 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
d6c88a50 | 510 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
511 | |
512 | /* | |
513 | * If its disabled or no action available | |
76d21601 | 514 | * then mask it and get out of here: |
dd87eb3a | 515 | */ |
c1594b77 | 516 | if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED))) { |
2a0d6fb3 TG |
517 | irq_compat_set_pending(desc); |
518 | desc->istate |= IRQS_PENDING; | |
e2c0f8ff | 519 | mask_irq(desc); |
dd87eb3a | 520 | goto out; |
98bb244b | 521 | } |
c69e3758 TG |
522 | |
523 | if (desc->istate & IRQS_ONESHOT) | |
524 | mask_irq(desc); | |
525 | ||
78129576 | 526 | preflow_handler(desc); |
a7ae4de5 | 527 | handle_irq_event(desc); |
77694b40 TG |
528 | |
529 | out_eoi: | |
0c5c1557 | 530 | desc->irq_data.chip->irq_eoi(&desc->irq_data); |
77694b40 | 531 | out_unlock: |
239007b8 | 532 | raw_spin_unlock(&desc->lock); |
77694b40 TG |
533 | return; |
534 | out: | |
535 | if (!(desc->irq_data.chip->flags & IRQCHIP_EOI_IF_HANDLED)) | |
536 | goto out_eoi; | |
537 | goto out_unlock; | |
dd87eb3a TG |
538 | } |
539 | ||
540 | /** | |
541 | * handle_edge_irq - edge type IRQ handler | |
542 | * @irq: the interrupt number | |
543 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
544 | * |
545 | * Interrupt occures on the falling and/or rising edge of a hardware | |
546 | * signal. The occurence is latched into the irq controller hardware | |
547 | * and must be acked in order to be reenabled. After the ack another | |
548 | * interrupt can happen on the same source even before the first one | |
dfff0615 | 549 | * is handled by the associated event handler. If this happens it |
dd87eb3a TG |
550 | * might be necessary to disable (mask) the interrupt depending on the |
551 | * controller hardware. This requires to reenable the interrupt inside | |
552 | * of the loop which handles the interrupts which have arrived while | |
553 | * the handler was running. If all pending interrupts are handled, the | |
554 | * loop is left. | |
555 | */ | |
7ad5b3a5 | 556 | void |
7d12e780 | 557 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 558 | { |
239007b8 | 559 | raw_spin_lock(&desc->lock); |
dd87eb3a | 560 | |
163ef309 | 561 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
dd87eb3a TG |
562 | /* |
563 | * If we're currently running this IRQ, or its disabled, | |
564 | * we shouldn't process the IRQ. Mark it pending, handle | |
565 | * the necessary masking and go out | |
566 | */ | |
c1594b77 TG |
567 | if (unlikely((desc->istate & (IRQS_DISABLED | IRQS_INPROGRESS) || |
568 | !desc->action))) { | |
fe200ae4 | 569 | if (!irq_check_poll(desc)) { |
2a0d6fb3 TG |
570 | irq_compat_set_pending(desc); |
571 | desc->istate |= IRQS_PENDING; | |
fe200ae4 TG |
572 | mask_ack_irq(desc); |
573 | goto out_unlock; | |
574 | } | |
dd87eb3a | 575 | } |
d6c88a50 | 576 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
577 | |
578 | /* Start handling the irq */ | |
22a49163 | 579 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
dd87eb3a | 580 | |
dd87eb3a | 581 | do { |
a60a5dc2 | 582 | if (unlikely(!desc->action)) { |
e2c0f8ff | 583 | mask_irq(desc); |
dd87eb3a TG |
584 | goto out_unlock; |
585 | } | |
586 | ||
587 | /* | |
588 | * When another irq arrived while we were handling | |
589 | * one, we could have masked the irq. | |
590 | * Renable it, if it was not disabled in meantime. | |
591 | */ | |
2a0d6fb3 | 592 | if (unlikely(desc->istate & IRQS_PENDING)) { |
c1594b77 | 593 | if (!(desc->istate & IRQS_DISABLED) && |
6e40262e | 594 | (desc->istate & IRQS_MASKED)) |
c1594b77 | 595 | unmask_irq(desc); |
dd87eb3a TG |
596 | } |
597 | ||
a60a5dc2 | 598 | handle_irq_event(desc); |
dd87eb3a | 599 | |
2a0d6fb3 | 600 | } while ((desc->istate & IRQS_PENDING) && |
c1594b77 | 601 | !(desc->istate & IRQS_DISABLED)); |
dd87eb3a | 602 | |
dd87eb3a | 603 | out_unlock: |
239007b8 | 604 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
605 | } |
606 | ||
dd87eb3a | 607 | /** |
24b26d42 | 608 | * handle_percpu_irq - Per CPU local irq handler |
dd87eb3a TG |
609 | * @irq: the interrupt number |
610 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
611 | * |
612 | * Per CPU interrupts on SMP machines without locking requirements | |
613 | */ | |
7ad5b3a5 | 614 | void |
7d12e780 | 615 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 616 | { |
35e857cb | 617 | struct irq_chip *chip = irq_desc_get_chip(desc); |
dd87eb3a | 618 | |
d6c88a50 | 619 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a | 620 | |
849f061c TG |
621 | if (chip->irq_ack) |
622 | chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 623 | |
849f061c | 624 | handle_irq_event_percpu(desc, desc->action); |
dd87eb3a | 625 | |
849f061c TG |
626 | if (chip->irq_eoi) |
627 | chip->irq_eoi(&desc->irq_data); | |
dd87eb3a TG |
628 | } |
629 | ||
dd87eb3a | 630 | void |
3836ca08 | 631 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
a460e745 | 632 | const char *name) |
dd87eb3a | 633 | { |
dd87eb3a | 634 | unsigned long flags; |
02725e74 | 635 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags); |
dd87eb3a | 636 | |
02725e74 | 637 | if (!desc) |
dd87eb3a | 638 | return; |
dd87eb3a | 639 | |
091738a2 | 640 | if (!handle) { |
dd87eb3a | 641 | handle = handle_bad_irq; |
091738a2 TG |
642 | } else { |
643 | if (WARN_ON(desc->irq_data.chip == &no_irq_chip)) | |
02725e74 | 644 | goto out; |
f8b5473f | 645 | } |
dd87eb3a | 646 | |
dd87eb3a TG |
647 | /* Uninstall? */ |
648 | if (handle == handle_bad_irq) { | |
6b8ff312 | 649 | if (desc->irq_data.chip != &no_irq_chip) |
9205e31d | 650 | mask_ack_irq(desc); |
c1594b77 TG |
651 | irq_compat_set_disabled(desc); |
652 | desc->istate |= IRQS_DISABLED; | |
dd87eb3a TG |
653 | desc->depth = 1; |
654 | } | |
655 | desc->handle_irq = handle; | |
a460e745 | 656 | desc->name = name; |
dd87eb3a TG |
657 | |
658 | if (handle != handle_bad_irq && is_chained) { | |
1ccb4e61 TG |
659 | irq_settings_set_noprobe(desc); |
660 | irq_settings_set_norequest(desc); | |
46999238 | 661 | irq_startup(desc); |
dd87eb3a | 662 | } |
02725e74 TG |
663 | out: |
664 | irq_put_desc_busunlock(desc, flags); | |
dd87eb3a | 665 | } |
3836ca08 | 666 | EXPORT_SYMBOL_GPL(__irq_set_handler); |
dd87eb3a TG |
667 | |
668 | void | |
3836ca08 | 669 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 | 670 | irq_flow_handler_t handle, const char *name) |
dd87eb3a | 671 | { |
35e857cb | 672 | irq_set_chip(irq, chip); |
3836ca08 | 673 | __irq_set_handler(irq, handle, 0, name); |
dd87eb3a | 674 | } |
46f4f8f6 | 675 | |
44247184 | 676 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
46f4f8f6 | 677 | { |
46f4f8f6 | 678 | unsigned long flags; |
02725e74 | 679 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags); |
46f4f8f6 | 680 | |
44247184 | 681 | if (!desc) |
46f4f8f6 | 682 | return; |
a005677b TG |
683 | irq_settings_clr_and_set(desc, clr, set); |
684 | ||
876dbd4c | 685 | irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | |
e1ef8241 | 686 | IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); |
a005677b TG |
687 | if (irq_settings_has_no_balance_set(desc)) |
688 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | |
689 | if (irq_settings_is_per_cpu(desc)) | |
690 | irqd_set(&desc->irq_data, IRQD_PER_CPU); | |
e1ef8241 TG |
691 | if (irq_settings_can_move_pcntxt(desc)) |
692 | irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); | |
a005677b | 693 | |
876dbd4c TG |
694 | irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); |
695 | ||
02725e74 | 696 | irq_put_desc_unlock(desc, flags); |
46f4f8f6 | 697 | } |