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Commit | Line | Data |
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dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
f8264e34 | 18 | #include <linux/irqdomain.h> |
dd87eb3a | 19 | |
f069686e SR |
20 | #include <trace/events/irq.h> |
21 | ||
dd87eb3a TG |
22 | #include "internals.h" |
23 | ||
e509bd7d MW |
24 | static irqreturn_t bad_chained_irq(int irq, void *dev_id) |
25 | { | |
26 | WARN_ONCE(1, "Chained irq %d should not call an action\n", irq); | |
27 | return IRQ_NONE; | |
28 | } | |
29 | ||
30 | /* | |
31 | * Chained handlers should never call action on their IRQ. This default | |
32 | * action will emit warning if such thing happens. | |
33 | */ | |
34 | struct irqaction chained_action = { | |
35 | .handler = bad_chained_irq, | |
36 | }; | |
37 | ||
dd87eb3a | 38 | /** |
a0cd9ca2 | 39 | * irq_set_chip - set the irq chip for an irq |
dd87eb3a TG |
40 | * @irq: irq number |
41 | * @chip: pointer to irq chip description structure | |
42 | */ | |
a0cd9ca2 | 43 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) |
dd87eb3a | 44 | { |
dd87eb3a | 45 | unsigned long flags; |
31d9d9b6 | 46 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
dd87eb3a | 47 | |
02725e74 | 48 | if (!desc) |
dd87eb3a | 49 | return -EINVAL; |
dd87eb3a TG |
50 | |
51 | if (!chip) | |
52 | chip = &no_irq_chip; | |
53 | ||
6b8ff312 | 54 | desc->irq_data.chip = chip; |
02725e74 | 55 | irq_put_desc_unlock(desc, flags); |
d72274e5 DD |
56 | /* |
57 | * For !CONFIG_SPARSE_IRQ make the irq show up in | |
f63b6a05 | 58 | * allocated_irqs. |
d72274e5 | 59 | */ |
f63b6a05 | 60 | irq_mark_irq(irq); |
dd87eb3a TG |
61 | return 0; |
62 | } | |
a0cd9ca2 | 63 | EXPORT_SYMBOL(irq_set_chip); |
dd87eb3a TG |
64 | |
65 | /** | |
a0cd9ca2 | 66 | * irq_set_type - set the irq trigger type for an irq |
dd87eb3a | 67 | * @irq: irq number |
0c5d1eb7 | 68 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a | 69 | */ |
a0cd9ca2 | 70 | int irq_set_irq_type(unsigned int irq, unsigned int type) |
dd87eb3a | 71 | { |
dd87eb3a | 72 | unsigned long flags; |
31d9d9b6 | 73 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
02725e74 | 74 | int ret = 0; |
dd87eb3a | 75 | |
02725e74 TG |
76 | if (!desc) |
77 | return -EINVAL; | |
dd87eb3a | 78 | |
f2b662da | 79 | type &= IRQ_TYPE_SENSE_MASK; |
a1ff541a | 80 | ret = __irq_set_trigger(desc, type); |
02725e74 | 81 | irq_put_desc_busunlock(desc, flags); |
dd87eb3a TG |
82 | return ret; |
83 | } | |
a0cd9ca2 | 84 | EXPORT_SYMBOL(irq_set_irq_type); |
dd87eb3a TG |
85 | |
86 | /** | |
a0cd9ca2 | 87 | * irq_set_handler_data - set irq handler data for an irq |
dd87eb3a TG |
88 | * @irq: Interrupt number |
89 | * @data: Pointer to interrupt specific data | |
90 | * | |
91 | * Set the hardware irq controller data for an irq | |
92 | */ | |
a0cd9ca2 | 93 | int irq_set_handler_data(unsigned int irq, void *data) |
dd87eb3a | 94 | { |
dd87eb3a | 95 | unsigned long flags; |
31d9d9b6 | 96 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
dd87eb3a | 97 | |
02725e74 | 98 | if (!desc) |
dd87eb3a | 99 | return -EINVAL; |
af7080e0 | 100 | desc->irq_common_data.handler_data = data; |
02725e74 | 101 | irq_put_desc_unlock(desc, flags); |
dd87eb3a TG |
102 | return 0; |
103 | } | |
a0cd9ca2 | 104 | EXPORT_SYMBOL(irq_set_handler_data); |
dd87eb3a | 105 | |
5b912c10 | 106 | /** |
51906e77 AG |
107 | * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset |
108 | * @irq_base: Interrupt number base | |
109 | * @irq_offset: Interrupt number offset | |
110 | * @entry: Pointer to MSI descriptor data | |
5b912c10 | 111 | * |
51906e77 | 112 | * Set the MSI descriptor entry for an irq at offset |
5b912c10 | 113 | */ |
51906e77 AG |
114 | int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, |
115 | struct msi_desc *entry) | |
5b912c10 | 116 | { |
5b912c10 | 117 | unsigned long flags; |
51906e77 | 118 | struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
5b912c10 | 119 | |
02725e74 | 120 | if (!desc) |
5b912c10 | 121 | return -EINVAL; |
b237721c | 122 | desc->irq_common_data.msi_desc = entry; |
51906e77 AG |
123 | if (entry && !irq_offset) |
124 | entry->irq = irq_base; | |
02725e74 | 125 | irq_put_desc_unlock(desc, flags); |
5b912c10 EB |
126 | return 0; |
127 | } | |
128 | ||
51906e77 AG |
129 | /** |
130 | * irq_set_msi_desc - set MSI descriptor data for an irq | |
131 | * @irq: Interrupt number | |
132 | * @entry: Pointer to MSI descriptor data | |
133 | * | |
134 | * Set the MSI descriptor entry for an irq | |
135 | */ | |
136 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) | |
137 | { | |
138 | return irq_set_msi_desc_off(irq, 0, entry); | |
139 | } | |
140 | ||
dd87eb3a | 141 | /** |
a0cd9ca2 | 142 | * irq_set_chip_data - set irq chip data for an irq |
dd87eb3a TG |
143 | * @irq: Interrupt number |
144 | * @data: Pointer to chip specific data | |
145 | * | |
146 | * Set the hardware irq chip data for an irq | |
147 | */ | |
a0cd9ca2 | 148 | int irq_set_chip_data(unsigned int irq, void *data) |
dd87eb3a | 149 | { |
dd87eb3a | 150 | unsigned long flags; |
31d9d9b6 | 151 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
dd87eb3a | 152 | |
02725e74 | 153 | if (!desc) |
dd87eb3a | 154 | return -EINVAL; |
6b8ff312 | 155 | desc->irq_data.chip_data = data; |
02725e74 | 156 | irq_put_desc_unlock(desc, flags); |
dd87eb3a TG |
157 | return 0; |
158 | } | |
a0cd9ca2 | 159 | EXPORT_SYMBOL(irq_set_chip_data); |
dd87eb3a | 160 | |
f303a6dd TG |
161 | struct irq_data *irq_get_irq_data(unsigned int irq) |
162 | { | |
163 | struct irq_desc *desc = irq_to_desc(irq); | |
164 | ||
165 | return desc ? &desc->irq_data : NULL; | |
166 | } | |
167 | EXPORT_SYMBOL_GPL(irq_get_irq_data); | |
168 | ||
c1594b77 TG |
169 | static void irq_state_clr_disabled(struct irq_desc *desc) |
170 | { | |
801a0e9a | 171 | irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED); |
c1594b77 TG |
172 | } |
173 | ||
174 | static void irq_state_set_disabled(struct irq_desc *desc) | |
175 | { | |
801a0e9a | 176 | irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); |
c1594b77 TG |
177 | } |
178 | ||
6e40262e TG |
179 | static void irq_state_clr_masked(struct irq_desc *desc) |
180 | { | |
32f4125e | 181 | irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED); |
6e40262e TG |
182 | } |
183 | ||
184 | static void irq_state_set_masked(struct irq_desc *desc) | |
185 | { | |
32f4125e | 186 | irqd_set(&desc->irq_data, IRQD_IRQ_MASKED); |
6e40262e TG |
187 | } |
188 | ||
b4bc724e | 189 | int irq_startup(struct irq_desc *desc, bool resend) |
46999238 | 190 | { |
b4bc724e TG |
191 | int ret = 0; |
192 | ||
c1594b77 | 193 | irq_state_clr_disabled(desc); |
46999238 TG |
194 | desc->depth = 0; |
195 | ||
f8264e34 | 196 | irq_domain_activate_irq(&desc->irq_data); |
3aae994f | 197 | if (desc->irq_data.chip->irq_startup) { |
b4bc724e | 198 | ret = desc->irq_data.chip->irq_startup(&desc->irq_data); |
6e40262e | 199 | irq_state_clr_masked(desc); |
b4bc724e TG |
200 | } else { |
201 | irq_enable(desc); | |
3aae994f | 202 | } |
b4bc724e | 203 | if (resend) |
0798abeb | 204 | check_irq_resend(desc); |
b4bc724e | 205 | return ret; |
46999238 TG |
206 | } |
207 | ||
208 | void irq_shutdown(struct irq_desc *desc) | |
209 | { | |
c1594b77 | 210 | irq_state_set_disabled(desc); |
46999238 | 211 | desc->depth = 1; |
50f7c032 TG |
212 | if (desc->irq_data.chip->irq_shutdown) |
213 | desc->irq_data.chip->irq_shutdown(&desc->irq_data); | |
ed585a65 | 214 | else if (desc->irq_data.chip->irq_disable) |
50f7c032 TG |
215 | desc->irq_data.chip->irq_disable(&desc->irq_data); |
216 | else | |
217 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
f8264e34 | 218 | irq_domain_deactivate_irq(&desc->irq_data); |
6e40262e | 219 | irq_state_set_masked(desc); |
46999238 TG |
220 | } |
221 | ||
87923470 TG |
222 | void irq_enable(struct irq_desc *desc) |
223 | { | |
c1594b77 | 224 | irq_state_clr_disabled(desc); |
50f7c032 TG |
225 | if (desc->irq_data.chip->irq_enable) |
226 | desc->irq_data.chip->irq_enable(&desc->irq_data); | |
227 | else | |
228 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
6e40262e | 229 | irq_state_clr_masked(desc); |
dd87eb3a TG |
230 | } |
231 | ||
d671a605 | 232 | /** |
f788e7bf | 233 | * irq_disable - Mark interrupt disabled |
d671a605 AF |
234 | * @desc: irq descriptor which should be disabled |
235 | * | |
236 | * If the chip does not implement the irq_disable callback, we | |
237 | * use a lazy disable approach. That means we mark the interrupt | |
238 | * disabled, but leave the hardware unmasked. That's an | |
239 | * optimization because we avoid the hardware access for the | |
240 | * common case where no interrupt happens after we marked it | |
241 | * disabled. If an interrupt happens, then the interrupt flow | |
242 | * handler masks the line at the hardware level and marks it | |
243 | * pending. | |
e9849777 TG |
244 | * |
245 | * If the interrupt chip does not implement the irq_disable callback, | |
246 | * a driver can disable the lazy approach for a particular irq line by | |
247 | * calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can | |
248 | * be used for devices which cannot disable the interrupt at the | |
249 | * device level under certain circumstances and have to use | |
250 | * disable_irq[_nosync] instead. | |
d671a605 | 251 | */ |
50f7c032 | 252 | void irq_disable(struct irq_desc *desc) |
89d694b9 | 253 | { |
c1594b77 | 254 | irq_state_set_disabled(desc); |
50f7c032 TG |
255 | if (desc->irq_data.chip->irq_disable) { |
256 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
a61d8258 | 257 | irq_state_set_masked(desc); |
e9849777 TG |
258 | } else if (irq_settings_disable_unlazy(desc)) { |
259 | mask_irq(desc); | |
50f7c032 | 260 | } |
89d694b9 TG |
261 | } |
262 | ||
31d9d9b6 MZ |
263 | void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu) |
264 | { | |
265 | if (desc->irq_data.chip->irq_enable) | |
266 | desc->irq_data.chip->irq_enable(&desc->irq_data); | |
267 | else | |
268 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
269 | cpumask_set_cpu(cpu, desc->percpu_enabled); | |
270 | } | |
271 | ||
272 | void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu) | |
273 | { | |
274 | if (desc->irq_data.chip->irq_disable) | |
275 | desc->irq_data.chip->irq_disable(&desc->irq_data); | |
276 | else | |
277 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
278 | cpumask_clear_cpu(cpu, desc->percpu_enabled); | |
279 | } | |
280 | ||
9205e31d | 281 | static inline void mask_ack_irq(struct irq_desc *desc) |
dd87eb3a | 282 | { |
9205e31d TG |
283 | if (desc->irq_data.chip->irq_mask_ack) |
284 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | |
dd87eb3a | 285 | else { |
e2c0f8ff | 286 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
22a49163 TG |
287 | if (desc->irq_data.chip->irq_ack) |
288 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 289 | } |
6e40262e | 290 | irq_state_set_masked(desc); |
0b1adaa0 TG |
291 | } |
292 | ||
d4d5e089 | 293 | void mask_irq(struct irq_desc *desc) |
0b1adaa0 | 294 | { |
e2c0f8ff TG |
295 | if (desc->irq_data.chip->irq_mask) { |
296 | desc->irq_data.chip->irq_mask(&desc->irq_data); | |
6e40262e | 297 | irq_state_set_masked(desc); |
0b1adaa0 TG |
298 | } |
299 | } | |
300 | ||
d4d5e089 | 301 | void unmask_irq(struct irq_desc *desc) |
0b1adaa0 | 302 | { |
0eda58b7 TG |
303 | if (desc->irq_data.chip->irq_unmask) { |
304 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | |
6e40262e | 305 | irq_state_clr_masked(desc); |
0b1adaa0 | 306 | } |
dd87eb3a TG |
307 | } |
308 | ||
328a4978 TG |
309 | void unmask_threaded_irq(struct irq_desc *desc) |
310 | { | |
311 | struct irq_chip *chip = desc->irq_data.chip; | |
312 | ||
313 | if (chip->flags & IRQCHIP_EOI_THREADED) | |
314 | chip->irq_eoi(&desc->irq_data); | |
315 | ||
316 | if (chip->irq_unmask) { | |
317 | chip->irq_unmask(&desc->irq_data); | |
318 | irq_state_clr_masked(desc); | |
319 | } | |
320 | } | |
321 | ||
399b5da2 TG |
322 | /* |
323 | * handle_nested_irq - Handle a nested irq from a irq thread | |
324 | * @irq: the interrupt number | |
325 | * | |
326 | * Handle interrupts which are nested into a threaded interrupt | |
327 | * handler. The handler function is called inside the calling | |
328 | * threads context. | |
329 | */ | |
330 | void handle_nested_irq(unsigned int irq) | |
331 | { | |
332 | struct irq_desc *desc = irq_to_desc(irq); | |
333 | struct irqaction *action; | |
334 | irqreturn_t action_ret; | |
335 | ||
336 | might_sleep(); | |
337 | ||
239007b8 | 338 | raw_spin_lock_irq(&desc->lock); |
399b5da2 | 339 | |
293a7a0a | 340 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
399b5da2 TG |
341 | |
342 | action = desc->action; | |
23812b9d NJ |
343 | if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) { |
344 | desc->istate |= IRQS_PENDING; | |
399b5da2 | 345 | goto out_unlock; |
23812b9d | 346 | } |
399b5da2 | 347 | |
a946e8c7 | 348 | kstat_incr_irqs_this_cpu(desc); |
32f4125e | 349 | irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
239007b8 | 350 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
351 | |
352 | action_ret = action->thread_fn(action->irq, action->dev_id); | |
353 | if (!noirqdebug) | |
0dcdbc97 | 354 | note_interrupt(desc, action_ret); |
399b5da2 | 355 | |
239007b8 | 356 | raw_spin_lock_irq(&desc->lock); |
32f4125e | 357 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
399b5da2 TG |
358 | |
359 | out_unlock: | |
239007b8 | 360 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
361 | } |
362 | EXPORT_SYMBOL_GPL(handle_nested_irq); | |
363 | ||
fe200ae4 TG |
364 | static bool irq_check_poll(struct irq_desc *desc) |
365 | { | |
6954b75b | 366 | if (!(desc->istate & IRQS_POLL_INPROGRESS)) |
fe200ae4 TG |
367 | return false; |
368 | return irq_wait_for_poll(desc); | |
369 | } | |
370 | ||
c7bd3ec0 TG |
371 | static bool irq_may_run(struct irq_desc *desc) |
372 | { | |
9ce7a258 TG |
373 | unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED; |
374 | ||
375 | /* | |
376 | * If the interrupt is not in progress and is not an armed | |
377 | * wakeup interrupt, proceed. | |
378 | */ | |
379 | if (!irqd_has_set(&desc->irq_data, mask)) | |
c7bd3ec0 | 380 | return true; |
9ce7a258 TG |
381 | |
382 | /* | |
383 | * If the interrupt is an armed wakeup source, mark it pending | |
384 | * and suspended, disable it and notify the pm core about the | |
385 | * event. | |
386 | */ | |
387 | if (irq_pm_check_wakeup(desc)) | |
388 | return false; | |
389 | ||
390 | /* | |
391 | * Handle a potential concurrent poll on a different core. | |
392 | */ | |
c7bd3ec0 TG |
393 | return irq_check_poll(desc); |
394 | } | |
395 | ||
dd87eb3a TG |
396 | /** |
397 | * handle_simple_irq - Simple and software-decoded IRQs. | |
dd87eb3a | 398 | * @desc: the interrupt description structure for this irq |
dd87eb3a TG |
399 | * |
400 | * Simple interrupts are either sent from a demultiplexing interrupt | |
401 | * handler or come from hardware, where no interrupt hardware control | |
402 | * is necessary. | |
403 | * | |
404 | * Note: The caller is expected to handle the ack, clear, mask and | |
405 | * unmask issues if necessary. | |
406 | */ | |
bd0b9ac4 | 407 | void handle_simple_irq(struct irq_desc *desc) |
dd87eb3a | 408 | { |
239007b8 | 409 | raw_spin_lock(&desc->lock); |
dd87eb3a | 410 | |
c7bd3ec0 TG |
411 | if (!irq_may_run(desc)) |
412 | goto out_unlock; | |
fe200ae4 | 413 | |
163ef309 | 414 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
dd87eb3a | 415 | |
23812b9d NJ |
416 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
417 | desc->istate |= IRQS_PENDING; | |
dd87eb3a | 418 | goto out_unlock; |
23812b9d | 419 | } |
dd87eb3a | 420 | |
a946e8c7 | 421 | kstat_incr_irqs_this_cpu(desc); |
107781e7 | 422 | handle_irq_event(desc); |
dd87eb3a | 423 | |
dd87eb3a | 424 | out_unlock: |
239007b8 | 425 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 426 | } |
edf76f83 | 427 | EXPORT_SYMBOL_GPL(handle_simple_irq); |
dd87eb3a | 428 | |
edd14cfe KB |
429 | /** |
430 | * handle_untracked_irq - Simple and software-decoded IRQs. | |
431 | * @desc: the interrupt description structure for this irq | |
432 | * | |
433 | * Untracked interrupts are sent from a demultiplexing interrupt | |
434 | * handler when the demultiplexer does not know which device it its | |
435 | * multiplexed irq domain generated the interrupt. IRQ's handled | |
436 | * through here are not subjected to stats tracking, randomness, or | |
437 | * spurious interrupt detection. | |
438 | * | |
439 | * Note: Like handle_simple_irq, the caller is expected to handle | |
440 | * the ack, clear, mask and unmask issues if necessary. | |
441 | */ | |
442 | void handle_untracked_irq(struct irq_desc *desc) | |
443 | { | |
444 | unsigned int flags = 0; | |
445 | ||
446 | raw_spin_lock(&desc->lock); | |
447 | ||
448 | if (!irq_may_run(desc)) | |
449 | goto out_unlock; | |
450 | ||
451 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | |
452 | ||
453 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { | |
454 | desc->istate |= IRQS_PENDING; | |
455 | goto out_unlock; | |
456 | } | |
457 | ||
458 | desc->istate &= ~IRQS_PENDING; | |
459 | irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS); | |
460 | raw_spin_unlock(&desc->lock); | |
461 | ||
462 | __handle_irq_event_percpu(desc, &flags); | |
463 | ||
464 | raw_spin_lock(&desc->lock); | |
465 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); | |
466 | ||
467 | out_unlock: | |
468 | raw_spin_unlock(&desc->lock); | |
469 | } | |
470 | EXPORT_SYMBOL_GPL(handle_untracked_irq); | |
471 | ||
ac563761 TG |
472 | /* |
473 | * Called unconditionally from handle_level_irq() and only for oneshot | |
474 | * interrupts from handle_fasteoi_irq() | |
475 | */ | |
476 | static void cond_unmask_irq(struct irq_desc *desc) | |
477 | { | |
478 | /* | |
479 | * We need to unmask in the following cases: | |
480 | * - Standard level irq (IRQF_ONESHOT is not set) | |
481 | * - Oneshot irq which did not wake the thread (caused by a | |
482 | * spurious interrupt or a primary handler handling it | |
483 | * completely). | |
484 | */ | |
485 | if (!irqd_irq_disabled(&desc->irq_data) && | |
486 | irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) | |
487 | unmask_irq(desc); | |
488 | } | |
489 | ||
dd87eb3a TG |
490 | /** |
491 | * handle_level_irq - Level type irq handler | |
dd87eb3a | 492 | * @desc: the interrupt description structure for this irq |
dd87eb3a TG |
493 | * |
494 | * Level type interrupts are active as long as the hardware line has | |
495 | * the active level. This may require to mask the interrupt and unmask | |
496 | * it after the associated handler has acknowledged the device, so the | |
497 | * interrupt line is back to inactive. | |
498 | */ | |
bd0b9ac4 | 499 | void handle_level_irq(struct irq_desc *desc) |
dd87eb3a | 500 | { |
239007b8 | 501 | raw_spin_lock(&desc->lock); |
9205e31d | 502 | mask_ack_irq(desc); |
dd87eb3a | 503 | |
c7bd3ec0 TG |
504 | if (!irq_may_run(desc)) |
505 | goto out_unlock; | |
fe200ae4 | 506 | |
163ef309 | 507 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
dd87eb3a TG |
508 | |
509 | /* | |
510 | * If its disabled or no action available | |
511 | * keep it masked and get out of here | |
512 | */ | |
d4dc0f90 TG |
513 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
514 | desc->istate |= IRQS_PENDING; | |
86998aa6 | 515 | goto out_unlock; |
d4dc0f90 | 516 | } |
dd87eb3a | 517 | |
a946e8c7 | 518 | kstat_incr_irqs_this_cpu(desc); |
1529866c | 519 | handle_irq_event(desc); |
b25c340c | 520 | |
ac563761 TG |
521 | cond_unmask_irq(desc); |
522 | ||
86998aa6 | 523 | out_unlock: |
239007b8 | 524 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 525 | } |
14819ea1 | 526 | EXPORT_SYMBOL_GPL(handle_level_irq); |
dd87eb3a | 527 | |
78129576 TG |
528 | #ifdef CONFIG_IRQ_PREFLOW_FASTEOI |
529 | static inline void preflow_handler(struct irq_desc *desc) | |
530 | { | |
531 | if (desc->preflow_handler) | |
532 | desc->preflow_handler(&desc->irq_data); | |
533 | } | |
534 | #else | |
535 | static inline void preflow_handler(struct irq_desc *desc) { } | |
536 | #endif | |
537 | ||
328a4978 TG |
538 | static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip) |
539 | { | |
540 | if (!(desc->istate & IRQS_ONESHOT)) { | |
541 | chip->irq_eoi(&desc->irq_data); | |
542 | return; | |
543 | } | |
544 | /* | |
545 | * We need to unmask in the following cases: | |
546 | * - Oneshot irq which did not wake the thread (caused by a | |
547 | * spurious interrupt or a primary handler handling it | |
548 | * completely). | |
549 | */ | |
550 | if (!irqd_irq_disabled(&desc->irq_data) && | |
551 | irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) { | |
552 | chip->irq_eoi(&desc->irq_data); | |
553 | unmask_irq(desc); | |
554 | } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) { | |
555 | chip->irq_eoi(&desc->irq_data); | |
556 | } | |
557 | } | |
558 | ||
dd87eb3a | 559 | /** |
47c2a3aa | 560 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a | 561 | * @desc: the interrupt description structure for this irq |
dd87eb3a | 562 | * |
47c2a3aa | 563 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
564 | * call when the interrupt has been serviced. This enables support |
565 | * for modern forms of interrupt handlers, which handle the flow | |
566 | * details in hardware, transparently. | |
567 | */ | |
bd0b9ac4 | 568 | void handle_fasteoi_irq(struct irq_desc *desc) |
dd87eb3a | 569 | { |
328a4978 TG |
570 | struct irq_chip *chip = desc->irq_data.chip; |
571 | ||
239007b8 | 572 | raw_spin_lock(&desc->lock); |
dd87eb3a | 573 | |
c7bd3ec0 TG |
574 | if (!irq_may_run(desc)) |
575 | goto out; | |
dd87eb3a | 576 | |
163ef309 | 577 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
dd87eb3a TG |
578 | |
579 | /* | |
580 | * If its disabled or no action available | |
76d21601 | 581 | * then mask it and get out of here: |
dd87eb3a | 582 | */ |
32f4125e | 583 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
2a0d6fb3 | 584 | desc->istate |= IRQS_PENDING; |
e2c0f8ff | 585 | mask_irq(desc); |
dd87eb3a | 586 | goto out; |
98bb244b | 587 | } |
c69e3758 | 588 | |
a946e8c7 | 589 | kstat_incr_irqs_this_cpu(desc); |
c69e3758 TG |
590 | if (desc->istate & IRQS_ONESHOT) |
591 | mask_irq(desc); | |
592 | ||
78129576 | 593 | preflow_handler(desc); |
a7ae4de5 | 594 | handle_irq_event(desc); |
77694b40 | 595 | |
328a4978 | 596 | cond_unmask_eoi_irq(desc, chip); |
ac563761 | 597 | |
239007b8 | 598 | raw_spin_unlock(&desc->lock); |
77694b40 TG |
599 | return; |
600 | out: | |
328a4978 TG |
601 | if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED)) |
602 | chip->irq_eoi(&desc->irq_data); | |
603 | raw_spin_unlock(&desc->lock); | |
dd87eb3a | 604 | } |
7cad45ee | 605 | EXPORT_SYMBOL_GPL(handle_fasteoi_irq); |
dd87eb3a TG |
606 | |
607 | /** | |
608 | * handle_edge_irq - edge type IRQ handler | |
dd87eb3a | 609 | * @desc: the interrupt description structure for this irq |
dd87eb3a TG |
610 | * |
611 | * Interrupt occures on the falling and/or rising edge of a hardware | |
25985edc | 612 | * signal. The occurrence is latched into the irq controller hardware |
dd87eb3a TG |
613 | * and must be acked in order to be reenabled. After the ack another |
614 | * interrupt can happen on the same source even before the first one | |
dfff0615 | 615 | * is handled by the associated event handler. If this happens it |
dd87eb3a TG |
616 | * might be necessary to disable (mask) the interrupt depending on the |
617 | * controller hardware. This requires to reenable the interrupt inside | |
618 | * of the loop which handles the interrupts which have arrived while | |
619 | * the handler was running. If all pending interrupts are handled, the | |
620 | * loop is left. | |
621 | */ | |
bd0b9ac4 | 622 | void handle_edge_irq(struct irq_desc *desc) |
dd87eb3a | 623 | { |
239007b8 | 624 | raw_spin_lock(&desc->lock); |
dd87eb3a | 625 | |
163ef309 | 626 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
c3d7acd0 | 627 | |
c7bd3ec0 TG |
628 | if (!irq_may_run(desc)) { |
629 | desc->istate |= IRQS_PENDING; | |
630 | mask_ack_irq(desc); | |
631 | goto out_unlock; | |
dd87eb3a | 632 | } |
c3d7acd0 | 633 | |
dd87eb3a | 634 | /* |
c3d7acd0 TG |
635 | * If its disabled or no action available then mask it and get |
636 | * out of here. | |
dd87eb3a | 637 | */ |
c3d7acd0 TG |
638 | if (irqd_irq_disabled(&desc->irq_data) || !desc->action) { |
639 | desc->istate |= IRQS_PENDING; | |
640 | mask_ack_irq(desc); | |
641 | goto out_unlock; | |
dd87eb3a | 642 | } |
c3d7acd0 | 643 | |
b51bf95c | 644 | kstat_incr_irqs_this_cpu(desc); |
dd87eb3a TG |
645 | |
646 | /* Start handling the irq */ | |
22a49163 | 647 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
dd87eb3a | 648 | |
dd87eb3a | 649 | do { |
a60a5dc2 | 650 | if (unlikely(!desc->action)) { |
e2c0f8ff | 651 | mask_irq(desc); |
dd87eb3a TG |
652 | goto out_unlock; |
653 | } | |
654 | ||
655 | /* | |
656 | * When another irq arrived while we were handling | |
657 | * one, we could have masked the irq. | |
658 | * Renable it, if it was not disabled in meantime. | |
659 | */ | |
2a0d6fb3 | 660 | if (unlikely(desc->istate & IRQS_PENDING)) { |
32f4125e TG |
661 | if (!irqd_irq_disabled(&desc->irq_data) && |
662 | irqd_irq_masked(&desc->irq_data)) | |
c1594b77 | 663 | unmask_irq(desc); |
dd87eb3a TG |
664 | } |
665 | ||
a60a5dc2 | 666 | handle_irq_event(desc); |
dd87eb3a | 667 | |
2a0d6fb3 | 668 | } while ((desc->istate & IRQS_PENDING) && |
32f4125e | 669 | !irqd_irq_disabled(&desc->irq_data)); |
dd87eb3a | 670 | |
dd87eb3a | 671 | out_unlock: |
239007b8 | 672 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 673 | } |
3911ff30 | 674 | EXPORT_SYMBOL(handle_edge_irq); |
dd87eb3a | 675 | |
0521c8fb TG |
676 | #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER |
677 | /** | |
678 | * handle_edge_eoi_irq - edge eoi type IRQ handler | |
0521c8fb TG |
679 | * @desc: the interrupt description structure for this irq |
680 | * | |
681 | * Similar as the above handle_edge_irq, but using eoi and w/o the | |
682 | * mask/unmask logic. | |
683 | */ | |
bd0b9ac4 | 684 | void handle_edge_eoi_irq(struct irq_desc *desc) |
0521c8fb TG |
685 | { |
686 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
687 | ||
688 | raw_spin_lock(&desc->lock); | |
689 | ||
690 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | |
c3d7acd0 | 691 | |
c7bd3ec0 TG |
692 | if (!irq_may_run(desc)) { |
693 | desc->istate |= IRQS_PENDING; | |
694 | goto out_eoi; | |
0521c8fb | 695 | } |
c3d7acd0 | 696 | |
0521c8fb | 697 | /* |
c3d7acd0 TG |
698 | * If its disabled or no action available then mask it and get |
699 | * out of here. | |
0521c8fb | 700 | */ |
c3d7acd0 TG |
701 | if (irqd_irq_disabled(&desc->irq_data) || !desc->action) { |
702 | desc->istate |= IRQS_PENDING; | |
703 | goto out_eoi; | |
0521c8fb | 704 | } |
c3d7acd0 | 705 | |
b51bf95c | 706 | kstat_incr_irqs_this_cpu(desc); |
0521c8fb TG |
707 | |
708 | do { | |
709 | if (unlikely(!desc->action)) | |
710 | goto out_eoi; | |
711 | ||
712 | handle_irq_event(desc); | |
713 | ||
714 | } while ((desc->istate & IRQS_PENDING) && | |
715 | !irqd_irq_disabled(&desc->irq_data)); | |
716 | ||
ac0e0447 | 717 | out_eoi: |
0521c8fb TG |
718 | chip->irq_eoi(&desc->irq_data); |
719 | raw_spin_unlock(&desc->lock); | |
720 | } | |
721 | #endif | |
722 | ||
dd87eb3a | 723 | /** |
24b26d42 | 724 | * handle_percpu_irq - Per CPU local irq handler |
dd87eb3a | 725 | * @desc: the interrupt description structure for this irq |
dd87eb3a TG |
726 | * |
727 | * Per CPU interrupts on SMP machines without locking requirements | |
728 | */ | |
bd0b9ac4 | 729 | void handle_percpu_irq(struct irq_desc *desc) |
dd87eb3a | 730 | { |
35e857cb | 731 | struct irq_chip *chip = irq_desc_get_chip(desc); |
dd87eb3a | 732 | |
b51bf95c | 733 | kstat_incr_irqs_this_cpu(desc); |
dd87eb3a | 734 | |
849f061c TG |
735 | if (chip->irq_ack) |
736 | chip->irq_ack(&desc->irq_data); | |
dd87eb3a | 737 | |
71f64340 | 738 | handle_irq_event_percpu(desc); |
dd87eb3a | 739 | |
849f061c TG |
740 | if (chip->irq_eoi) |
741 | chip->irq_eoi(&desc->irq_data); | |
dd87eb3a TG |
742 | } |
743 | ||
31d9d9b6 MZ |
744 | /** |
745 | * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids | |
31d9d9b6 MZ |
746 | * @desc: the interrupt description structure for this irq |
747 | * | |
748 | * Per CPU interrupts on SMP machines without locking requirements. Same as | |
749 | * handle_percpu_irq() above but with the following extras: | |
750 | * | |
751 | * action->percpu_dev_id is a pointer to percpu variables which | |
752 | * contain the real device id for the cpu on which this handler is | |
753 | * called | |
754 | */ | |
bd0b9ac4 | 755 | void handle_percpu_devid_irq(struct irq_desc *desc) |
31d9d9b6 MZ |
756 | { |
757 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
758 | struct irqaction *action = desc->action; | |
532d0d06 | 759 | void *dev_id = raw_cpu_ptr(action->percpu_dev_id); |
bd0b9ac4 | 760 | unsigned int irq = irq_desc_get_irq(desc); |
31d9d9b6 MZ |
761 | irqreturn_t res; |
762 | ||
b51bf95c | 763 | kstat_incr_irqs_this_cpu(desc); |
31d9d9b6 MZ |
764 | |
765 | if (chip->irq_ack) | |
766 | chip->irq_ack(&desc->irq_data); | |
767 | ||
768 | trace_irq_handler_entry(irq, action); | |
769 | res = action->handler(irq, dev_id); | |
770 | trace_irq_handler_exit(irq, action, res); | |
771 | ||
772 | if (chip->irq_eoi) | |
773 | chip->irq_eoi(&desc->irq_data); | |
774 | } | |
775 | ||
dd87eb3a | 776 | void |
3b0f95be RK |
777 | __irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle, |
778 | int is_chained, const char *name) | |
dd87eb3a | 779 | { |
091738a2 | 780 | if (!handle) { |
dd87eb3a | 781 | handle = handle_bad_irq; |
091738a2 | 782 | } else { |
f86eff22 MZ |
783 | struct irq_data *irq_data = &desc->irq_data; |
784 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
785 | /* | |
786 | * With hierarchical domains we might run into a | |
787 | * situation where the outermost chip is not yet set | |
788 | * up, but the inner chips are there. Instead of | |
789 | * bailing we install the handler, but obviously we | |
790 | * cannot enable/startup the interrupt at this point. | |
791 | */ | |
792 | while (irq_data) { | |
793 | if (irq_data->chip != &no_irq_chip) | |
794 | break; | |
795 | /* | |
796 | * Bail out if the outer chip is not set up | |
797 | * and the interrrupt supposed to be started | |
798 | * right away. | |
799 | */ | |
800 | if (WARN_ON(is_chained)) | |
3b0f95be | 801 | return; |
f86eff22 MZ |
802 | /* Try the parent */ |
803 | irq_data = irq_data->parent_data; | |
804 | } | |
805 | #endif | |
806 | if (WARN_ON(!irq_data || irq_data->chip == &no_irq_chip)) | |
3b0f95be | 807 | return; |
f8b5473f | 808 | } |
dd87eb3a | 809 | |
dd87eb3a TG |
810 | /* Uninstall? */ |
811 | if (handle == handle_bad_irq) { | |
6b8ff312 | 812 | if (desc->irq_data.chip != &no_irq_chip) |
9205e31d | 813 | mask_ack_irq(desc); |
801a0e9a | 814 | irq_state_set_disabled(desc); |
e509bd7d MW |
815 | if (is_chained) |
816 | desc->action = NULL; | |
dd87eb3a TG |
817 | desc->depth = 1; |
818 | } | |
819 | desc->handle_irq = handle; | |
a460e745 | 820 | desc->name = name; |
dd87eb3a TG |
821 | |
822 | if (handle != handle_bad_irq && is_chained) { | |
1ccb4e61 TG |
823 | irq_settings_set_noprobe(desc); |
824 | irq_settings_set_norequest(desc); | |
7f1b1244 | 825 | irq_settings_set_nothread(desc); |
e509bd7d | 826 | desc->action = &chained_action; |
b4bc724e | 827 | irq_startup(desc, true); |
dd87eb3a | 828 | } |
3b0f95be RK |
829 | } |
830 | ||
831 | void | |
832 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, | |
833 | const char *name) | |
834 | { | |
835 | unsigned long flags; | |
836 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0); | |
837 | ||
838 | if (!desc) | |
839 | return; | |
840 | ||
841 | __irq_do_set_handler(desc, handle, is_chained, name); | |
02725e74 | 842 | irq_put_desc_busunlock(desc, flags); |
dd87eb3a | 843 | } |
3836ca08 | 844 | EXPORT_SYMBOL_GPL(__irq_set_handler); |
dd87eb3a | 845 | |
3b0f95be RK |
846 | void |
847 | irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, | |
848 | void *data) | |
849 | { | |
850 | unsigned long flags; | |
851 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0); | |
852 | ||
853 | if (!desc) | |
854 | return; | |
855 | ||
856 | __irq_do_set_handler(desc, handle, 1, NULL); | |
af7080e0 | 857 | desc->irq_common_data.handler_data = data; |
3b0f95be RK |
858 | |
859 | irq_put_desc_busunlock(desc, flags); | |
860 | } | |
861 | EXPORT_SYMBOL_GPL(irq_set_chained_handler_and_data); | |
862 | ||
dd87eb3a | 863 | void |
3836ca08 | 864 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 | 865 | irq_flow_handler_t handle, const char *name) |
dd87eb3a | 866 | { |
35e857cb | 867 | irq_set_chip(irq, chip); |
3836ca08 | 868 | __irq_set_handler(irq, handle, 0, name); |
dd87eb3a | 869 | } |
b3ae66f2 | 870 | EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name); |
46f4f8f6 | 871 | |
44247184 | 872 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
46f4f8f6 | 873 | { |
46f4f8f6 | 874 | unsigned long flags; |
31d9d9b6 | 875 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
46f4f8f6 | 876 | |
44247184 | 877 | if (!desc) |
46f4f8f6 | 878 | return; |
a005677b TG |
879 | irq_settings_clr_and_set(desc, clr, set); |
880 | ||
876dbd4c | 881 | irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | |
e1ef8241 | 882 | IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); |
a005677b TG |
883 | if (irq_settings_has_no_balance_set(desc)) |
884 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | |
885 | if (irq_settings_is_per_cpu(desc)) | |
886 | irqd_set(&desc->irq_data, IRQD_PER_CPU); | |
e1ef8241 TG |
887 | if (irq_settings_can_move_pcntxt(desc)) |
888 | irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); | |
0ef5ca1e TG |
889 | if (irq_settings_is_level(desc)) |
890 | irqd_set(&desc->irq_data, IRQD_LEVEL); | |
a005677b | 891 | |
876dbd4c TG |
892 | irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); |
893 | ||
02725e74 | 894 | irq_put_desc_unlock(desc, flags); |
46f4f8f6 | 895 | } |
edf76f83 | 896 | EXPORT_SYMBOL_GPL(irq_modify_status); |
0fdb4b25 DD |
897 | |
898 | /** | |
899 | * irq_cpu_online - Invoke all irq_cpu_online functions. | |
900 | * | |
901 | * Iterate through all irqs and invoke the chip.irq_cpu_online() | |
902 | * for each. | |
903 | */ | |
904 | void irq_cpu_online(void) | |
905 | { | |
906 | struct irq_desc *desc; | |
907 | struct irq_chip *chip; | |
908 | unsigned long flags; | |
909 | unsigned int irq; | |
910 | ||
911 | for_each_active_irq(irq) { | |
912 | desc = irq_to_desc(irq); | |
913 | if (!desc) | |
914 | continue; | |
915 | ||
916 | raw_spin_lock_irqsave(&desc->lock, flags); | |
917 | ||
918 | chip = irq_data_get_irq_chip(&desc->irq_data); | |
b3d42232 TG |
919 | if (chip && chip->irq_cpu_online && |
920 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | |
32f4125e | 921 | !irqd_irq_disabled(&desc->irq_data))) |
0fdb4b25 DD |
922 | chip->irq_cpu_online(&desc->irq_data); |
923 | ||
924 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
925 | } | |
926 | } | |
927 | ||
928 | /** | |
929 | * irq_cpu_offline - Invoke all irq_cpu_offline functions. | |
930 | * | |
931 | * Iterate through all irqs and invoke the chip.irq_cpu_offline() | |
932 | * for each. | |
933 | */ | |
934 | void irq_cpu_offline(void) | |
935 | { | |
936 | struct irq_desc *desc; | |
937 | struct irq_chip *chip; | |
938 | unsigned long flags; | |
939 | unsigned int irq; | |
940 | ||
941 | for_each_active_irq(irq) { | |
942 | desc = irq_to_desc(irq); | |
943 | if (!desc) | |
944 | continue; | |
945 | ||
946 | raw_spin_lock_irqsave(&desc->lock, flags); | |
947 | ||
948 | chip = irq_data_get_irq_chip(&desc->irq_data); | |
b3d42232 TG |
949 | if (chip && chip->irq_cpu_offline && |
950 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | |
32f4125e | 951 | !irqd_irq_disabled(&desc->irq_data))) |
0fdb4b25 DD |
952 | chip->irq_cpu_offline(&desc->irq_data); |
953 | ||
954 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
955 | } | |
956 | } | |
85f08c17 JL |
957 | |
958 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
3cfeffc2 SA |
959 | /** |
960 | * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if | |
961 | * NULL) | |
962 | * @data: Pointer to interrupt specific data | |
963 | */ | |
964 | void irq_chip_enable_parent(struct irq_data *data) | |
965 | { | |
966 | data = data->parent_data; | |
967 | if (data->chip->irq_enable) | |
968 | data->chip->irq_enable(data); | |
969 | else | |
970 | data->chip->irq_unmask(data); | |
971 | } | |
972 | ||
973 | /** | |
974 | * irq_chip_disable_parent - Disable the parent interrupt (defaults to mask if | |
975 | * NULL) | |
976 | * @data: Pointer to interrupt specific data | |
977 | */ | |
978 | void irq_chip_disable_parent(struct irq_data *data) | |
979 | { | |
980 | data = data->parent_data; | |
981 | if (data->chip->irq_disable) | |
982 | data->chip->irq_disable(data); | |
983 | else | |
984 | data->chip->irq_mask(data); | |
985 | } | |
986 | ||
85f08c17 JL |
987 | /** |
988 | * irq_chip_ack_parent - Acknowledge the parent interrupt | |
989 | * @data: Pointer to interrupt specific data | |
990 | */ | |
991 | void irq_chip_ack_parent(struct irq_data *data) | |
992 | { | |
993 | data = data->parent_data; | |
994 | data->chip->irq_ack(data); | |
995 | } | |
a4289dc2 | 996 | EXPORT_SYMBOL_GPL(irq_chip_ack_parent); |
85f08c17 | 997 | |
56e8abab YC |
998 | /** |
999 | * irq_chip_mask_parent - Mask the parent interrupt | |
1000 | * @data: Pointer to interrupt specific data | |
1001 | */ | |
1002 | void irq_chip_mask_parent(struct irq_data *data) | |
1003 | { | |
1004 | data = data->parent_data; | |
1005 | data->chip->irq_mask(data); | |
1006 | } | |
52b2a05f | 1007 | EXPORT_SYMBOL_GPL(irq_chip_mask_parent); |
56e8abab YC |
1008 | |
1009 | /** | |
1010 | * irq_chip_unmask_parent - Unmask the parent interrupt | |
1011 | * @data: Pointer to interrupt specific data | |
1012 | */ | |
1013 | void irq_chip_unmask_parent(struct irq_data *data) | |
1014 | { | |
1015 | data = data->parent_data; | |
1016 | data->chip->irq_unmask(data); | |
1017 | } | |
52b2a05f | 1018 | EXPORT_SYMBOL_GPL(irq_chip_unmask_parent); |
56e8abab YC |
1019 | |
1020 | /** | |
1021 | * irq_chip_eoi_parent - Invoke EOI on the parent interrupt | |
1022 | * @data: Pointer to interrupt specific data | |
1023 | */ | |
1024 | void irq_chip_eoi_parent(struct irq_data *data) | |
1025 | { | |
1026 | data = data->parent_data; | |
1027 | data->chip->irq_eoi(data); | |
1028 | } | |
52b2a05f | 1029 | EXPORT_SYMBOL_GPL(irq_chip_eoi_parent); |
56e8abab YC |
1030 | |
1031 | /** | |
1032 | * irq_chip_set_affinity_parent - Set affinity on the parent interrupt | |
1033 | * @data: Pointer to interrupt specific data | |
1034 | * @dest: The affinity mask to set | |
1035 | * @force: Flag to enforce setting (disable online checks) | |
1036 | * | |
1037 | * Conditinal, as the underlying parent chip might not implement it. | |
1038 | */ | |
1039 | int irq_chip_set_affinity_parent(struct irq_data *data, | |
1040 | const struct cpumask *dest, bool force) | |
1041 | { | |
1042 | data = data->parent_data; | |
1043 | if (data->chip->irq_set_affinity) | |
1044 | return data->chip->irq_set_affinity(data, dest, force); | |
b7560de1 GS |
1045 | |
1046 | return -ENOSYS; | |
1047 | } | |
1048 | ||
1049 | /** | |
1050 | * irq_chip_set_type_parent - Set IRQ type on the parent interrupt | |
1051 | * @data: Pointer to interrupt specific data | |
1052 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h | |
1053 | * | |
1054 | * Conditional, as the underlying parent chip might not implement it. | |
1055 | */ | |
1056 | int irq_chip_set_type_parent(struct irq_data *data, unsigned int type) | |
1057 | { | |
1058 | data = data->parent_data; | |
1059 | ||
1060 | if (data->chip->irq_set_type) | |
1061 | return data->chip->irq_set_type(data, type); | |
56e8abab YC |
1062 | |
1063 | return -ENOSYS; | |
1064 | } | |
52b2a05f | 1065 | EXPORT_SYMBOL_GPL(irq_chip_set_type_parent); |
56e8abab | 1066 | |
85f08c17 JL |
1067 | /** |
1068 | * irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware | |
1069 | * @data: Pointer to interrupt specific data | |
1070 | * | |
1071 | * Iterate through the domain hierarchy of the interrupt and check | |
1072 | * whether a hw retrigger function exists. If yes, invoke it. | |
1073 | */ | |
1074 | int irq_chip_retrigger_hierarchy(struct irq_data *data) | |
1075 | { | |
1076 | for (data = data->parent_data; data; data = data->parent_data) | |
1077 | if (data->chip && data->chip->irq_retrigger) | |
1078 | return data->chip->irq_retrigger(data); | |
1079 | ||
6d4affea | 1080 | return 0; |
85f08c17 | 1081 | } |
08b55e2a | 1082 | |
0a4377de JL |
1083 | /** |
1084 | * irq_chip_set_vcpu_affinity_parent - Set vcpu affinity on the parent interrupt | |
1085 | * @data: Pointer to interrupt specific data | |
8505a81b | 1086 | * @vcpu_info: The vcpu affinity information |
0a4377de JL |
1087 | */ |
1088 | int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info) | |
1089 | { | |
1090 | data = data->parent_data; | |
1091 | if (data->chip->irq_set_vcpu_affinity) | |
1092 | return data->chip->irq_set_vcpu_affinity(data, vcpu_info); | |
1093 | ||
1094 | return -ENOSYS; | |
1095 | } | |
1096 | ||
08b55e2a MZ |
1097 | /** |
1098 | * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt | |
1099 | * @data: Pointer to interrupt specific data | |
1100 | * @on: Whether to set or reset the wake-up capability of this irq | |
1101 | * | |
1102 | * Conditional, as the underlying parent chip might not implement it. | |
1103 | */ | |
1104 | int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on) | |
1105 | { | |
1106 | data = data->parent_data; | |
1107 | if (data->chip->irq_set_wake) | |
1108 | return data->chip->irq_set_wake(data, on); | |
1109 | ||
1110 | return -ENOSYS; | |
1111 | } | |
85f08c17 | 1112 | #endif |
515085ef JL |
1113 | |
1114 | /** | |
1115 | * irq_chip_compose_msi_msg - Componse msi message for a irq chip | |
1116 | * @data: Pointer to interrupt specific data | |
1117 | * @msg: Pointer to the MSI message | |
1118 | * | |
1119 | * For hierarchical domains we find the first chip in the hierarchy | |
1120 | * which implements the irq_compose_msi_msg callback. For non | |
1121 | * hierarchical we use the top level chip. | |
1122 | */ | |
1123 | int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) | |
1124 | { | |
1125 | struct irq_data *pos = NULL; | |
1126 | ||
1127 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
1128 | for (; data; data = data->parent_data) | |
1129 | #endif | |
1130 | if (data->chip && data->chip->irq_compose_msi_msg) | |
1131 | pos = data; | |
1132 | if (!pos) | |
1133 | return -ENOSYS; | |
1134 | ||
1135 | pos->chip->irq_compose_msi_msg(pos, msg); | |
1136 | ||
1137 | return 0; | |
1138 | } | |
be45beb2 JH |
1139 | |
1140 | /** | |
1141 | * irq_chip_pm_get - Enable power for an IRQ chip | |
1142 | * @data: Pointer to interrupt specific data | |
1143 | * | |
1144 | * Enable the power to the IRQ chip referenced by the interrupt data | |
1145 | * structure. | |
1146 | */ | |
1147 | int irq_chip_pm_get(struct irq_data *data) | |
1148 | { | |
1149 | int retval; | |
1150 | ||
1151 | if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) { | |
1152 | retval = pm_runtime_get_sync(data->chip->parent_device); | |
1153 | if (retval < 0) { | |
1154 | pm_runtime_put_noidle(data->chip->parent_device); | |
1155 | return retval; | |
1156 | } | |
1157 | } | |
1158 | ||
1159 | return 0; | |
1160 | } | |
1161 | ||
1162 | /** | |
1163 | * irq_chip_pm_put - Disable power for an IRQ chip | |
1164 | * @data: Pointer to interrupt specific data | |
1165 | * | |
1166 | * Disable the power to the IRQ chip referenced by the interrupt data | |
1167 | * structure, belongs. Note that power will only be disabled, once this | |
1168 | * function has been called for all IRQs that have called irq_chip_pm_get(). | |
1169 | */ | |
1170 | int irq_chip_pm_put(struct irq_data *data) | |
1171 | { | |
1172 | int retval = 0; | |
1173 | ||
1174 | if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) | |
1175 | retval = pm_runtime_put(data->chip->parent_device); | |
1176 | ||
1177 | return (retval < 0) ? retval : 0; | |
1178 | } |