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Commit | Line | Data |
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dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
18 | ||
19 | #include "internals.h" | |
20 | ||
ced5b697 | 21 | static void dynamic_irq_init_x(unsigned int irq, bool keep_chip_data) |
3a16d713 | 22 | { |
0b8f1efa | 23 | struct irq_desc *desc; |
3a16d713 EB |
24 | unsigned long flags; |
25 | ||
0b8f1efa | 26 | desc = irq_to_desc(irq); |
7d94f7ca | 27 | if (!desc) { |
261c40c1 | 28 | WARN(1, KERN_ERR "Trying to initialize invalid IRQ%d\n", irq); |
3a16d713 EB |
29 | return; |
30 | } | |
31 | ||
32 | /* Ensure we don't have left over values from a previous use of this irq */ | |
239007b8 | 33 | raw_spin_lock_irqsave(&desc->lock, flags); |
3a16d713 EB |
34 | desc->status = IRQ_DISABLED; |
35 | desc->chip = &no_irq_chip; | |
36 | desc->handle_irq = handle_bad_irq; | |
37 | desc->depth = 1; | |
5b912c10 | 38 | desc->msi_desc = NULL; |
3a16d713 | 39 | desc->handler_data = NULL; |
ced5b697 BP |
40 | if (!keep_chip_data) |
41 | desc->chip_data = NULL; | |
3a16d713 EB |
42 | desc->action = NULL; |
43 | desc->irq_count = 0; | |
44 | desc->irqs_unhandled = 0; | |
45 | #ifdef CONFIG_SMP | |
7f7ace0c MT |
46 | cpumask_setall(desc->affinity); |
47 | #ifdef CONFIG_GENERIC_PENDING_IRQ | |
48 | cpumask_clear(desc->pending_mask); | |
49 | #endif | |
3a16d713 | 50 | #endif |
239007b8 | 51 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3a16d713 EB |
52 | } |
53 | ||
54 | /** | |
ced5b697 | 55 | * dynamic_irq_init - initialize a dynamically allocated irq |
3a16d713 EB |
56 | * @irq: irq number to initialize |
57 | */ | |
ced5b697 BP |
58 | void dynamic_irq_init(unsigned int irq) |
59 | { | |
60 | dynamic_irq_init_x(irq, false); | |
61 | } | |
62 | ||
63 | /** | |
64 | * dynamic_irq_init_keep_chip_data - initialize a dynamically allocated irq | |
65 | * @irq: irq number to initialize | |
66 | * | |
67 | * does not set irq_to_desc(irq)->chip_data to NULL | |
68 | */ | |
69 | void dynamic_irq_init_keep_chip_data(unsigned int irq) | |
70 | { | |
71 | dynamic_irq_init_x(irq, true); | |
72 | } | |
73 | ||
74 | static void dynamic_irq_cleanup_x(unsigned int irq, bool keep_chip_data) | |
3a16d713 | 75 | { |
d3c60047 | 76 | struct irq_desc *desc = irq_to_desc(irq); |
3a16d713 EB |
77 | unsigned long flags; |
78 | ||
7d94f7ca | 79 | if (!desc) { |
261c40c1 | 80 | WARN(1, KERN_ERR "Trying to cleanup invalid IRQ%d\n", irq); |
3a16d713 EB |
81 | return; |
82 | } | |
83 | ||
239007b8 | 84 | raw_spin_lock_irqsave(&desc->lock, flags); |
1f80025e | 85 | if (desc->action) { |
239007b8 | 86 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
261c40c1 | 87 | WARN(1, KERN_ERR "Destroying IRQ%d without calling free_irq\n", |
1f80025e | 88 | irq); |
1f80025e EB |
89 | return; |
90 | } | |
5b912c10 EB |
91 | desc->msi_desc = NULL; |
92 | desc->handler_data = NULL; | |
ced5b697 BP |
93 | if (!keep_chip_data) |
94 | desc->chip_data = NULL; | |
3a16d713 EB |
95 | desc->handle_irq = handle_bad_irq; |
96 | desc->chip = &no_irq_chip; | |
b6f3b780 | 97 | desc->name = NULL; |
0f3c2a89 | 98 | clear_kstat_irqs(desc); |
239007b8 | 99 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3a16d713 EB |
100 | } |
101 | ||
ced5b697 BP |
102 | /** |
103 | * dynamic_irq_cleanup - cleanup a dynamically allocated irq | |
104 | * @irq: irq number to initialize | |
105 | */ | |
106 | void dynamic_irq_cleanup(unsigned int irq) | |
107 | { | |
108 | dynamic_irq_cleanup_x(irq, false); | |
109 | } | |
110 | ||
111 | /** | |
112 | * dynamic_irq_cleanup_keep_chip_data - cleanup a dynamically allocated irq | |
113 | * @irq: irq number to initialize | |
114 | * | |
115 | * does not set irq_to_desc(irq)->chip_data to NULL | |
116 | */ | |
117 | void dynamic_irq_cleanup_keep_chip_data(unsigned int irq) | |
118 | { | |
119 | dynamic_irq_cleanup_x(irq, true); | |
120 | } | |
121 | ||
3a16d713 | 122 | |
dd87eb3a TG |
123 | /** |
124 | * set_irq_chip - set the irq chip for an irq | |
125 | * @irq: irq number | |
126 | * @chip: pointer to irq chip description structure | |
127 | */ | |
128 | int set_irq_chip(unsigned int irq, struct irq_chip *chip) | |
129 | { | |
d3c60047 | 130 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
131 | unsigned long flags; |
132 | ||
7d94f7ca | 133 | if (!desc) { |
261c40c1 | 134 | WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq); |
dd87eb3a TG |
135 | return -EINVAL; |
136 | } | |
137 | ||
138 | if (!chip) | |
139 | chip = &no_irq_chip; | |
140 | ||
239007b8 | 141 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a TG |
142 | irq_chip_set_defaults(chip); |
143 | desc->chip = chip; | |
239007b8 | 144 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
145 | |
146 | return 0; | |
147 | } | |
148 | EXPORT_SYMBOL(set_irq_chip); | |
149 | ||
150 | /** | |
0c5d1eb7 | 151 | * set_irq_type - set the irq trigger type for an irq |
dd87eb3a | 152 | * @irq: irq number |
0c5d1eb7 | 153 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a TG |
154 | */ |
155 | int set_irq_type(unsigned int irq, unsigned int type) | |
156 | { | |
d3c60047 | 157 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
158 | unsigned long flags; |
159 | int ret = -ENXIO; | |
160 | ||
7d94f7ca | 161 | if (!desc) { |
dd87eb3a TG |
162 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); |
163 | return -ENODEV; | |
164 | } | |
165 | ||
f2b662da | 166 | type &= IRQ_TYPE_SENSE_MASK; |
0c5d1eb7 DB |
167 | if (type == IRQ_TYPE_NONE) |
168 | return 0; | |
169 | ||
239007b8 | 170 | raw_spin_lock_irqsave(&desc->lock, flags); |
0b3682ba | 171 | ret = __irq_set_trigger(desc, irq, type); |
239007b8 | 172 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
173 | return ret; |
174 | } | |
175 | EXPORT_SYMBOL(set_irq_type); | |
176 | ||
177 | /** | |
178 | * set_irq_data - set irq type data for an irq | |
179 | * @irq: Interrupt number | |
180 | * @data: Pointer to interrupt specific data | |
181 | * | |
182 | * Set the hardware irq controller data for an irq | |
183 | */ | |
184 | int set_irq_data(unsigned int irq, void *data) | |
185 | { | |
d3c60047 | 186 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
187 | unsigned long flags; |
188 | ||
7d94f7ca | 189 | if (!desc) { |
dd87eb3a TG |
190 | printk(KERN_ERR |
191 | "Trying to install controller data for IRQ%d\n", irq); | |
192 | return -EINVAL; | |
193 | } | |
194 | ||
239007b8 | 195 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a | 196 | desc->handler_data = data; |
239007b8 | 197 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
198 | return 0; |
199 | } | |
200 | EXPORT_SYMBOL(set_irq_data); | |
201 | ||
5b912c10 | 202 | /** |
24b26d42 | 203 | * set_irq_msi - set MSI descriptor data for an irq |
5b912c10 | 204 | * @irq: Interrupt number |
472900b8 | 205 | * @entry: Pointer to MSI descriptor data |
5b912c10 | 206 | * |
24b26d42 | 207 | * Set the MSI descriptor entry for an irq |
5b912c10 EB |
208 | */ |
209 | int set_irq_msi(unsigned int irq, struct msi_desc *entry) | |
210 | { | |
d3c60047 | 211 | struct irq_desc *desc = irq_to_desc(irq); |
5b912c10 EB |
212 | unsigned long flags; |
213 | ||
7d94f7ca | 214 | if (!desc) { |
5b912c10 EB |
215 | printk(KERN_ERR |
216 | "Trying to install msi data for IRQ%d\n", irq); | |
217 | return -EINVAL; | |
218 | } | |
7d94f7ca | 219 | |
239007b8 | 220 | raw_spin_lock_irqsave(&desc->lock, flags); |
5b912c10 | 221 | desc->msi_desc = entry; |
7fe3730d ME |
222 | if (entry) |
223 | entry->irq = irq; | |
239007b8 | 224 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
5b912c10 EB |
225 | return 0; |
226 | } | |
227 | ||
dd87eb3a TG |
228 | /** |
229 | * set_irq_chip_data - set irq chip data for an irq | |
230 | * @irq: Interrupt number | |
231 | * @data: Pointer to chip specific data | |
232 | * | |
233 | * Set the hardware irq chip data for an irq | |
234 | */ | |
235 | int set_irq_chip_data(unsigned int irq, void *data) | |
236 | { | |
d3c60047 | 237 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
238 | unsigned long flags; |
239 | ||
7d94f7ca YL |
240 | if (!desc) { |
241 | printk(KERN_ERR | |
242 | "Trying to install chip data for IRQ%d\n", irq); | |
243 | return -EINVAL; | |
244 | } | |
245 | ||
246 | if (!desc->chip) { | |
dd87eb3a TG |
247 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); |
248 | return -EINVAL; | |
249 | } | |
250 | ||
239007b8 | 251 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a | 252 | desc->chip_data = data; |
239007b8 | 253 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
dd87eb3a TG |
254 | |
255 | return 0; | |
256 | } | |
257 | EXPORT_SYMBOL(set_irq_chip_data); | |
258 | ||
399b5da2 TG |
259 | /** |
260 | * set_irq_nested_thread - Set/Reset the IRQ_NESTED_THREAD flag of an irq | |
261 | * | |
262 | * @irq: Interrupt number | |
263 | * @nest: 0 to clear / 1 to set the IRQ_NESTED_THREAD flag | |
264 | * | |
265 | * The IRQ_NESTED_THREAD flag indicates that on | |
266 | * request_threaded_irq() no separate interrupt thread should be | |
267 | * created for the irq as the handler are called nested in the | |
268 | * context of a demultiplexing interrupt handler thread. | |
269 | */ | |
270 | void set_irq_nested_thread(unsigned int irq, int nest) | |
271 | { | |
272 | struct irq_desc *desc = irq_to_desc(irq); | |
273 | unsigned long flags; | |
274 | ||
275 | if (!desc) | |
276 | return; | |
277 | ||
239007b8 | 278 | raw_spin_lock_irqsave(&desc->lock, flags); |
399b5da2 TG |
279 | if (nest) |
280 | desc->status |= IRQ_NESTED_THREAD; | |
281 | else | |
282 | desc->status &= ~IRQ_NESTED_THREAD; | |
239007b8 | 283 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
399b5da2 TG |
284 | } |
285 | EXPORT_SYMBOL_GPL(set_irq_nested_thread); | |
286 | ||
dd87eb3a TG |
287 | /* |
288 | * default enable function | |
289 | */ | |
290 | static void default_enable(unsigned int irq) | |
291 | { | |
d3c60047 | 292 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
293 | |
294 | desc->chip->unmask(irq); | |
295 | desc->status &= ~IRQ_MASKED; | |
296 | } | |
297 | ||
298 | /* | |
299 | * default disable function | |
300 | */ | |
301 | static void default_disable(unsigned int irq) | |
302 | { | |
dd87eb3a TG |
303 | } |
304 | ||
305 | /* | |
306 | * default startup function | |
307 | */ | |
308 | static unsigned int default_startup(unsigned int irq) | |
309 | { | |
d3c60047 | 310 | struct irq_desc *desc = irq_to_desc(irq); |
08678b08 | 311 | |
08678b08 | 312 | desc->chip->enable(irq); |
dd87eb3a TG |
313 | return 0; |
314 | } | |
315 | ||
89d694b9 TG |
316 | /* |
317 | * default shutdown function | |
318 | */ | |
319 | static void default_shutdown(unsigned int irq) | |
320 | { | |
d3c60047 | 321 | struct irq_desc *desc = irq_to_desc(irq); |
89d694b9 TG |
322 | |
323 | desc->chip->mask(irq); | |
324 | desc->status |= IRQ_MASKED; | |
325 | } | |
326 | ||
dd87eb3a TG |
327 | /* |
328 | * Fixup enable/disable function pointers | |
329 | */ | |
330 | void irq_chip_set_defaults(struct irq_chip *chip) | |
331 | { | |
332 | if (!chip->enable) | |
333 | chip->enable = default_enable; | |
334 | if (!chip->disable) | |
335 | chip->disable = default_disable; | |
336 | if (!chip->startup) | |
337 | chip->startup = default_startup; | |
89d694b9 TG |
338 | /* |
339 | * We use chip->disable, when the user provided its own. When | |
340 | * we have default_disable set for chip->disable, then we need | |
341 | * to use default_shutdown, otherwise the irq line is not | |
342 | * disabled on free_irq(): | |
343 | */ | |
dd87eb3a | 344 | if (!chip->shutdown) |
89d694b9 TG |
345 | chip->shutdown = chip->disable != default_disable ? |
346 | chip->disable : default_shutdown; | |
b86432b4 ZY |
347 | if (!chip->end) |
348 | chip->end = dummy_irq_chip.end; | |
dd87eb3a TG |
349 | } |
350 | ||
351 | static inline void mask_ack_irq(struct irq_desc *desc, int irq) | |
352 | { | |
353 | if (desc->chip->mask_ack) | |
354 | desc->chip->mask_ack(irq); | |
355 | else { | |
356 | desc->chip->mask(irq); | |
efdc64f0 WC |
357 | if (desc->chip->ack) |
358 | desc->chip->ack(irq); | |
dd87eb3a | 359 | } |
0b1adaa0 TG |
360 | desc->status |= IRQ_MASKED; |
361 | } | |
362 | ||
363 | static inline void mask_irq(struct irq_desc *desc, int irq) | |
364 | { | |
365 | if (desc->chip->mask) { | |
366 | desc->chip->mask(irq); | |
367 | desc->status |= IRQ_MASKED; | |
368 | } | |
369 | } | |
370 | ||
371 | static inline void unmask_irq(struct irq_desc *desc, int irq) | |
372 | { | |
373 | if (desc->chip->unmask) { | |
374 | desc->chip->unmask(irq); | |
375 | desc->status &= ~IRQ_MASKED; | |
376 | } | |
dd87eb3a TG |
377 | } |
378 | ||
399b5da2 TG |
379 | /* |
380 | * handle_nested_irq - Handle a nested irq from a irq thread | |
381 | * @irq: the interrupt number | |
382 | * | |
383 | * Handle interrupts which are nested into a threaded interrupt | |
384 | * handler. The handler function is called inside the calling | |
385 | * threads context. | |
386 | */ | |
387 | void handle_nested_irq(unsigned int irq) | |
388 | { | |
389 | struct irq_desc *desc = irq_to_desc(irq); | |
390 | struct irqaction *action; | |
391 | irqreturn_t action_ret; | |
392 | ||
393 | might_sleep(); | |
394 | ||
239007b8 | 395 | raw_spin_lock_irq(&desc->lock); |
399b5da2 TG |
396 | |
397 | kstat_incr_irqs_this_cpu(irq, desc); | |
398 | ||
399 | action = desc->action; | |
400 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) | |
401 | goto out_unlock; | |
402 | ||
403 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 404 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
405 | |
406 | action_ret = action->thread_fn(action->irq, action->dev_id); | |
407 | if (!noirqdebug) | |
408 | note_interrupt(irq, desc, action_ret); | |
409 | ||
239007b8 | 410 | raw_spin_lock_irq(&desc->lock); |
399b5da2 TG |
411 | desc->status &= ~IRQ_INPROGRESS; |
412 | ||
413 | out_unlock: | |
239007b8 | 414 | raw_spin_unlock_irq(&desc->lock); |
399b5da2 TG |
415 | } |
416 | EXPORT_SYMBOL_GPL(handle_nested_irq); | |
417 | ||
dd87eb3a TG |
418 | /** |
419 | * handle_simple_irq - Simple and software-decoded IRQs. | |
420 | * @irq: the interrupt number | |
421 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
422 | * |
423 | * Simple interrupts are either sent from a demultiplexing interrupt | |
424 | * handler or come from hardware, where no interrupt hardware control | |
425 | * is necessary. | |
426 | * | |
427 | * Note: The caller is expected to handle the ack, clear, mask and | |
428 | * unmask issues if necessary. | |
429 | */ | |
7ad5b3a5 | 430 | void |
7d12e780 | 431 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
432 | { |
433 | struct irqaction *action; | |
434 | irqreturn_t action_ret; | |
dd87eb3a | 435 | |
239007b8 | 436 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
437 | |
438 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
439 | goto out_unlock; | |
971e5b35 | 440 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
d6c88a50 | 441 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
442 | |
443 | action = desc->action; | |
971e5b35 | 444 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
dd87eb3a TG |
445 | goto out_unlock; |
446 | ||
447 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 448 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 449 | |
7d12e780 | 450 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 451 | if (!noirqdebug) |
7d12e780 | 452 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 453 | |
239007b8 | 454 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
455 | desc->status &= ~IRQ_INPROGRESS; |
456 | out_unlock: | |
239007b8 | 457 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
458 | } |
459 | ||
460 | /** | |
461 | * handle_level_irq - Level type irq handler | |
462 | * @irq: the interrupt number | |
463 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
464 | * |
465 | * Level type interrupts are active as long as the hardware line has | |
466 | * the active level. This may require to mask the interrupt and unmask | |
467 | * it after the associated handler has acknowledged the device, so the | |
468 | * interrupt line is back to inactive. | |
469 | */ | |
7ad5b3a5 | 470 | void |
7d12e780 | 471 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 472 | { |
dd87eb3a TG |
473 | struct irqaction *action; |
474 | irqreturn_t action_ret; | |
475 | ||
239007b8 | 476 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
477 | mask_ack_irq(desc, irq); |
478 | ||
479 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
86998aa6 | 480 | goto out_unlock; |
dd87eb3a | 481 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
d6c88a50 | 482 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
483 | |
484 | /* | |
485 | * If its disabled or no action available | |
486 | * keep it masked and get out of here | |
487 | */ | |
488 | action = desc->action; | |
49663421 | 489 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
86998aa6 | 490 | goto out_unlock; |
dd87eb3a TG |
491 | |
492 | desc->status |= IRQ_INPROGRESS; | |
239007b8 | 493 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 494 | |
7d12e780 | 495 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 496 | if (!noirqdebug) |
7d12e780 | 497 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 498 | |
239007b8 | 499 | raw_spin_lock(&desc->lock); |
dd87eb3a | 500 | desc->status &= ~IRQ_INPROGRESS; |
b25c340c | 501 | |
0b1adaa0 TG |
502 | if (!(desc->status & (IRQ_DISABLED | IRQ_ONESHOT))) |
503 | unmask_irq(desc, irq); | |
86998aa6 | 504 | out_unlock: |
239007b8 | 505 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 506 | } |
14819ea1 | 507 | EXPORT_SYMBOL_GPL(handle_level_irq); |
dd87eb3a TG |
508 | |
509 | /** | |
47c2a3aa | 510 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
511 | * @irq: the interrupt number |
512 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 513 | * |
47c2a3aa | 514 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
515 | * call when the interrupt has been serviced. This enables support |
516 | * for modern forms of interrupt handlers, which handle the flow | |
517 | * details in hardware, transparently. | |
518 | */ | |
7ad5b3a5 | 519 | void |
7d12e780 | 520 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 521 | { |
dd87eb3a TG |
522 | struct irqaction *action; |
523 | irqreturn_t action_ret; | |
524 | ||
239007b8 | 525 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
526 | |
527 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
528 | goto out; | |
529 | ||
530 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
d6c88a50 | 531 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
532 | |
533 | /* | |
534 | * If its disabled or no action available | |
76d21601 | 535 | * then mask it and get out of here: |
dd87eb3a TG |
536 | */ |
537 | action = desc->action; | |
98bb244b BH |
538 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
539 | desc->status |= IRQ_PENDING; | |
0b1adaa0 | 540 | mask_irq(desc, irq); |
dd87eb3a | 541 | goto out; |
98bb244b | 542 | } |
dd87eb3a TG |
543 | |
544 | desc->status |= IRQ_INPROGRESS; | |
98bb244b | 545 | desc->status &= ~IRQ_PENDING; |
239007b8 | 546 | raw_spin_unlock(&desc->lock); |
dd87eb3a | 547 | |
7d12e780 | 548 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 549 | if (!noirqdebug) |
7d12e780 | 550 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 551 | |
239007b8 | 552 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
553 | desc->status &= ~IRQ_INPROGRESS; |
554 | out: | |
47c2a3aa | 555 | desc->chip->eoi(irq); |
dd87eb3a | 556 | |
239007b8 | 557 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
558 | } |
559 | ||
560 | /** | |
561 | * handle_edge_irq - edge type IRQ handler | |
562 | * @irq: the interrupt number | |
563 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
564 | * |
565 | * Interrupt occures on the falling and/or rising edge of a hardware | |
566 | * signal. The occurence is latched into the irq controller hardware | |
567 | * and must be acked in order to be reenabled. After the ack another | |
568 | * interrupt can happen on the same source even before the first one | |
dfff0615 | 569 | * is handled by the associated event handler. If this happens it |
dd87eb3a TG |
570 | * might be necessary to disable (mask) the interrupt depending on the |
571 | * controller hardware. This requires to reenable the interrupt inside | |
572 | * of the loop which handles the interrupts which have arrived while | |
573 | * the handler was running. If all pending interrupts are handled, the | |
574 | * loop is left. | |
575 | */ | |
7ad5b3a5 | 576 | void |
7d12e780 | 577 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 578 | { |
239007b8 | 579 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
580 | |
581 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
582 | ||
583 | /* | |
584 | * If we're currently running this IRQ, or its disabled, | |
585 | * we shouldn't process the IRQ. Mark it pending, handle | |
586 | * the necessary masking and go out | |
587 | */ | |
588 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || | |
589 | !desc->action)) { | |
590 | desc->status |= (IRQ_PENDING | IRQ_MASKED); | |
591 | mask_ack_irq(desc, irq); | |
592 | goto out_unlock; | |
593 | } | |
d6c88a50 | 594 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
595 | |
596 | /* Start handling the irq */ | |
4dbc9ca2 TG |
597 | if (desc->chip->ack) |
598 | desc->chip->ack(irq); | |
dd87eb3a TG |
599 | |
600 | /* Mark the IRQ currently in progress.*/ | |
601 | desc->status |= IRQ_INPROGRESS; | |
602 | ||
603 | do { | |
604 | struct irqaction *action = desc->action; | |
605 | irqreturn_t action_ret; | |
606 | ||
607 | if (unlikely(!action)) { | |
0b1adaa0 | 608 | mask_irq(desc, irq); |
dd87eb3a TG |
609 | goto out_unlock; |
610 | } | |
611 | ||
612 | /* | |
613 | * When another irq arrived while we were handling | |
614 | * one, we could have masked the irq. | |
615 | * Renable it, if it was not disabled in meantime. | |
616 | */ | |
617 | if (unlikely((desc->status & | |
618 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == | |
619 | (IRQ_PENDING | IRQ_MASKED))) { | |
0b1adaa0 | 620 | unmask_irq(desc, irq); |
dd87eb3a TG |
621 | } |
622 | ||
623 | desc->status &= ~IRQ_PENDING; | |
239007b8 | 624 | raw_spin_unlock(&desc->lock); |
7d12e780 | 625 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 626 | if (!noirqdebug) |
7d12e780 | 627 | note_interrupt(irq, desc, action_ret); |
239007b8 | 628 | raw_spin_lock(&desc->lock); |
dd87eb3a TG |
629 | |
630 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); | |
631 | ||
632 | desc->status &= ~IRQ_INPROGRESS; | |
633 | out_unlock: | |
239007b8 | 634 | raw_spin_unlock(&desc->lock); |
dd87eb3a TG |
635 | } |
636 | ||
dd87eb3a | 637 | /** |
24b26d42 | 638 | * handle_percpu_irq - Per CPU local irq handler |
dd87eb3a TG |
639 | * @irq: the interrupt number |
640 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
641 | * |
642 | * Per CPU interrupts on SMP machines without locking requirements | |
643 | */ | |
7ad5b3a5 | 644 | void |
7d12e780 | 645 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
646 | { |
647 | irqreturn_t action_ret; | |
648 | ||
d6c88a50 | 649 | kstat_incr_irqs_this_cpu(irq, desc); |
dd87eb3a TG |
650 | |
651 | if (desc->chip->ack) | |
652 | desc->chip->ack(irq); | |
653 | ||
7d12e780 | 654 | action_ret = handle_IRQ_event(irq, desc->action); |
dd87eb3a | 655 | if (!noirqdebug) |
7d12e780 | 656 | note_interrupt(irq, desc, action_ret); |
dd87eb3a | 657 | |
fcef5911 | 658 | if (desc->chip->eoi) |
dd87eb3a TG |
659 | desc->chip->eoi(irq); |
660 | } | |
661 | ||
dd87eb3a | 662 | void |
a460e745 IM |
663 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
664 | const char *name) | |
dd87eb3a | 665 | { |
d3c60047 | 666 | struct irq_desc *desc = irq_to_desc(irq); |
dd87eb3a TG |
667 | unsigned long flags; |
668 | ||
7d94f7ca | 669 | if (!desc) { |
dd87eb3a TG |
670 | printk(KERN_ERR |
671 | "Trying to install type control for IRQ%d\n", irq); | |
672 | return; | |
673 | } | |
674 | ||
dd87eb3a TG |
675 | if (!handle) |
676 | handle = handle_bad_irq; | |
9d7ac8be | 677 | else if (desc->chip == &no_irq_chip) { |
f8b5473f | 678 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
b039db8e | 679 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
f8b5473f TG |
680 | /* |
681 | * Some ARM implementations install a handler for really dumb | |
682 | * interrupt hardware without setting an irq_chip. This worked | |
683 | * with the ARM no_irq_chip but the check in setup_irq would | |
684 | * prevent us to setup the interrupt at all. Switch it to | |
685 | * dummy_irq_chip for easy transition. | |
686 | */ | |
687 | desc->chip = &dummy_irq_chip; | |
688 | } | |
dd87eb3a | 689 | |
70aedd24 | 690 | chip_bus_lock(irq, desc); |
239007b8 | 691 | raw_spin_lock_irqsave(&desc->lock, flags); |
dd87eb3a TG |
692 | |
693 | /* Uninstall? */ | |
694 | if (handle == handle_bad_irq) { | |
fcef5911 | 695 | if (desc->chip != &no_irq_chip) |
5575ddf7 | 696 | mask_ack_irq(desc, irq); |
dd87eb3a TG |
697 | desc->status |= IRQ_DISABLED; |
698 | desc->depth = 1; | |
699 | } | |
700 | desc->handle_irq = handle; | |
a460e745 | 701 | desc->name = name; |
dd87eb3a TG |
702 | |
703 | if (handle != handle_bad_irq && is_chained) { | |
704 | desc->status &= ~IRQ_DISABLED; | |
705 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; | |
706 | desc->depth = 0; | |
7e6e178a | 707 | desc->chip->startup(irq); |
dd87eb3a | 708 | } |
239007b8 | 709 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
70aedd24 | 710 | chip_bus_sync_unlock(irq, desc); |
dd87eb3a | 711 | } |
14819ea1 | 712 | EXPORT_SYMBOL_GPL(__set_irq_handler); |
dd87eb3a TG |
713 | |
714 | void | |
715 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
57a58a94 | 716 | irq_flow_handler_t handle) |
dd87eb3a TG |
717 | { |
718 | set_irq_chip(irq, chip); | |
a460e745 | 719 | __set_irq_handler(irq, handle, 0, NULL); |
dd87eb3a TG |
720 | } |
721 | ||
a460e745 IM |
722 | void |
723 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | |
724 | irq_flow_handler_t handle, const char *name) | |
dd87eb3a | 725 | { |
a460e745 IM |
726 | set_irq_chip(irq, chip); |
727 | __set_irq_handler(irq, handle, 0, name); | |
dd87eb3a | 728 | } |
46f4f8f6 | 729 | |
860652bf | 730 | void set_irq_noprobe(unsigned int irq) |
46f4f8f6 | 731 | { |
d3c60047 | 732 | struct irq_desc *desc = irq_to_desc(irq); |
46f4f8f6 RB |
733 | unsigned long flags; |
734 | ||
7d94f7ca | 735 | if (!desc) { |
46f4f8f6 | 736 | printk(KERN_ERR "Trying to mark IRQ%d non-probeable\n", irq); |
46f4f8f6 RB |
737 | return; |
738 | } | |
739 | ||
239007b8 | 740 | raw_spin_lock_irqsave(&desc->lock, flags); |
46f4f8f6 | 741 | desc->status |= IRQ_NOPROBE; |
239007b8 | 742 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
46f4f8f6 RB |
743 | } |
744 | ||
860652bf | 745 | void set_irq_probe(unsigned int irq) |
46f4f8f6 | 746 | { |
d3c60047 | 747 | struct irq_desc *desc = irq_to_desc(irq); |
46f4f8f6 RB |
748 | unsigned long flags; |
749 | ||
7d94f7ca | 750 | if (!desc) { |
46f4f8f6 | 751 | printk(KERN_ERR "Trying to mark IRQ%d probeable\n", irq); |
46f4f8f6 RB |
752 | return; |
753 | } | |
754 | ||
239007b8 | 755 | raw_spin_lock_irqsave(&desc->lock, flags); |
46f4f8f6 | 756 | desc->status &= ~IRQ_NOPROBE; |
239007b8 | 757 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
46f4f8f6 | 758 | } |