[mirror_ubuntu-kernels.git] / kernel / irq / generic-chip.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Library implementing the most common irq chip callback functions
 *
 * Copyright (C) 2011, Thomas Gleixner
 */
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/syscore_ops.h>

#include "internals.h"

static LIST_HEAD(gc_list);
static DEFINE_RAW_SPINLOCK(gc_lock);

/**
 * irq_gc_noop - NOOP function
 * @d: irq_data
 */
void irq_gc_noop(struct irq_data *d)
{
}
EXPORT_SYMBOL_GPL(irq_gc_noop);

/**
 * irq_gc_mask_disable_reg - Mask chip via disable register
 * @d: irq_data
 *
 * Chip has separate enable/disable registers instead of a single mask
 * register.
 */
void irq_gc_mask_disable_reg(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(gc, mask, ct->regs.disable);
	*ct->mask_cache &= ~mask;
	irq_gc_unlock(gc);
}
EXPORT_SYMBOL_GPL(irq_gc_mask_disable_reg);

/**
 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
 * @d: irq_data
 *
 * Chip has a single mask register. Values of this register are cached
 * and protected by gc->lock
 */
void irq_gc_mask_set_bit(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	*ct->mask_cache |= mask;
	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
	irq_gc_unlock(gc);
}
EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);

/**
 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
 * @d: irq_data
 *
 * Chip has a single mask register. Values of this register are cached
 * and protected by gc->lock
 */
void irq_gc_mask_clr_bit(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	*ct->mask_cache &= ~mask;
	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
	irq_gc_unlock(gc);
}
EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);

/**
 * irq_gc_unmask_enable_reg - Unmask chip via enable register
 * @d: irq_data
 *
 * Chip has separate enable/disable registers instead of a single mask
 * register.
 */
void irq_gc_unmask_enable_reg(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(gc, mask, ct->regs.enable);
	*ct->mask_cache |= mask;
	irq_gc_unlock(gc);
}
EXPORT_SYMBOL_GPL(irq_gc_unmask_enable_reg);

/**
 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
 * @d: irq_data
 */
void irq_gc_ack_set_bit(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(gc, mask, ct->regs.ack);
	irq_gc_unlock(gc);
}
EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);

/**
 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
 * @d: irq_data
 */
void irq_gc_ack_clr_bit(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = ~d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(gc, mask, ct->regs.ack);
	irq_gc_unlock(gc);
}

/**
 * irq_gc_mask_disable_and_ack_set - Mask and ack pending interrupt
 * @d: irq_data
 *
 * This generic implementation of the irq_mask_ack method is for chips
 * with separate enable/disable registers instead of a single mask
 * register and where a pending interrupt is acknowledged by setting a
 * bit.
 *
 * Note: This is the only permutation currently used.  Similar generic
 * functions should be added here if other permutations are required.
 */
void irq_gc_mask_disable_and_ack_set(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(gc, mask, ct->regs.disable);
	*ct->mask_cache &= ~mask;
	irq_reg_writel(gc, mask, ct->regs.ack);
	irq_gc_unlock(gc);
}

/**
 * irq_gc_eoi - EOI interrupt
 * @d: irq_data
 */
void irq_gc_eoi(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(gc, mask, ct->regs.eoi);
	irq_gc_unlock(gc);
}

/**
 * irq_gc_set_wake - Set/clr wake bit for an interrupt
 * @d:  irq_data
 * @on: Indicates whether the wake bit should be set or cleared
 *
 * For chips where the wake from suspend functionality is not
 * configured in a separate register and the wakeup active state is
 * just stored in a bitmask.
 */
int irq_gc_set_wake(struct irq_data *d, unsigned int on)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	u32 mask = d->mask;

	if (!(mask & gc->wake_enabled))
		return -EINVAL;

	irq_gc_lock(gc);
	if (on)
		gc->wake_active |= mask;
	else
		gc->wake_active &= ~mask;
	irq_gc_unlock(gc);
	return 0;
}
EXPORT_SYMBOL_GPL(irq_gc_set_wake);

static u32 irq_readl_be(void __iomem *addr)
{
	return ioread32be(addr);
}

static void irq_writel_be(u32 val, void __iomem *addr)
{
	iowrite32be(val, addr);
}

void irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
			   int num_ct, unsigned int irq_base,
			   void __iomem *reg_base, irq_flow_handler_t handler)
{
	raw_spin_lock_init(&gc->lock);
	gc->num_ct = num_ct;
	gc->irq_base = irq_base;
	gc->reg_base = reg_base;
	gc->chip_types->chip.name = name;
	gc->chip_types->handler = handler;
}

/**
 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
 * @name:	Name of the irq chip
 * @num_ct:	Number of irq_chip_type instances associated with this
 * @irq_base:	Interrupt base nr for this chip
 * @reg_base:	Register base address (virtual)
 * @handler:	Default flow handler associated with this chip
 *
 * Returns an initialized irq_chip_generic structure. The chip defaults
 * to the primary (index 0) irq_chip_type and @handler
 */
struct irq_chip_generic *
irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
		       void __iomem *reg_base, irq_flow_handler_t handler)
{
	struct irq_chip_generic *gc;

	gc = kzalloc(struct_size(gc, chip_types, num_ct), GFP_KERNEL);
	if (gc) {
		irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
				      handler);
	}
	return gc;
}
EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);

static void
irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
{
	struct irq_chip_type *ct = gc->chip_types;
	u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
	int i;

	for (i = 0; i < gc->num_ct; i++) {
		if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
			mskptr = &ct[i].mask_cache_priv;
			mskreg = ct[i].regs.mask;
		}
		ct[i].mask_cache = mskptr;
		if (flags & IRQ_GC_INIT_MASK_CACHE)
			*mskptr = irq_reg_readl(gc, mskreg);
	}
}

/**
 * __irq_alloc_domain_generic_chips - Allocate generic chips for an irq domain
 * @d:			irq domain for which to allocate chips
 * @irqs_per_chip:	Number of interrupts each chip handles (max 32)
 * @num_ct:		Number of irq_chip_type instances associated with this
 * @name:		Name of the irq chip
 * @handler:		Default flow handler associated with these chips
 * @clr:		IRQ_* bits to clear in the mapping function
 * @set:		IRQ_* bits to set in the mapping function
 * @gcflags:		Generic chip specific setup flags
 */
int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
				     int num_ct, const char *name,
				     irq_flow_handler_t handler,
				     unsigned int clr, unsigned int set,
				     enum irq_gc_flags gcflags)
{
	struct irq_domain_chip_generic *dgc;
	struct irq_chip_generic *gc;
	unsigned long flags;
	int numchips, i;
	size_t dgc_sz;
	size_t gc_sz;
	size_t sz;
	void *tmp;

	if (d->gc)
		return -EBUSY;

	numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);
	if (!numchips)
		return -EINVAL;

	/* Allocate a pointer, generic chip and chiptypes for each chip */
	gc_sz = struct_size(gc, chip_types, num_ct);
	dgc_sz = struct_size(dgc, gc, numchips);
	sz = dgc_sz + numchips * gc_sz;

	tmp = dgc = kzalloc(sz, GFP_KERNEL);
	if (!dgc)
		return -ENOMEM;
	dgc->irqs_per_chip = irqs_per_chip;
	dgc->num_chips = numchips;
	dgc->irq_flags_to_set = set;
	dgc->irq_flags_to_clear = clr;
	dgc->gc_flags = gcflags;
	d->gc = dgc;

	/* Calc pointer to the first generic chip */
	tmp += dgc_sz;
	for (i = 0; i < numchips; i++) {
		/* Store the pointer to the generic chip */
		dgc->gc[i] = gc = tmp;
		irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
				      NULL, handler);

		gc->domain = d;
		if (gcflags & IRQ_GC_BE_IO) {
			gc->reg_readl = &irq_readl_be;
			gc->reg_writel = &irq_writel_be;
		}

		raw_spin_lock_irqsave(&gc_lock, flags);
		list_add_tail(&gc->list, &gc_list);
		raw_spin_unlock_irqrestore(&gc_lock, flags);
		/* Calc pointer to the next generic chip */
		tmp += gc_sz;
	}
	return 0;
}
EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);

static struct irq_chip_generic *
__irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
{
	struct irq_domain_chip_generic *dgc = d->gc;
	int idx;

	if (!dgc)
		return ERR_PTR(-ENODEV);
	idx = hw_irq / dgc->irqs_per_chip;
	if (idx >= dgc->num_chips)
		return ERR_PTR(-EINVAL);
	return dgc->gc[idx];
}

/**
 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
 * @d:			irq domain pointer
 * @hw_irq:		Hardware interrupt number
 */
struct irq_chip_generic *
irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
{
	struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);

	return !IS_ERR(gc) ? gc : NULL;
}
EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);

/*
 * Separate lockdep classes for interrupt chip which can nest irq_desc
 * lock and request mutex.
 */
static struct lock_class_key irq_nested_lock_class;
static struct lock_class_key irq_nested_request_class;

/*
 * irq_map_generic_chip - Map a generic chip for an irq domain
 */
int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
			 irq_hw_number_t hw_irq)
{
	struct irq_data *data = irq_domain_get_irq_data(d, virq);
	struct irq_domain_chip_generic *dgc = d->gc;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	struct irq_chip *chip;
	unsigned long flags;
	int idx;

	gc = __irq_get_domain_generic_chip(d, hw_irq);
	if (IS_ERR(gc))
		return PTR_ERR(gc);

	idx = hw_irq % dgc->irqs_per_chip;

	if (test_bit(idx, &gc->unused))
		return -ENOTSUPP;

	if (test_bit(idx, &gc->installed))
		return -EBUSY;

	ct = gc->chip_types;
	chip = &ct->chip;

	/* We only init the cache for the first mapping of a generic chip */
	if (!gc->installed) {
		raw_spin_lock_irqsave(&gc->lock, flags);
		irq_gc_init_mask_cache(gc, dgc->gc_flags);
		raw_spin_unlock_irqrestore(&gc->lock, flags);
	}

	/* Mark the interrupt as installed */
	set_bit(idx, &gc->installed);

	if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
		irq_set_lockdep_class(virq, &irq_nested_lock_class,
				      &irq_nested_request_class);

	if (chip->irq_calc_mask)
		chip->irq_calc_mask(data);
	else
		data->mask = 1 << idx;

	irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
	irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
	return 0;
}

static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
{
	struct irq_data *data = irq_domain_get_irq_data(d, virq);
	struct irq_domain_chip_generic *dgc = d->gc;
	unsigned int hw_irq = data->hwirq;
	struct irq_chip_generic *gc;
	int irq_idx;

	gc = irq_get_domain_generic_chip(d, hw_irq);
	if (!gc)
		return;

	irq_idx = hw_irq % dgc->irqs_per_chip;

	clear_bit(irq_idx, &gc->installed);
	irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL,
			    NULL);

}

struct irq_domain_ops irq_generic_chip_ops = {
	.map	= irq_map_generic_chip,
	.unmap  = irq_unmap_generic_chip,
	.xlate	= irq_domain_xlate_onetwocell,
};
EXPORT_SYMBOL_GPL(irq_generic_chip_ops);

/**
 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
 * @gc:		Generic irq chip holding all data
 * @msk:	Bitmask holding the irqs to initialize relative to gc->irq_base
 * @flags:	Flags for initialization
 * @clr:	IRQ_* bits to clear
 * @set:	IRQ_* bits to set
 *
 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
 * initializes all interrupts to the primary irq_chip_type and its
 * associated handler.
 */
void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
			    enum irq_gc_flags flags, unsigned int clr,
			    unsigned int set)
{
	struct irq_chip_type *ct = gc->chip_types;
	struct irq_chip *chip = &ct->chip;
	unsigned int i;

	raw_spin_lock(&gc_lock);
	list_add_tail(&gc->list, &gc_list);
	raw_spin_unlock(&gc_lock);

	irq_gc_init_mask_cache(gc, flags);

	for (i = gc->irq_base; msk; msk >>= 1, i++) {
		if (!(msk & 0x01))
			continue;

		if (flags & IRQ_GC_INIT_NESTED_LOCK)
			irq_set_lockdep_class(i, &irq_nested_lock_class,
					      &irq_nested_request_class);

		if (!(flags & IRQ_GC_NO_MASK)) {
			struct irq_data *d = irq_get_irq_data(i);

			if (chip->irq_calc_mask)
				chip->irq_calc_mask(d);
			else
				d->mask = 1 << (i - gc->irq_base);
		}
		irq_set_chip_and_handler(i, chip, ct->handler);
		irq_set_chip_data(i, gc);
		irq_modify_status(i, clr, set);
	}
	gc->irq_cnt = i - gc->irq_base;
}
EXPORT_SYMBOL_GPL(irq_setup_generic_chip);

/**
 * irq_setup_alt_chip - Switch to alternative chip
 * @d:		irq_data for this interrupt
 * @type:	Flow type to be initialized
 *
 * Only to be called from chip->irq_set_type() callbacks.
 */
int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = gc->chip_types;
	unsigned int i;

	for (i = 0; i < gc->num_ct; i++, ct++) {
		if (ct->type & type) {
			d->chip = &ct->chip;
			irq_data_to_desc(d)->handle_irq = ct->handler;
			return 0;
		}
	}
	return -EINVAL;
}
EXPORT_SYMBOL_GPL(irq_setup_alt_chip);

/**
 * irq_remove_generic_chip - Remove a chip
 * @gc:		Generic irq chip holding all data
 * @msk:	Bitmask holding the irqs to initialize relative to gc->irq_base
 * @clr:	IRQ_* bits to clear
 * @set:	IRQ_* bits to set
 *
 * Remove up to 32 interrupts starting from gc->irq_base.
 */
void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
			     unsigned int clr, unsigned int set)
{
	unsigned int i = gc->irq_base;

	raw_spin_lock(&gc_lock);
	list_del(&gc->list);
	raw_spin_unlock(&gc_lock);

	for (; msk; msk >>= 1, i++) {
		if (!(msk & 0x01))
			continue;

		/* Remove handler first. That will mask the irq line */
		irq_set_handler(i, NULL);
		irq_set_chip(i, &no_irq_chip);
		irq_set_chip_data(i, NULL);
		irq_modify_status(i, clr, set);
	}
}
EXPORT_SYMBOL_GPL(irq_remove_generic_chip);

static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
{
	unsigned int virq;

	if (!gc->domain)
		return irq_get_irq_data(gc->irq_base);

	/*
	 * We don't know which of the irqs has been actually
	 * installed. Use the first one.
	 */
	if (!gc->installed)
		return NULL;

	virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
	return virq ? irq_get_irq_data(virq) : NULL;
}

#ifdef CONFIG_PM
static int irq_gc_suspend(void)
{
	struct irq_chip_generic *gc;

	list_for_each_entry(gc, &gc_list, list) {
		struct irq_chip_type *ct = gc->chip_types;

		if (ct->chip.irq_suspend) {
			struct irq_data *data = irq_gc_get_irq_data(gc);

			if (data)
				ct->chip.irq_suspend(data);
		}

		if (gc->suspend)
			gc->suspend(gc);
	}
	return 0;
}

static void irq_gc_resume(void)
{
	struct irq_chip_generic *gc;

	list_for_each_entry(gc, &gc_list, list) {
		struct irq_chip_type *ct = gc->chip_types;

		if (gc->resume)
			gc->resume(gc);

		if (ct->chip.irq_resume) {
			struct irq_data *data = irq_gc_get_irq_data(gc);

			if (data)
				ct->chip.irq_resume(data);
		}
	}
}
#else
#define irq_gc_suspend NULL
#define irq_gc_resume NULL
#endif

static void irq_gc_shutdown(void)
{
	struct irq_chip_generic *gc;

	list_for_each_entry(gc, &gc_list, list) {
		struct irq_chip_type *ct = gc->chip_types;

		if (ct->chip.irq_pm_shutdown) {
			struct irq_data *data = irq_gc_get_irq_data(gc);

			if (data)
				ct->chip.irq_pm_shutdown(data);
		}
	}
}

static struct syscore_ops irq_gc_syscore_ops = {
	.suspend = irq_gc_suspend,
	.resume = irq_gc_resume,
	.shutdown = irq_gc_shutdown,
};

static int __init irq_gc_init_ops(void)
{
	register_syscore_ops(&irq_gc_syscore_ops);
	return 0;
}
device_initcall(irq_gc_init_ops);
Commit	Line	Data
52a65ff5	1	// SPDX-License-Identifier: GPL-2.0
7d828062 TG	2	/*
	3	* Library implementing the most common irq chip callback functions
	4	*
	5	* Copyright (C) 2011, Thomas Gleixner
	6	*/
	7	#include <linux/io.h>
	8	#include <linux/irq.h>
	9	#include <linux/slab.h>
6e5fdeed	10	#include <linux/export.h>
088f40b7	11	#include <linux/irqdomain.h>
7d828062 TG	12	#include <linux/interrupt.h>
7d828062 TG	13	#include <linux/kernel_stat.h>
cfefd21e	14	#include <linux/syscore_ops.h>
7d828062 TG	15
	16	#include "internals.h"
	17
cfefd21e TG	18	static LIST_HEAD(gc_list);
	19	static DEFINE_RAW_SPINLOCK(gc_lock);
	20
7d828062 TG	21	/**
	22	* irq_gc_noop - NOOP function
	23	* @d: irq_data
	24	*/
	25	void irq_gc_noop(struct irq_data *d)
	26	{
	27	}
945486bf	28	EXPORT_SYMBOL_GPL(irq_gc_noop);
7d828062 TG	29
	30	/**
	31	* irq_gc_mask_disable_reg - Mask chip via disable register
	32	* @d: irq_data
	33	*
	34	* Chip has separate enable/disable registers instead of a single mask
	35	* register.
	36	*/
	37	void irq_gc_mask_disable_reg(struct irq_data *d)
	38	{
	39	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	40	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	41	u32 mask = d->mask;
7d828062 TG	42
7d828062 TG	43	irq_gc_lock(gc);
332fd7c4	44	irq_reg_writel(gc, mask, ct->regs.disable);
899f0e66	45	*ct->mask_cache &= ~mask;
7d828062 TG	46	irq_gc_unlock(gc);
7d828062 TG	47	}
fcd0f63d	48	EXPORT_SYMBOL_GPL(irq_gc_mask_disable_reg);
7d828062 TG	49
7d828062 TG	50	/**
ccc414f8	51	* irq_gc_mask_set_bit - Mask chip via setting bit in mask register
7d828062 TG	52	* @d: irq_data
	53	*
	54	* Chip has a single mask register. Values of this register are cached
	55	* and protected by gc->lock
	56	*/
	57	void irq_gc_mask_set_bit(struct irq_data *d)
	58	{
	59	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	60	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	61	u32 mask = d->mask;
7d828062 TG	62
7d828062 TG	63	irq_gc_lock(gc);
899f0e66	64	*ct->mask_cache \|= mask;
332fd7c4	65	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
7d828062 TG	66	irq_gc_unlock(gc);
7d828062 TG	67	}
d55f0cc4	68	EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
7d828062 TG	69
7d828062 TG	70	/**
ccc414f8	71	* irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
7d828062 TG	72	* @d: irq_data
	73	*
	74	* Chip has a single mask register. Values of this register are cached
	75	* and protected by gc->lock
	76	*/
	77	void irq_gc_mask_clr_bit(struct irq_data *d)
	78	{
	79	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	80	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	81	u32 mask = d->mask;
7d828062 TG	82
7d828062 TG	83	irq_gc_lock(gc);
899f0e66	84	*ct->mask_cache &= ~mask;
332fd7c4	85	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
7d828062 TG	86	irq_gc_unlock(gc);
7d828062 TG	87	}
d55f0cc4	88	EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
7d828062 TG	89
	90	/**
	91	* irq_gc_unmask_enable_reg - Unmask chip via enable register
	92	* @d: irq_data
	93	*
	94	* Chip has separate enable/disable registers instead of a single mask
	95	* register.
	96	*/
	97	void irq_gc_unmask_enable_reg(struct irq_data *d)
	98	{
	99	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	100	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	101	u32 mask = d->mask;
7d828062 TG	102
7d828062 TG	103	irq_gc_lock(gc);
332fd7c4	104	irq_reg_writel(gc, mask, ct->regs.enable);
899f0e66	105	*ct->mask_cache \|= mask;
7d828062 TG	106	irq_gc_unlock(gc);
7d828062 TG	107	}
fcd0f63d	108	EXPORT_SYMBOL_GPL(irq_gc_unmask_enable_reg);
7d828062 TG	109
7d828062 TG	110	/**
659fb32d	111	* irq_gc_ack_set_bit - Ack pending interrupt via setting bit
7d828062 TG	112	* @d: irq_data
7d828062 TG	113	*/
659fb32d	114	void irq_gc_ack_set_bit(struct irq_data *d)
7d828062 TG	115	{
7d828062 TG	116	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	117	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	118	u32 mask = d->mask;
7d828062 TG	119
7d828062 TG	120	irq_gc_lock(gc);
332fd7c4	121	irq_reg_writel(gc, mask, ct->regs.ack);
7d828062 TG	122	irq_gc_unlock(gc);
7d828062 TG	123	}
d55f0cc4	124	EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
7d828062	125
659fb32d SG	126	/**
	127	* irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
	128	* @d: irq_data
	129	*/
	130	void irq_gc_ack_clr_bit(struct irq_data *d)
	131	{
	132	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	133	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	134	u32 mask = ~d->mask;
659fb32d SG	135
659fb32d SG	136	irq_gc_lock(gc);
332fd7c4	137	irq_reg_writel(gc, mask, ct->regs.ack);
659fb32d SG	138	irq_gc_unlock(gc);
	139	}
	140
20608924 DB	141	/**
	142	* irq_gc_mask_disable_and_ack_set - Mask and ack pending interrupt
	143	* @d: irq_data
	144	*
	145	* This generic implementation of the irq_mask_ack method is for chips
	146	* with separate enable/disable registers instead of a single mask
	147	* register and where a pending interrupt is acknowledged by setting a
	148	* bit.
	149	*
	150	* Note: This is the only permutation currently used. Similar generic
	151	* functions should be added here if other permutations are required.
	152	*/
	153	void irq_gc_mask_disable_and_ack_set(struct irq_data *d)
	154	{
	155	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	156	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	157	u32 mask = d->mask;
	158
	159	irq_gc_lock(gc);
	160	irq_reg_writel(gc, mask, ct->regs.disable);
	161	*ct->mask_cache &= ~mask;
	162	irq_reg_writel(gc, mask, ct->regs.ack);
	163	irq_gc_unlock(gc);
	164	}
	165
7d828062 TG	166	/**
	167	* irq_gc_eoi - EOI interrupt
	168	* @d: irq_data
	169	*/
	170	void irq_gc_eoi(struct irq_data *d)
	171	{
	172	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	173	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	174	u32 mask = d->mask;
7d828062 TG	175
7d828062 TG	176	irq_gc_lock(gc);
332fd7c4	177	irq_reg_writel(gc, mask, ct->regs.eoi);
7d828062 TG	178	irq_gc_unlock(gc);
	179	}
	180
	181	/**
	182	* irq_gc_set_wake - Set/clr wake bit for an interrupt
ccc414f8 TG	183	* @d: irq_data
ccc414f8 TG	184	* @on: Indicates whether the wake bit should be set or cleared
7d828062 TG	185	*
	186	* For chips where the wake from suspend functionality is not
	187	* configured in a separate register and the wakeup active state is
	188	* just stored in a bitmask.
	189	*/
	190	int irq_gc_set_wake(struct irq_data *d, unsigned int on)
	191	{
	192	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
966dc736	193	u32 mask = d->mask;
7d828062 TG	194
	195	if (!(mask & gc->wake_enabled))
	196	return -EINVAL;
	197
	198	irq_gc_lock(gc);
	199	if (on)
	200	gc->wake_active \|= mask;
	201	else
	202	gc->wake_active &= ~mask;
	203	irq_gc_unlock(gc);
	204	return 0;
	205	}
024c7952	206	EXPORT_SYMBOL_GPL(irq_gc_set_wake);
7d828062	207
b7905595 KC	208	static u32 irq_readl_be(void __iomem *addr)
	209	{
	210	return ioread32be(addr);
	211	}
	212
	213	static void irq_writel_be(u32 val, void __iomem *addr)
	214	{
	215	iowrite32be(val, addr);
	216	}
	217
f1602039 BG	218	void irq_init_generic_chip(struct irq_chip_generic gc, const char name,
	219	int num_ct, unsigned int irq_base,
	220	void __iomem *reg_base, irq_flow_handler_t handler)
3528d82b TG	221	{
	222	raw_spin_lock_init(&gc->lock);
	223	gc->num_ct = num_ct;
	224	gc->irq_base = irq_base;
	225	gc->reg_base = reg_base;
	226	gc->chip_types->chip.name = name;
	227	gc->chip_types->handler = handler;
	228	}
	229
7d828062 TG	230	/**
	231	* irq_alloc_generic_chip - Allocate a generic chip and initialize it
	232	* @name: Name of the irq chip
	233	* @num_ct: Number of irq_chip_type instances associated with this
	234	* @irq_base: Interrupt base nr for this chip
	235	* @reg_base: Register base address (virtual)
	236	* @handler: Default flow handler associated with this chip
	237	*
	238	* Returns an initialized irq_chip_generic structure. The chip defaults
	239	* to the primary (index 0) irq_chip_type and @handler
	240	*/
	241	struct irq_chip_generic *
	242	irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
	243	void __iomem *reg_base, irq_flow_handler_t handler)
	244	{
	245	struct irq_chip_generic *gc;
7d828062	246
5a6c76b5	247	gc = kzalloc(struct_size(gc, chip_types, num_ct), GFP_KERNEL);
7d828062	248	if (gc) {
3528d82b TG	249	irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
3528d82b TG	250	handler);
7d828062 TG	251	}
	252	return gc;
	253	}
825de2e9	254	EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
7d828062	255
3528d82b TG	256	static void
	257	irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
	258	{
	259	struct irq_chip_type *ct = gc->chip_types;
	260	u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
	261	int i;
	262
	263	for (i = 0; i < gc->num_ct; i++) {
	264	if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
	265	mskptr = &ct[i].mask_cache_priv;
	266	mskreg = ct[i].regs.mask;
	267	}
	268	ct[i].mask_cache = mskptr;
	269	if (flags & IRQ_GC_INIT_MASK_CACHE)
332fd7c4	270	*mskptr = irq_reg_readl(gc, mskreg);
3528d82b TG	271	}
	272	}
	273
088f40b7	274	/**
8c67d247	275	* __irq_alloc_domain_generic_chips - Allocate generic chips for an irq domain
088f40b7	276	* @d: irq domain for which to allocate chips
f88eecfe	277	* @irqs_per_chip: Number of interrupts each chip handles (max 32)
088f40b7 TG	278	* @num_ct: Number of irq_chip_type instances associated with this
	279	* @name: Name of the irq chip
	280	* @handler: Default flow handler associated with these chips
	281	* @clr: IRQ_* bits to clear in the mapping function
	282	* @set: IRQ_* bits to set in the mapping function
6fff8314	283	* @gcflags: Generic chip specific setup flags
088f40b7	284	*/
f88eecfe SF	285	int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
	286	int num_ct, const char *name,
	287	irq_flow_handler_t handler,
	288	unsigned int clr, unsigned int set,
	289	enum irq_gc_flags gcflags)
088f40b7 TG	290	{
	291	struct irq_domain_chip_generic *dgc;
	292	struct irq_chip_generic *gc;
088f40b7	293	unsigned long flags;
5a6c76b5 GS	294	int numchips, i;
	295	size_t dgc_sz;
	296	size_t gc_sz;
	297	size_t sz;
088f40b7 TG	298	void *tmp;
	299
	300	if (d->gc)
	301	return -EBUSY;
	302
505608d2	303	numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);
088f40b7 TG	304	if (!numchips)
	305	return -EINVAL;
	306
	307	/* Allocate a pointer, generic chip and chiptypes for each chip */
5a6c76b5 GS	308	gc_sz = struct_size(gc, chip_types, num_ct);
	309	dgc_sz = struct_size(dgc, gc, numchips);
	310	sz = dgc_sz + numchips * gc_sz;
088f40b7 TG	311
	312	tmp = dgc = kzalloc(sz, GFP_KERNEL);
	313	if (!dgc)
	314	return -ENOMEM;
	315	dgc->irqs_per_chip = irqs_per_chip;
	316	dgc->num_chips = numchips;
	317	dgc->irq_flags_to_set = set;
	318	dgc->irq_flags_to_clear = clr;
	319	dgc->gc_flags = gcflags;
	320	d->gc = dgc;
	321
	322	/* Calc pointer to the first generic chip */
5a6c76b5	323	tmp += dgc_sz;
088f40b7 TG	324	for (i = 0; i < numchips; i++) {
	325	/* Store the pointer to the generic chip */
	326	dgc->gc[i] = gc = tmp;
	327	irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
	328	NULL, handler);
b7905595	329
088f40b7	330	gc->domain = d;
b7905595 KC	331	if (gcflags & IRQ_GC_BE_IO) {
	332	gc->reg_readl = &irq_readl_be;
	333	gc->reg_writel = &irq_writel_be;
	334	}
	335
088f40b7 TG	336	raw_spin_lock_irqsave(&gc_lock, flags);
	337	list_add_tail(&gc->list, &gc_list);
	338	raw_spin_unlock_irqrestore(&gc_lock, flags);
	339	/* Calc pointer to the next generic chip */
5a6c76b5	340	tmp += gc_sz;
088f40b7 TG	341	}
	342	return 0;
	343	}
f88eecfe	344	EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);
088f40b7	345
f0c450ea SF	346	static struct irq_chip_generic *
	347	__irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
	348	{
	349	struct irq_domain_chip_generic *dgc = d->gc;
	350	int idx;
	351
	352	if (!dgc)
	353	return ERR_PTR(-ENODEV);
	354	idx = hw_irq / dgc->irqs_per_chip;
	355	if (idx >= dgc->num_chips)
	356	return ERR_PTR(-EINVAL);
	357	return dgc->gc[idx];
	358	}
	359
088f40b7 TG	360	/**
	361	* irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
	362	* @d: irq domain pointer
	363	* @hw_irq: Hardware interrupt number
	364	*/
	365	struct irq_chip_generic *
	366	irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
	367	{
f0c450ea	368	struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);
088f40b7	369
f0c450ea	370	return !IS_ERR(gc) ? gc : NULL;
088f40b7 TG	371	}
	372	EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
	373
7d828062	374	/*
39c3fd58 AL	375	* Separate lockdep classes for interrupt chip which can nest irq_desc
39c3fd58 AL	376	* lock and request mutex.
7d828062 TG	377	*/
7d828062 TG	378	static struct lock_class_key irq_nested_lock_class;
39c3fd58	379	static struct lock_class_key irq_nested_request_class;
7d828062	380
ccc414f8	381	/*
088f40b7 TG	382	* irq_map_generic_chip - Map a generic chip for an irq domain
088f40b7 TG	383	*/
a5152c8a BB	384	int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
a5152c8a BB	385	irq_hw_number_t hw_irq)
088f40b7	386	{
c5863484	387	struct irq_data *data = irq_domain_get_irq_data(d, virq);
088f40b7 TG	388	struct irq_domain_chip_generic *dgc = d->gc;
	389	struct irq_chip_generic *gc;
	390	struct irq_chip_type *ct;
	391	struct irq_chip *chip;
	392	unsigned long flags;
	393	int idx;
	394
f0c450ea SF	395	gc = __irq_get_domain_generic_chip(d, hw_irq);
	396	if (IS_ERR(gc))
	397	return PTR_ERR(gc);
088f40b7 TG	398
	399	idx = hw_irq % dgc->irqs_per_chip;
	400
e8bd834f GL	401	if (test_bit(idx, &gc->unused))
	402	return -ENOTSUPP;
	403
088f40b7 TG	404	if (test_bit(idx, &gc->installed))
	405	return -EBUSY;
	406
	407	ct = gc->chip_types;
	408	chip = &ct->chip;
	409
	410	/* We only init the cache for the first mapping of a generic chip */
	411	if (!gc->installed) {
	412	raw_spin_lock_irqsave(&gc->lock, flags);
	413	irq_gc_init_mask_cache(gc, dgc->gc_flags);
	414	raw_spin_unlock_irqrestore(&gc->lock, flags);
	415	}
	416
	417	/* Mark the interrupt as installed */
	418	set_bit(idx, &gc->installed);
	419
	420	if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
39c3fd58 AL	421	irq_set_lockdep_class(virq, &irq_nested_lock_class,
39c3fd58 AL	422	&irq_nested_request_class);
088f40b7 TG	423
	424	if (chip->irq_calc_mask)
	425	chip->irq_calc_mask(data);
	426	else
	427	data->mask = 1 << idx;
	428
c5863484	429	irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
088f40b7 TG	430	irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
	431	return 0;
	432	}
	433
ee26c013 SF	434	static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
	435	{
	436	struct irq_data *data = irq_domain_get_irq_data(d, virq);
	437	struct irq_domain_chip_generic *dgc = d->gc;
	438	unsigned int hw_irq = data->hwirq;
	439	struct irq_chip_generic *gc;
	440	int irq_idx;
	441
	442	gc = irq_get_domain_generic_chip(d, hw_irq);
	443	if (!gc)
	444	return;
	445
	446	irq_idx = hw_irq % dgc->irqs_per_chip;
	447
	448	clear_bit(irq_idx, &gc->installed);
	449	irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL,
	450	NULL);
	451
	452	}
	453
088f40b7 TG	454	struct irq_domain_ops irq_generic_chip_ops = {
088f40b7 TG	455	.map = irq_map_generic_chip,
ee26c013	456	.unmap = irq_unmap_generic_chip,
088f40b7 TG	457	.xlate = irq_domain_xlate_onetwocell,
	458	};
	459	EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
	460
7d828062 TG	461	/**
	462	* irq_setup_generic_chip - Setup a range of interrupts with a generic chip
	463	* @gc: Generic irq chip holding all data
	464	* @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
	465	* @flags: Flags for initialization
	466	* @clr: IRQ_* bits to clear
	467	* @set: IRQ_* bits to set
	468	*
	469	* Set up max. 32 interrupts starting from gc->irq_base. Note, this
	470	* initializes all interrupts to the primary irq_chip_type and its
	471	* associated handler.
	472	*/
	473	void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
	474	enum irq_gc_flags flags, unsigned int clr,
	475	unsigned int set)
	476	{
	477	struct irq_chip_type *ct = gc->chip_types;
d0051816	478	struct irq_chip *chip = &ct->chip;
7d828062 TG	479	unsigned int i;
7d828062 TG	480
cfefd21e TG	481	raw_spin_lock(&gc_lock);
	482	list_add_tail(&gc->list, &gc_list);
	483	raw_spin_unlock(&gc_lock);
	484
3528d82b	485	irq_gc_init_mask_cache(gc, flags);
899f0e66	486
7d828062	487	for (i = gc->irq_base; msk; msk >>= 1, i++) {
1dd75f91	488	if (!(msk & 0x01))
7d828062 TG	489	continue;
	490
	491	if (flags & IRQ_GC_INIT_NESTED_LOCK)
39c3fd58 AL	492	irq_set_lockdep_class(i, &irq_nested_lock_class,
39c3fd58 AL	493	&irq_nested_request_class);
7d828062	494
966dc736 TG	495	if (!(flags & IRQ_GC_NO_MASK)) {
	496	struct irq_data *d = irq_get_irq_data(i);
	497
d0051816 TG	498	if (chip->irq_calc_mask)
	499	chip->irq_calc_mask(d);
	500	else
	501	d->mask = 1 << (i - gc->irq_base);
966dc736	502	}
d0051816	503	irq_set_chip_and_handler(i, chip, ct->handler);
7d828062 TG	504	irq_set_chip_data(i, gc);
	505	irq_modify_status(i, clr, set);
	506	}
	507	gc->irq_cnt = i - gc->irq_base;
	508	}
825de2e9	509	EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
7d828062 TG	510
	511	/**
	512	* irq_setup_alt_chip - Switch to alternative chip
	513	* @d: irq_data for this interrupt
ccc414f8	514	* @type: Flow type to be initialized
7d828062 TG	515	*
	516	* Only to be called from chip->irq_set_type() callbacks.
	517	*/
	518	int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
	519	{
	520	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	521	struct irq_chip_type *ct = gc->chip_types;
	522	unsigned int i;
	523
	524	for (i = 0; i < gc->num_ct; i++, ct++) {
	525	if (ct->type & type) {
	526	d->chip = &ct->chip;
	527	irq_data_to_desc(d)->handle_irq = ct->handler;
	528	return 0;
	529	}
	530	}
	531	return -EINVAL;
	532	}
825de2e9	533	EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
cfefd21e TG	534
	535	/**
	536	* irq_remove_generic_chip - Remove a chip
	537	* @gc: Generic irq chip holding all data
	538	* @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
	539	* @clr: IRQ_* bits to clear
	540	* @set: IRQ_* bits to set
	541	*
	542	* Remove up to 32 interrupts starting from gc->irq_base.
	543	*/
	544	void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
	545	unsigned int clr, unsigned int set)
	546	{
	547	unsigned int i = gc->irq_base;
	548
	549	raw_spin_lock(&gc_lock);
	550	list_del(&gc->list);
	551	raw_spin_unlock(&gc_lock);
	552
	553	for (; msk; msk >>= 1, i++) {
1dd75f91	554	if (!(msk & 0x01))
cfefd21e TG	555	continue;
	556
	557	/* Remove handler first. That will mask the irq line */
	558	irq_set_handler(i, NULL);
	559	irq_set_chip(i, &no_irq_chip);
	560	irq_set_chip_data(i, NULL);
	561	irq_modify_status(i, clr, set);
	562	}
	563	}
825de2e9	564	EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
cfefd21e	565
088f40b7 TG	566	static struct irq_data irq_gc_get_irq_data(struct irq_chip_generic gc)
	567	{
	568	unsigned int virq;
	569
	570	if (!gc->domain)
	571	return irq_get_irq_data(gc->irq_base);
	572
	573	/*
	574	* We don't know which of the irqs has been actually
	575	* installed. Use the first one.
	576	*/
	577	if (!gc->installed)
	578	return NULL;
	579
	580	virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
	581	return virq ? irq_get_irq_data(virq) : NULL;
	582	}
	583
cfefd21e TG	584	#ifdef CONFIG_PM
	585	static int irq_gc_suspend(void)
	586	{
	587	struct irq_chip_generic *gc;
	588
	589	list_for_each_entry(gc, &gc_list, list) {
	590	struct irq_chip_type *ct = gc->chip_types;
	591
088f40b7 TG	592	if (ct->chip.irq_suspend) {
	593	struct irq_data *data = irq_gc_get_irq_data(gc);
	594
	595	if (data)
	596	ct->chip.irq_suspend(data);
	597	}
be9b22b6 BN	598
	599	if (gc->suspend)
	600	gc->suspend(gc);
cfefd21e TG	601	}
	602	return 0;
	603	}
	604
	605	static void irq_gc_resume(void)
	606	{
	607	struct irq_chip_generic *gc;
	608
	609	list_for_each_entry(gc, &gc_list, list) {
	610	struct irq_chip_type *ct = gc->chip_types;
	611
be9b22b6 BN	612	if (gc->resume)
	613	gc->resume(gc);
	614
088f40b7 TG	615	if (ct->chip.irq_resume) {
	616	struct irq_data *data = irq_gc_get_irq_data(gc);
	617
	618	if (data)
	619	ct->chip.irq_resume(data);
	620	}
cfefd21e TG	621	}
	622	}
	623	#else
	624	#define irq_gc_suspend NULL
	625	#define irq_gc_resume NULL
	626	#endif
	627
	628	static void irq_gc_shutdown(void)
	629	{
	630	struct irq_chip_generic *gc;
	631
	632	list_for_each_entry(gc, &gc_list, list) {
	633	struct irq_chip_type *ct = gc->chip_types;
	634
088f40b7 TG	635	if (ct->chip.irq_pm_shutdown) {
	636	struct irq_data *data = irq_gc_get_irq_data(gc);
	637
	638	if (data)
	639	ct->chip.irq_pm_shutdown(data);
	640	}
cfefd21e TG	641	}
	642	}
	643
	644	static struct syscore_ops irq_gc_syscore_ops = {
	645	.suspend = irq_gc_suspend,
	646	.resume = irq_gc_resume,
	647	.shutdown = irq_gc_shutdown,
	648	};
	649
	650	static int __init irq_gc_init_ops(void)
	651	{
	652	register_syscore_ops(&irq_gc_syscore_ops);
	653	return 0;
	654	}
	655	device_initcall(irq_gc_init_ops);