[mirror_ubuntu-artful-kernel.git] / kernel / irq / generic-chip.c

/*
 * Library implementing the most common irq chip callback functions
 *
 * Copyright (C) 2011, Thomas Gleixner
 */
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/syscore_ops.h>

#include "internals.h"

static LIST_HEAD(gc_list);
static DEFINE_RAW_SPINLOCK(gc_lock);

/**
 * irq_gc_noop - NOOP function
 * @d: irq_data
 */
void irq_gc_noop(struct irq_data *d)
{
}

/**
 * irq_gc_mask_disable_reg - Mask chip via disable register
 * @d: irq_data
 *
 * Chip has separate enable/disable registers instead of a single mask
 * register.
 */
void irq_gc_mask_disable_reg(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(mask, gc->reg_base + ct->regs.disable);
	*ct->mask_cache &= ~mask;
	irq_gc_unlock(gc);
}

/**
 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
 * @d: irq_data
 *
 * Chip has a single mask register. Values of this register are cached
 * and protected by gc->lock
 */
void irq_gc_mask_set_bit(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	*ct->mask_cache |= mask;
	irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
	irq_gc_unlock(gc);
}
EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);

/**
 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
 * @d: irq_data
 *
 * Chip has a single mask register. Values of this register are cached
 * and protected by gc->lock
 */
void irq_gc_mask_clr_bit(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	*ct->mask_cache &= ~mask;
	irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
	irq_gc_unlock(gc);
}
EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);

/**
 * irq_gc_unmask_enable_reg - Unmask chip via enable register
 * @d: irq_data
 *
 * Chip has separate enable/disable registers instead of a single mask
 * register.
 */
void irq_gc_unmask_enable_reg(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(mask, gc->reg_base + ct->regs.enable);
	*ct->mask_cache |= mask;
	irq_gc_unlock(gc);
}

/**
 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
 * @d: irq_data
 */
void irq_gc_ack_set_bit(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
	irq_gc_unlock(gc);
}
EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);

/**
 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
 * @d: irq_data
 */
void irq_gc_ack_clr_bit(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = ~d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
	irq_gc_unlock(gc);
}

/**
 * irq_gc_mask_disable_reg_and_ack - Mask and ack pending interrupt
 * @d: irq_data
 */
void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(mask, gc->reg_base + ct->regs.mask);
	irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
	irq_gc_unlock(gc);
}

/**
 * irq_gc_eoi - EOI interrupt
 * @d: irq_data
 */
void irq_gc_eoi(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(mask, gc->reg_base + ct->regs.eoi);
	irq_gc_unlock(gc);
}

/**
 * irq_gc_set_wake - Set/clr wake bit for an interrupt
 * @d:  irq_data
 * @on: Indicates whether the wake bit should be set or cleared
 *
 * For chips where the wake from suspend functionality is not
 * configured in a separate register and the wakeup active state is
 * just stored in a bitmask.
 */
int irq_gc_set_wake(struct irq_data *d, unsigned int on)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	u32 mask = d->mask;

	if (!(mask & gc->wake_enabled))
		return -EINVAL;

	irq_gc_lock(gc);
	if (on)
		gc->wake_active |= mask;
	else
		gc->wake_active &= ~mask;
	irq_gc_unlock(gc);
	return 0;
}

static void
irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
		      int num_ct, unsigned int irq_base,
		      void __iomem *reg_base, irq_flow_handler_t handler)
{
	raw_spin_lock_init(&gc->lock);
	gc->num_ct = num_ct;
	gc->irq_base = irq_base;
	gc->reg_base = reg_base;
	gc->chip_types->chip.name = name;
	gc->chip_types->handler = handler;
}

/**
 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
 * @name:	Name of the irq chip
 * @num_ct:	Number of irq_chip_type instances associated with this
 * @irq_base:	Interrupt base nr for this chip
 * @reg_base:	Register base address (virtual)
 * @handler:	Default flow handler associated with this chip
 *
 * Returns an initialized irq_chip_generic structure. The chip defaults
 * to the primary (index 0) irq_chip_type and @handler
 */
struct irq_chip_generic *
irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
		       void __iomem *reg_base, irq_flow_handler_t handler)
{
	struct irq_chip_generic *gc;
	unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);

	gc = kzalloc(sz, GFP_KERNEL);
	if (gc) {
		irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
				      handler);
	}
	return gc;
}
EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);

static void
irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
{
	struct irq_chip_type *ct = gc->chip_types;
	u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
	int i;

	for (i = 0; i < gc->num_ct; i++) {
		if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
			mskptr = &ct[i].mask_cache_priv;
			mskreg = ct[i].regs.mask;
		}
		ct[i].mask_cache = mskptr;
		if (flags & IRQ_GC_INIT_MASK_CACHE)
			*mskptr = irq_reg_readl(gc->reg_base + mskreg);
	}
}

/**
 * irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain
 * @d:			irq domain for which to allocate chips
 * @irqs_per_chip:	Number of interrupts each chip handles
 * @num_ct:		Number of irq_chip_type instances associated with this
 * @name:		Name of the irq chip
 * @handler:		Default flow handler associated with these chips
 * @clr:		IRQ_* bits to clear in the mapping function
 * @set:		IRQ_* bits to set in the mapping function
 * @gcflags:		Generic chip specific setup flags
 */
int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
				   int num_ct, const char *name,
				   irq_flow_handler_t handler,
				   unsigned int clr, unsigned int set,
				   enum irq_gc_flags gcflags)
{
	struct irq_domain_chip_generic *dgc;
	struct irq_chip_generic *gc;
	int numchips, sz, i;
	unsigned long flags;
	void *tmp;

	if (d->gc)
		return -EBUSY;

	numchips = d->revmap_size / irqs_per_chip;
	if (!numchips)
		return -EINVAL;

	/* Allocate a pointer, generic chip and chiptypes for each chip */
	sz = sizeof(*dgc) + numchips * sizeof(gc);
	sz += numchips * (sizeof(*gc) + num_ct * sizeof(struct irq_chip_type));

	tmp = dgc = kzalloc(sz, GFP_KERNEL);
	if (!dgc)
		return -ENOMEM;
	dgc->irqs_per_chip = irqs_per_chip;
	dgc->num_chips = numchips;
	dgc->irq_flags_to_set = set;
	dgc->irq_flags_to_clear = clr;
	dgc->gc_flags = gcflags;
	d->gc = dgc;

	/* Calc pointer to the first generic chip */
	tmp += sizeof(*dgc) + numchips * sizeof(gc);
	for (i = 0; i < numchips; i++) {
		/* Store the pointer to the generic chip */
		dgc->gc[i] = gc = tmp;
		irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
				      NULL, handler);
		gc->domain = d;
		raw_spin_lock_irqsave(&gc_lock, flags);
		list_add_tail(&gc->list, &gc_list);
		raw_spin_unlock_irqrestore(&gc_lock, flags);
		/* Calc pointer to the next generic chip */
		tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
	}
	d->name = name;
	return 0;
}
EXPORT_SYMBOL_GPL(irq_alloc_domain_generic_chips);

/**
 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
 * @d:			irq domain pointer
 * @hw_irq:		Hardware interrupt number
 */
struct irq_chip_generic *
irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
{
	struct irq_domain_chip_generic *dgc = d->gc;
	int idx;

	if (!dgc)
		return NULL;
	idx = hw_irq / dgc->irqs_per_chip;
	if (idx >= dgc->num_chips)
		return NULL;
	return dgc->gc[idx];
}
EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);

/*
 * Separate lockdep class for interrupt chip which can nest irq_desc
 * lock.
 */
static struct lock_class_key irq_nested_lock_class;

/*
 * irq_map_generic_chip - Map a generic chip for an irq domain
 */
static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
				irq_hw_number_t hw_irq)
{
	struct irq_data *data = irq_get_irq_data(virq);
	struct irq_domain_chip_generic *dgc = d->gc;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	struct irq_chip *chip;
	unsigned long flags;
	int idx;

	if (!d->gc)
		return -ENODEV;

	idx = hw_irq / dgc->irqs_per_chip;
	if (idx >= dgc->num_chips)
		return -EINVAL;
	gc = dgc->gc[idx];

	idx = hw_irq % dgc->irqs_per_chip;

	if (test_bit(idx, &gc->unused))
		return -ENOTSUPP;

	if (test_bit(idx, &gc->installed))
		return -EBUSY;

	ct = gc->chip_types;
	chip = &ct->chip;

	/* We only init the cache for the first mapping of a generic chip */
	if (!gc->installed) {
		raw_spin_lock_irqsave(&gc->lock, flags);
		irq_gc_init_mask_cache(gc, dgc->gc_flags);
		raw_spin_unlock_irqrestore(&gc->lock, flags);
	}

	/* Mark the interrupt as installed */
	set_bit(idx, &gc->installed);

	if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
		irq_set_lockdep_class(virq, &irq_nested_lock_class);

	if (chip->irq_calc_mask)
		chip->irq_calc_mask(data);
	else
		data->mask = 1 << idx;

	irq_set_chip_and_handler(virq, chip, ct->handler);
	irq_set_chip_data(virq, gc);
	irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
	return 0;
}

struct irq_domain_ops irq_generic_chip_ops = {
	.map	= irq_map_generic_chip,
	.xlate	= irq_domain_xlate_onetwocell,
};
EXPORT_SYMBOL_GPL(irq_generic_chip_ops);

/**
 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
 * @gc:		Generic irq chip holding all data
 * @msk:	Bitmask holding the irqs to initialize relative to gc->irq_base
 * @flags:	Flags for initialization
 * @clr:	IRQ_* bits to clear
 * @set:	IRQ_* bits to set
 *
 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
 * initializes all interrupts to the primary irq_chip_type and its
 * associated handler.
 */
void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
			    enum irq_gc_flags flags, unsigned int clr,
			    unsigned int set)
{
	struct irq_chip_type *ct = gc->chip_types;
	struct irq_chip *chip = &ct->chip;
	unsigned int i;

	raw_spin_lock(&gc_lock);
	list_add_tail(&gc->list, &gc_list);
	raw_spin_unlock(&gc_lock);

	irq_gc_init_mask_cache(gc, flags);

	for (i = gc->irq_base; msk; msk >>= 1, i++) {
		if (!(msk & 0x01))
			continue;

		if (flags & IRQ_GC_INIT_NESTED_LOCK)
			irq_set_lockdep_class(i, &irq_nested_lock_class);

		if (!(flags & IRQ_GC_NO_MASK)) {
			struct irq_data *d = irq_get_irq_data(i);

			if (chip->irq_calc_mask)
				chip->irq_calc_mask(d);
			else
				d->mask = 1 << (i - gc->irq_base);
		}
		irq_set_chip_and_handler(i, chip, ct->handler);
		irq_set_chip_data(i, gc);
		irq_modify_status(i, clr, set);
	}
	gc->irq_cnt = i - gc->irq_base;
}
EXPORT_SYMBOL_GPL(irq_setup_generic_chip);

/**
 * irq_setup_alt_chip - Switch to alternative chip
 * @d:		irq_data for this interrupt
 * @type:	Flow type to be initialized
 *
 * Only to be called from chip->irq_set_type() callbacks.
 */
int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = gc->chip_types;
	unsigned int i;

	for (i = 0; i < gc->num_ct; i++, ct++) {
		if (ct->type & type) {
			d->chip = &ct->chip;
			irq_data_to_desc(d)->handle_irq = ct->handler;
			return 0;
		}
	}
	return -EINVAL;
}
EXPORT_SYMBOL_GPL(irq_setup_alt_chip);

/**
 * irq_remove_generic_chip - Remove a chip
 * @gc:		Generic irq chip holding all data
 * @msk:	Bitmask holding the irqs to initialize relative to gc->irq_base
 * @clr:	IRQ_* bits to clear
 * @set:	IRQ_* bits to set
 *
 * Remove up to 32 interrupts starting from gc->irq_base.
 */
void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
			     unsigned int clr, unsigned int set)
{
	unsigned int i = gc->irq_base;

	raw_spin_lock(&gc_lock);
	list_del(&gc->list);
	raw_spin_unlock(&gc_lock);

	for (; msk; msk >>= 1, i++) {
		if (!(msk & 0x01))
			continue;

		/* Remove handler first. That will mask the irq line */
		irq_set_handler(i, NULL);
		irq_set_chip(i, &no_irq_chip);
		irq_set_chip_data(i, NULL);
		irq_modify_status(i, clr, set);
	}
}
EXPORT_SYMBOL_GPL(irq_remove_generic_chip);

static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
{
	unsigned int virq;

	if (!gc->domain)
		return irq_get_irq_data(gc->irq_base);

	/*
	 * We don't know which of the irqs has been actually
	 * installed. Use the first one.
	 */
	if (!gc->installed)
		return NULL;

	virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
	return virq ? irq_get_irq_data(virq) : NULL;
}

#ifdef CONFIG_PM
static int irq_gc_suspend(void)
{
	struct irq_chip_generic *gc;

	list_for_each_entry(gc, &gc_list, list) {
		struct irq_chip_type *ct = gc->chip_types;

		if (ct->chip.irq_suspend) {
			struct irq_data *data = irq_gc_get_irq_data(gc);

			if (data)
				ct->chip.irq_suspend(data);
		}
	}
	return 0;
}

static void irq_gc_resume(void)
{
	struct irq_chip_generic *gc;

	list_for_each_entry(gc, &gc_list, list) {
		struct irq_chip_type *ct = gc->chip_types;

		if (ct->chip.irq_resume) {
			struct irq_data *data = irq_gc_get_irq_data(gc);

			if (data)
				ct->chip.irq_resume(data);
		}
	}
}
#else
#define irq_gc_suspend NULL
#define irq_gc_resume NULL
#endif

static void irq_gc_shutdown(void)
{
	struct irq_chip_generic *gc;

	list_for_each_entry(gc, &gc_list, list) {
		struct irq_chip_type *ct = gc->chip_types;

		if (ct->chip.irq_pm_shutdown) {
			struct irq_data *data = irq_gc_get_irq_data(gc);

			if (data)
				ct->chip.irq_pm_shutdown(data);
		}
	}
}

static struct syscore_ops irq_gc_syscore_ops = {
	.suspend = irq_gc_suspend,
	.resume = irq_gc_resume,
	.shutdown = irq_gc_shutdown,
};

static int __init irq_gc_init_ops(void)
{
	register_syscore_ops(&irq_gc_syscore_ops);
	return 0;
}
device_initcall(irq_gc_init_ops);
Commit	Line	Data
7d828062 TG	1	/*
	2	* Library implementing the most common irq chip callback functions
	3	*
	4	* Copyright (C) 2011, Thomas Gleixner
	5	*/
	6	#include <linux/io.h>
	7	#include <linux/irq.h>
	8	#include <linux/slab.h>
6e5fdeed	9	#include <linux/export.h>
088f40b7	10	#include <linux/irqdomain.h>
7d828062 TG	11	#include <linux/interrupt.h>
7d828062 TG	12	#include <linux/kernel_stat.h>
cfefd21e	13	#include <linux/syscore_ops.h>
7d828062 TG	14
	15	#include "internals.h"
	16
cfefd21e TG	17	static LIST_HEAD(gc_list);
	18	static DEFINE_RAW_SPINLOCK(gc_lock);
	19
7d828062 TG	20	/**
	21	* irq_gc_noop - NOOP function
	22	* @d: irq_data
	23	*/
	24	void irq_gc_noop(struct irq_data *d)
	25	{
	26	}
	27
	28	/**
	29	* irq_gc_mask_disable_reg - Mask chip via disable register
	30	* @d: irq_data
	31	*
	32	* Chip has separate enable/disable registers instead of a single mask
	33	* register.
	34	*/
	35	void irq_gc_mask_disable_reg(struct irq_data *d)
	36	{
	37	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	38	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	39	u32 mask = d->mask;
7d828062 TG	40
7d828062 TG	41	irq_gc_lock(gc);
cfeaa93f	42	irq_reg_writel(mask, gc->reg_base + ct->regs.disable);
899f0e66	43	*ct->mask_cache &= ~mask;
7d828062 TG	44	irq_gc_unlock(gc);
	45	}
	46
	47	/**
ccc414f8	48	* irq_gc_mask_set_bit - Mask chip via setting bit in mask register
7d828062 TG	49	* @d: irq_data
	50	*
	51	* Chip has a single mask register. Values of this register are cached
	52	* and protected by gc->lock
	53	*/
	54	void irq_gc_mask_set_bit(struct irq_data *d)
	55	{
	56	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	57	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	58	u32 mask = d->mask;
7d828062 TG	59
7d828062 TG	60	irq_gc_lock(gc);
899f0e66 GF	61	*ct->mask_cache \|= mask;
899f0e66 GF	62	irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
7d828062 TG	63	irq_gc_unlock(gc);
7d828062 TG	64	}
d55f0cc4	65	EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
7d828062 TG	66
7d828062 TG	67	/**
ccc414f8	68	* irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
7d828062 TG	69	* @d: irq_data
	70	*
	71	* Chip has a single mask register. Values of this register are cached
	72	* and protected by gc->lock
	73	*/
	74	void irq_gc_mask_clr_bit(struct irq_data *d)
	75	{
	76	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	77	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	78	u32 mask = d->mask;
7d828062 TG	79
7d828062 TG	80	irq_gc_lock(gc);
899f0e66 GF	81	*ct->mask_cache &= ~mask;
899f0e66 GF	82	irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
7d828062 TG	83	irq_gc_unlock(gc);
7d828062 TG	84	}
d55f0cc4	85	EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
7d828062 TG	86
	87	/**
	88	* irq_gc_unmask_enable_reg - Unmask chip via enable register
	89	* @d: irq_data
	90	*
	91	* Chip has separate enable/disable registers instead of a single mask
	92	* register.
	93	*/
	94	void irq_gc_unmask_enable_reg(struct irq_data *d)
	95	{
	96	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	97	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	98	u32 mask = d->mask;
7d828062 TG	99
7d828062 TG	100	irq_gc_lock(gc);
cfeaa93f	101	irq_reg_writel(mask, gc->reg_base + ct->regs.enable);
899f0e66	102	*ct->mask_cache \|= mask;
7d828062 TG	103	irq_gc_unlock(gc);
	104	}
	105
	106	/**
659fb32d	107	* irq_gc_ack_set_bit - Ack pending interrupt via setting bit
7d828062 TG	108	* @d: irq_data
7d828062 TG	109	*/
659fb32d	110	void irq_gc_ack_set_bit(struct irq_data *d)
7d828062 TG	111	{
7d828062 TG	112	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	113	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	114	u32 mask = d->mask;
7d828062 TG	115
7d828062 TG	116	irq_gc_lock(gc);
cfeaa93f	117	irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
7d828062 TG	118	irq_gc_unlock(gc);
7d828062 TG	119	}
d55f0cc4	120	EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
7d828062	121
659fb32d SG	122	/**
	123	* irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
	124	* @d: irq_data
	125	*/
	126	void irq_gc_ack_clr_bit(struct irq_data *d)
	127	{
	128	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	129	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	130	u32 mask = ~d->mask;
659fb32d SG	131
659fb32d SG	132	irq_gc_lock(gc);
cfeaa93f	133	irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
659fb32d SG	134	irq_gc_unlock(gc);
	135	}
	136
7d828062	137	/**
37074c5a	138	* irq_gc_mask_disable_reg_and_ack - Mask and ack pending interrupt
7d828062 TG	139	* @d: irq_data
	140	*/
	141	void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
	142	{
	143	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	144	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	145	u32 mask = d->mask;
7d828062 TG	146
7d828062 TG	147	irq_gc_lock(gc);
cfeaa93f GF	148	irq_reg_writel(mask, gc->reg_base + ct->regs.mask);
cfeaa93f GF	149	irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
7d828062 TG	150	irq_gc_unlock(gc);
	151	}
	152
	153	/**
	154	* irq_gc_eoi - EOI interrupt
	155	* @d: irq_data
	156	*/
	157	void irq_gc_eoi(struct irq_data *d)
	158	{
	159	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	160	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	161	u32 mask = d->mask;
7d828062 TG	162
7d828062 TG	163	irq_gc_lock(gc);
cfeaa93f	164	irq_reg_writel(mask, gc->reg_base + ct->regs.eoi);
7d828062 TG	165	irq_gc_unlock(gc);
	166	}
	167
	168	/**
	169	* irq_gc_set_wake - Set/clr wake bit for an interrupt
ccc414f8 TG	170	* @d: irq_data
ccc414f8 TG	171	* @on: Indicates whether the wake bit should be set or cleared
7d828062 TG	172	*
	173	* For chips where the wake from suspend functionality is not
	174	* configured in a separate register and the wakeup active state is
	175	* just stored in a bitmask.
	176	*/
	177	int irq_gc_set_wake(struct irq_data *d, unsigned int on)
	178	{
	179	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
966dc736	180	u32 mask = d->mask;
7d828062 TG	181
	182	if (!(mask & gc->wake_enabled))
	183	return -EINVAL;
	184
	185	irq_gc_lock(gc);
	186	if (on)
	187	gc->wake_active \|= mask;
	188	else
	189	gc->wake_active &= ~mask;
	190	irq_gc_unlock(gc);
	191	return 0;
	192	}
	193
3528d82b TG	194	static void
	195	irq_init_generic_chip(struct irq_chip_generic gc, const char name,
	196	int num_ct, unsigned int irq_base,
	197	void __iomem *reg_base, irq_flow_handler_t handler)
	198	{
	199	raw_spin_lock_init(&gc->lock);
	200	gc->num_ct = num_ct;
	201	gc->irq_base = irq_base;
	202	gc->reg_base = reg_base;
	203	gc->chip_types->chip.name = name;
	204	gc->chip_types->handler = handler;
	205	}
	206
7d828062 TG	207	/**
	208	* irq_alloc_generic_chip - Allocate a generic chip and initialize it
	209	* @name: Name of the irq chip
	210	* @num_ct: Number of irq_chip_type instances associated with this
	211	* @irq_base: Interrupt base nr for this chip
	212	* @reg_base: Register base address (virtual)
	213	* @handler: Default flow handler associated with this chip
	214	*
	215	* Returns an initialized irq_chip_generic structure. The chip defaults
	216	* to the primary (index 0) irq_chip_type and @handler
	217	*/
	218	struct irq_chip_generic *
	219	irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
	220	void __iomem *reg_base, irq_flow_handler_t handler)
	221	{
	222	struct irq_chip_generic *gc;
	223	unsigned long sz = sizeof(gc) + num_ct sizeof(struct irq_chip_type);
	224
	225	gc = kzalloc(sz, GFP_KERNEL);
	226	if (gc) {
3528d82b TG	227	irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
3528d82b TG	228	handler);
7d828062 TG	229	}
	230	return gc;
	231	}
825de2e9	232	EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
7d828062	233
3528d82b TG	234	static void
	235	irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
	236	{
	237	struct irq_chip_type *ct = gc->chip_types;
	238	u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
	239	int i;
	240
	241	for (i = 0; i < gc->num_ct; i++) {
	242	if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
	243	mskptr = &ct[i].mask_cache_priv;
	244	mskreg = ct[i].regs.mask;
	245	}
	246	ct[i].mask_cache = mskptr;
	247	if (flags & IRQ_GC_INIT_MASK_CACHE)
	248	*mskptr = irq_reg_readl(gc->reg_base + mskreg);
	249	}
	250	}
	251
088f40b7 TG	252	/**
	253	* irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain
	254	* @d: irq domain for which to allocate chips
	255	* @irqs_per_chip: Number of interrupts each chip handles
	256	* @num_ct: Number of irq_chip_type instances associated with this
	257	* @name: Name of the irq chip
	258	* @handler: Default flow handler associated with these chips
	259	* @clr: IRQ_* bits to clear in the mapping function
	260	* @set: IRQ_* bits to set in the mapping function
6fff8314	261	* @gcflags: Generic chip specific setup flags
088f40b7 TG	262	*/
	263	int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
	264	int num_ct, const char *name,
	265	irq_flow_handler_t handler,
	266	unsigned int clr, unsigned int set,
	267	enum irq_gc_flags gcflags)
	268	{
	269	struct irq_domain_chip_generic *dgc;
	270	struct irq_chip_generic *gc;
	271	int numchips, sz, i;
	272	unsigned long flags;
	273	void *tmp;
	274
	275	if (d->gc)
	276	return -EBUSY;
	277
1aa0dd94	278	numchips = d->revmap_size / irqs_per_chip;
088f40b7 TG	279	if (!numchips)
	280	return -EINVAL;
	281
	282	/* Allocate a pointer, generic chip and chiptypes for each chip */
	283	sz = sizeof(dgc) + numchips sizeof(gc);
	284	sz += numchips * (sizeof(gc) + num_ct sizeof(struct irq_chip_type));
	285
	286	tmp = dgc = kzalloc(sz, GFP_KERNEL);
	287	if (!dgc)
	288	return -ENOMEM;
	289	dgc->irqs_per_chip = irqs_per_chip;
	290	dgc->num_chips = numchips;
	291	dgc->irq_flags_to_set = set;
	292	dgc->irq_flags_to_clear = clr;
	293	dgc->gc_flags = gcflags;
	294	d->gc = dgc;
	295
	296	/* Calc pointer to the first generic chip */
	297	tmp += sizeof(dgc) + numchips sizeof(gc);
	298	for (i = 0; i < numchips; i++) {
	299	/* Store the pointer to the generic chip */
	300	dgc->gc[i] = gc = tmp;
	301	irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
	302	NULL, handler);
	303	gc->domain = d;
	304	raw_spin_lock_irqsave(&gc_lock, flags);
	305	list_add_tail(&gc->list, &gc_list);
	306	raw_spin_unlock_irqrestore(&gc_lock, flags);
	307	/* Calc pointer to the next generic chip */
	308	tmp += sizeof(gc) + num_ct sizeof(struct irq_chip_type);
	309	}
0bb4afb4	310	d->name = name;
088f40b7 TG	311	return 0;
	312	}
	313	EXPORT_SYMBOL_GPL(irq_alloc_domain_generic_chips);
	314
	315	/**
	316	* irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
	317	* @d: irq domain pointer
	318	* @hw_irq: Hardware interrupt number
	319	*/
	320	struct irq_chip_generic *
	321	irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
	322	{
	323	struct irq_domain_chip_generic *dgc = d->gc;
	324	int idx;
	325
	326	if (!dgc)
	327	return NULL;
	328	idx = hw_irq / dgc->irqs_per_chip;
	329	if (idx >= dgc->num_chips)
	330	return NULL;
	331	return dgc->gc[idx];
	332	}
	333	EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
	334
7d828062 TG	335	/*
	336	* Separate lockdep class for interrupt chip which can nest irq_desc
	337	* lock.
	338	*/
	339	static struct lock_class_key irq_nested_lock_class;
	340
ccc414f8	341	/*
088f40b7 TG	342	* irq_map_generic_chip - Map a generic chip for an irq domain
	343	*/
	344	static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
	345	irq_hw_number_t hw_irq)
	346	{
	347	struct irq_data *data = irq_get_irq_data(virq);
	348	struct irq_domain_chip_generic *dgc = d->gc;
	349	struct irq_chip_generic *gc;
	350	struct irq_chip_type *ct;
	351	struct irq_chip *chip;
	352	unsigned long flags;
	353	int idx;
	354
	355	if (!d->gc)
	356	return -ENODEV;
	357
	358	idx = hw_irq / dgc->irqs_per_chip;
	359	if (idx >= dgc->num_chips)
	360	return -EINVAL;
	361	gc = dgc->gc[idx];
	362
	363	idx = hw_irq % dgc->irqs_per_chip;
	364
e8bd834f GL	365	if (test_bit(idx, &gc->unused))
	366	return -ENOTSUPP;
	367
088f40b7 TG	368	if (test_bit(idx, &gc->installed))
	369	return -EBUSY;
	370
	371	ct = gc->chip_types;
	372	chip = &ct->chip;
	373
	374	/* We only init the cache for the first mapping of a generic chip */
	375	if (!gc->installed) {
	376	raw_spin_lock_irqsave(&gc->lock, flags);
	377	irq_gc_init_mask_cache(gc, dgc->gc_flags);
	378	raw_spin_unlock_irqrestore(&gc->lock, flags);
	379	}
	380
	381	/* Mark the interrupt as installed */
	382	set_bit(idx, &gc->installed);
	383
	384	if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
	385	irq_set_lockdep_class(virq, &irq_nested_lock_class);
	386
	387	if (chip->irq_calc_mask)
	388	chip->irq_calc_mask(data);
	389	else
	390	data->mask = 1 << idx;
	391
	392	irq_set_chip_and_handler(virq, chip, ct->handler);
	393	irq_set_chip_data(virq, gc);
	394	irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
	395	return 0;
	396	}
	397
	398	struct irq_domain_ops irq_generic_chip_ops = {
	399	.map = irq_map_generic_chip,
	400	.xlate = irq_domain_xlate_onetwocell,
	401	};
	402	EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
	403
7d828062 TG	404	/**
	405	* irq_setup_generic_chip - Setup a range of interrupts with a generic chip
	406	* @gc: Generic irq chip holding all data
	407	* @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
	408	* @flags: Flags for initialization
	409	* @clr: IRQ_* bits to clear
	410	* @set: IRQ_* bits to set
	411	*
	412	* Set up max. 32 interrupts starting from gc->irq_base. Note, this
	413	* initializes all interrupts to the primary irq_chip_type and its
	414	* associated handler.
	415	*/
	416	void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
	417	enum irq_gc_flags flags, unsigned int clr,
	418	unsigned int set)
	419	{
	420	struct irq_chip_type *ct = gc->chip_types;
d0051816	421	struct irq_chip *chip = &ct->chip;
7d828062 TG	422	unsigned int i;
7d828062 TG	423
cfefd21e TG	424	raw_spin_lock(&gc_lock);
	425	list_add_tail(&gc->list, &gc_list);
	426	raw_spin_unlock(&gc_lock);
	427
3528d82b	428	irq_gc_init_mask_cache(gc, flags);
899f0e66	429
7d828062	430	for (i = gc->irq_base; msk; msk >>= 1, i++) {
1dd75f91	431	if (!(msk & 0x01))
7d828062 TG	432	continue;
	433
	434	if (flags & IRQ_GC_INIT_NESTED_LOCK)
	435	irq_set_lockdep_class(i, &irq_nested_lock_class);
	436
966dc736 TG	437	if (!(flags & IRQ_GC_NO_MASK)) {
	438	struct irq_data *d = irq_get_irq_data(i);
	439
d0051816 TG	440	if (chip->irq_calc_mask)
	441	chip->irq_calc_mask(d);
	442	else
	443	d->mask = 1 << (i - gc->irq_base);
966dc736	444	}
d0051816	445	irq_set_chip_and_handler(i, chip, ct->handler);
7d828062 TG	446	irq_set_chip_data(i, gc);
	447	irq_modify_status(i, clr, set);
	448	}
	449	gc->irq_cnt = i - gc->irq_base;
	450	}
825de2e9	451	EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
7d828062 TG	452
	453	/**
	454	* irq_setup_alt_chip - Switch to alternative chip
	455	* @d: irq_data for this interrupt
ccc414f8	456	* @type: Flow type to be initialized
7d828062 TG	457	*
	458	* Only to be called from chip->irq_set_type() callbacks.
	459	*/
	460	int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
	461	{
	462	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	463	struct irq_chip_type *ct = gc->chip_types;
	464	unsigned int i;
	465
	466	for (i = 0; i < gc->num_ct; i++, ct++) {
	467	if (ct->type & type) {
	468	d->chip = &ct->chip;
	469	irq_data_to_desc(d)->handle_irq = ct->handler;
	470	return 0;
	471	}
	472	}
	473	return -EINVAL;
	474	}
825de2e9	475	EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
cfefd21e TG	476
	477	/**
	478	* irq_remove_generic_chip - Remove a chip
	479	* @gc: Generic irq chip holding all data
	480	* @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
	481	* @clr: IRQ_* bits to clear
	482	* @set: IRQ_* bits to set
	483	*
	484	* Remove up to 32 interrupts starting from gc->irq_base.
	485	*/
	486	void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
	487	unsigned int clr, unsigned int set)
	488	{
	489	unsigned int i = gc->irq_base;
	490
	491	raw_spin_lock(&gc_lock);
	492	list_del(&gc->list);
	493	raw_spin_unlock(&gc_lock);
	494
	495	for (; msk; msk >>= 1, i++) {
1dd75f91	496	if (!(msk & 0x01))
cfefd21e TG	497	continue;
	498
	499	/* Remove handler first. That will mask the irq line */
	500	irq_set_handler(i, NULL);
	501	irq_set_chip(i, &no_irq_chip);
	502	irq_set_chip_data(i, NULL);
	503	irq_modify_status(i, clr, set);
	504	}
	505	}
825de2e9	506	EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
cfefd21e	507
088f40b7 TG	508	static struct irq_data irq_gc_get_irq_data(struct irq_chip_generic gc)
	509	{
	510	unsigned int virq;
	511
	512	if (!gc->domain)
	513	return irq_get_irq_data(gc->irq_base);
	514
	515	/*
	516	* We don't know which of the irqs has been actually
	517	* installed. Use the first one.
	518	*/
	519	if (!gc->installed)
	520	return NULL;
	521
	522	virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
	523	return virq ? irq_get_irq_data(virq) : NULL;
	524	}
	525
cfefd21e TG	526	#ifdef CONFIG_PM
	527	static int irq_gc_suspend(void)
	528	{
	529	struct irq_chip_generic *gc;
	530
	531	list_for_each_entry(gc, &gc_list, list) {
	532	struct irq_chip_type *ct = gc->chip_types;
	533
088f40b7 TG	534	if (ct->chip.irq_suspend) {
	535	struct irq_data *data = irq_gc_get_irq_data(gc);
	536
	537	if (data)
	538	ct->chip.irq_suspend(data);
	539	}
cfefd21e TG	540	}
	541	return 0;
	542	}
	543
	544	static void irq_gc_resume(void)
	545	{
	546	struct irq_chip_generic *gc;
	547
	548	list_for_each_entry(gc, &gc_list, list) {
	549	struct irq_chip_type *ct = gc->chip_types;
	550
088f40b7 TG	551	if (ct->chip.irq_resume) {
	552	struct irq_data *data = irq_gc_get_irq_data(gc);
	553
	554	if (data)
	555	ct->chip.irq_resume(data);
	556	}
cfefd21e TG	557	}
	558	}
	559	#else
	560	#define irq_gc_suspend NULL
	561	#define irq_gc_resume NULL
	562	#endif
	563
	564	static void irq_gc_shutdown(void)
	565	{
	566	struct irq_chip_generic *gc;
	567
	568	list_for_each_entry(gc, &gc_list, list) {
	569	struct irq_chip_type *ct = gc->chip_types;
	570
088f40b7 TG	571	if (ct->chip.irq_pm_shutdown) {
	572	struct irq_data *data = irq_gc_get_irq_data(gc);
	573
	574	if (data)
	575	ct->chip.irq_pm_shutdown(data);
	576	}
cfefd21e TG	577	}
	578	}
	579
	580	static struct syscore_ops irq_gc_syscore_ops = {
	581	.suspend = irq_gc_suspend,
	582	.resume = irq_gc_resume,
	583	.shutdown = irq_gc_shutdown,
	584	};
	585
	586	static int __init irq_gc_init_ops(void)
	587	{
	588	register_syscore_ops(&irq_gc_syscore_ops);
	589	return 0;
	590	}
	591	device_initcall(irq_gc_init_ops);