[mirror_ubuntu-bionic-kernel.git] / kernel / irq / generic-chip.c

/*
 * Library implementing the most common irq chip callback functions
 *
 * Copyright (C) 2011, Thomas Gleixner
 */
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/syscore_ops.h>

#include "internals.h"

static LIST_HEAD(gc_list);
static DEFINE_RAW_SPINLOCK(gc_lock);

/**
 * irq_gc_noop - NOOP function
 * @d: irq_data
 */
void irq_gc_noop(struct irq_data *d)
{
}

/**
 * irq_gc_mask_disable_reg - Mask chip via disable register
 * @d: irq_data
 *
 * Chip has separate enable/disable registers instead of a single mask
 * register.
 */
void irq_gc_mask_disable_reg(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(gc, mask, ct->regs.disable);
	*ct->mask_cache &= ~mask;
	irq_gc_unlock(gc);
}

/**
 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
 * @d: irq_data
 *
 * Chip has a single mask register. Values of this register are cached
 * and protected by gc->lock
 */
void irq_gc_mask_set_bit(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	*ct->mask_cache |= mask;
	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
	irq_gc_unlock(gc);
}
EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);

/**
 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
 * @d: irq_data
 *
 * Chip has a single mask register. Values of this register are cached
 * and protected by gc->lock
 */
void irq_gc_mask_clr_bit(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	*ct->mask_cache &= ~mask;
	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
	irq_gc_unlock(gc);
}
EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);

/**
 * irq_gc_unmask_enable_reg - Unmask chip via enable register
 * @d: irq_data
 *
 * Chip has separate enable/disable registers instead of a single mask
 * register.
 */
void irq_gc_unmask_enable_reg(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(gc, mask, ct->regs.enable);
	*ct->mask_cache |= mask;
	irq_gc_unlock(gc);
}

/**
 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
 * @d: irq_data
 */
void irq_gc_ack_set_bit(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(gc, mask, ct->regs.ack);
	irq_gc_unlock(gc);
}
EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);

/**
 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
 * @d: irq_data
 */
void irq_gc_ack_clr_bit(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = ~d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(gc, mask, ct->regs.ack);
	irq_gc_unlock(gc);
}

/**
 * irq_gc_mask_disable_reg_and_ack - Mask and ack pending interrupt
 * @d: irq_data
 */
void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(gc, mask, ct->regs.mask);
	irq_reg_writel(gc, mask, ct->regs.ack);
	irq_gc_unlock(gc);
}

/**
 * irq_gc_eoi - EOI interrupt
 * @d: irq_data
 */
void irq_gc_eoi(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(gc, mask, ct->regs.eoi);
	irq_gc_unlock(gc);
}

/**
 * irq_gc_set_wake - Set/clr wake bit for an interrupt
 * @d:  irq_data
 * @on: Indicates whether the wake bit should be set or cleared
 *
 * For chips where the wake from suspend functionality is not
 * configured in a separate register and the wakeup active state is
 * just stored in a bitmask.
 */
int irq_gc_set_wake(struct irq_data *d, unsigned int on)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	u32 mask = d->mask;

	if (!(mask & gc->wake_enabled))
		return -EINVAL;

	irq_gc_lock(gc);
	if (on)
		gc->wake_active |= mask;
	else
		gc->wake_active &= ~mask;
	irq_gc_unlock(gc);
	return 0;
}

static u32 irq_readl_be(void __iomem *addr)
{
	return ioread32be(addr);
}

static void irq_writel_be(u32 val, void __iomem *addr)
{
	iowrite32be(val, addr);
}

void irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
			   int num_ct, unsigned int irq_base,
			   void __iomem *reg_base, irq_flow_handler_t handler)
{
	raw_spin_lock_init(&gc->lock);
	gc->num_ct = num_ct;
	gc->irq_base = irq_base;
	gc->reg_base = reg_base;
	gc->chip_types->chip.name = name;
	gc->chip_types->handler = handler;
}

/**
 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
 * @name:	Name of the irq chip
 * @num_ct:	Number of irq_chip_type instances associated with this
 * @irq_base:	Interrupt base nr for this chip
 * @reg_base:	Register base address (virtual)
 * @handler:	Default flow handler associated with this chip
 *
 * Returns an initialized irq_chip_generic structure. The chip defaults
 * to the primary (index 0) irq_chip_type and @handler
 */
struct irq_chip_generic *
irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
		       void __iomem *reg_base, irq_flow_handler_t handler)
{
	struct irq_chip_generic *gc;
	unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);

	gc = kzalloc(sz, GFP_KERNEL);
	if (gc) {
		irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
				      handler);
	}
	return gc;
}
EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);

static void
irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
{
	struct irq_chip_type *ct = gc->chip_types;
	u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
	int i;

	for (i = 0; i < gc->num_ct; i++) {
		if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
			mskptr = &ct[i].mask_cache_priv;
			mskreg = ct[i].regs.mask;
		}
		ct[i].mask_cache = mskptr;
		if (flags & IRQ_GC_INIT_MASK_CACHE)
			*mskptr = irq_reg_readl(gc, mskreg);
	}
}

/**
 * __irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain
 * @d:			irq domain for which to allocate chips
 * @irqs_per_chip:	Number of interrupts each chip handles (max 32)
 * @num_ct:		Number of irq_chip_type instances associated with this
 * @name:		Name of the irq chip
 * @handler:		Default flow handler associated with these chips
 * @clr:		IRQ_* bits to clear in the mapping function
 * @set:		IRQ_* bits to set in the mapping function
 * @gcflags:		Generic chip specific setup flags
 */
int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
				     int num_ct, const char *name,
				     irq_flow_handler_t handler,
				     unsigned int clr, unsigned int set,
				     enum irq_gc_flags gcflags)
{
	struct irq_domain_chip_generic *dgc;
	struct irq_chip_generic *gc;
	int numchips, sz, i;
	unsigned long flags;
	void *tmp;

	if (d->gc)
		return -EBUSY;

	numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);
	if (!numchips)
		return -EINVAL;

	/* Allocate a pointer, generic chip and chiptypes for each chip */
	sz = sizeof(*dgc) + numchips * sizeof(gc);
	sz += numchips * (sizeof(*gc) + num_ct * sizeof(struct irq_chip_type));

	tmp = dgc = kzalloc(sz, GFP_KERNEL);
	if (!dgc)
		return -ENOMEM;
	dgc->irqs_per_chip = irqs_per_chip;
	dgc->num_chips = numchips;
	dgc->irq_flags_to_set = set;
	dgc->irq_flags_to_clear = clr;
	dgc->gc_flags = gcflags;
	d->gc = dgc;

	/* Calc pointer to the first generic chip */
	tmp += sizeof(*dgc) + numchips * sizeof(gc);
	for (i = 0; i < numchips; i++) {
		/* Store the pointer to the generic chip */
		dgc->gc[i] = gc = tmp;
		irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
				      NULL, handler);

		gc->domain = d;
		if (gcflags & IRQ_GC_BE_IO) {
			gc->reg_readl = &irq_readl_be;
			gc->reg_writel = &irq_writel_be;
		}

		raw_spin_lock_irqsave(&gc_lock, flags);
		list_add_tail(&gc->list, &gc_list);
		raw_spin_unlock_irqrestore(&gc_lock, flags);
		/* Calc pointer to the next generic chip */
		tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
	}
	d->name = name;
	return 0;
}
EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);

static struct irq_chip_generic *
__irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
{
	struct irq_domain_chip_generic *dgc = d->gc;
	int idx;

	if (!dgc)
		return ERR_PTR(-ENODEV);
	idx = hw_irq / dgc->irqs_per_chip;
	if (idx >= dgc->num_chips)
		return ERR_PTR(-EINVAL);
	return dgc->gc[idx];
}

/**
 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
 * @d:			irq domain pointer
 * @hw_irq:		Hardware interrupt number
 */
struct irq_chip_generic *
irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
{
	struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);

	return !IS_ERR(gc) ? gc : NULL;
}
EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);

/*
 * Separate lockdep class for interrupt chip which can nest irq_desc
 * lock.
 */
static struct lock_class_key irq_nested_lock_class;

/*
 * irq_map_generic_chip - Map a generic chip for an irq domain
 */
int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
			 irq_hw_number_t hw_irq)
{
	struct irq_data *data = irq_domain_get_irq_data(d, virq);
	struct irq_domain_chip_generic *dgc = d->gc;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	struct irq_chip *chip;
	unsigned long flags;
	int idx;

	gc = __irq_get_domain_generic_chip(d, hw_irq);
	if (IS_ERR(gc))
		return PTR_ERR(gc);

	idx = hw_irq % dgc->irqs_per_chip;

	if (test_bit(idx, &gc->unused))
		return -ENOTSUPP;

	if (test_bit(idx, &gc->installed))
		return -EBUSY;

	ct = gc->chip_types;
	chip = &ct->chip;

	/* We only init the cache for the first mapping of a generic chip */
	if (!gc->installed) {
		raw_spin_lock_irqsave(&gc->lock, flags);
		irq_gc_init_mask_cache(gc, dgc->gc_flags);
		raw_spin_unlock_irqrestore(&gc->lock, flags);
	}

	/* Mark the interrupt as installed */
	set_bit(idx, &gc->installed);

	if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
		irq_set_lockdep_class(virq, &irq_nested_lock_class);

	if (chip->irq_calc_mask)
		chip->irq_calc_mask(data);
	else
		data->mask = 1 << idx;

	irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
	irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
	return 0;
}

static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
{
	struct irq_data *data = irq_domain_get_irq_data(d, virq);
	struct irq_domain_chip_generic *dgc = d->gc;
	unsigned int hw_irq = data->hwirq;
	struct irq_chip_generic *gc;
	int irq_idx;

	gc = irq_get_domain_generic_chip(d, hw_irq);
	if (!gc)
		return;

	irq_idx = hw_irq % dgc->irqs_per_chip;

	clear_bit(irq_idx, &gc->installed);
	irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL,
			    NULL);

}

struct irq_domain_ops irq_generic_chip_ops = {
	.map	= irq_map_generic_chip,
	.unmap  = irq_unmap_generic_chip,
	.xlate	= irq_domain_xlate_onetwocell,
};
EXPORT_SYMBOL_GPL(irq_generic_chip_ops);

/**
 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
 * @gc:		Generic irq chip holding all data
 * @msk:	Bitmask holding the irqs to initialize relative to gc->irq_base
 * @flags:	Flags for initialization
 * @clr:	IRQ_* bits to clear
 * @set:	IRQ_* bits to set
 *
 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
 * initializes all interrupts to the primary irq_chip_type and its
 * associated handler.
 */
void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
			    enum irq_gc_flags flags, unsigned int clr,
			    unsigned int set)
{
	struct irq_chip_type *ct = gc->chip_types;
	struct irq_chip *chip = &ct->chip;
	unsigned int i;

	raw_spin_lock(&gc_lock);
	list_add_tail(&gc->list, &gc_list);
	raw_spin_unlock(&gc_lock);

	irq_gc_init_mask_cache(gc, flags);

	for (i = gc->irq_base; msk; msk >>= 1, i++) {
		if (!(msk & 0x01))
			continue;

		if (flags & IRQ_GC_INIT_NESTED_LOCK)
			irq_set_lockdep_class(i, &irq_nested_lock_class);

		if (!(flags & IRQ_GC_NO_MASK)) {
			struct irq_data *d = irq_get_irq_data(i);

			if (chip->irq_calc_mask)
				chip->irq_calc_mask(d);
			else
				d->mask = 1 << (i - gc->irq_base);
		}
		irq_set_chip_and_handler(i, chip, ct->handler);
		irq_set_chip_data(i, gc);
		irq_modify_status(i, clr, set);
	}
	gc->irq_cnt = i - gc->irq_base;
}
EXPORT_SYMBOL_GPL(irq_setup_generic_chip);

/**
 * irq_setup_alt_chip - Switch to alternative chip
 * @d:		irq_data for this interrupt
 * @type:	Flow type to be initialized
 *
 * Only to be called from chip->irq_set_type() callbacks.
 */
int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = gc->chip_types;
	unsigned int i;

	for (i = 0; i < gc->num_ct; i++, ct++) {
		if (ct->type & type) {
			d->chip = &ct->chip;
			irq_data_to_desc(d)->handle_irq = ct->handler;
			return 0;
		}
	}
	return -EINVAL;
}
EXPORT_SYMBOL_GPL(irq_setup_alt_chip);

/**
 * irq_remove_generic_chip - Remove a chip
 * @gc:		Generic irq chip holding all data
 * @msk:	Bitmask holding the irqs to initialize relative to gc->irq_base
 * @clr:	IRQ_* bits to clear
 * @set:	IRQ_* bits to set
 *
 * Remove up to 32 interrupts starting from gc->irq_base.
 */
void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
			     unsigned int clr, unsigned int set)
{
	unsigned int i = gc->irq_base;

	raw_spin_lock(&gc_lock);
	list_del(&gc->list);
	raw_spin_unlock(&gc_lock);

	for (; msk; msk >>= 1, i++) {
		if (!(msk & 0x01))
			continue;

		/* Remove handler first. That will mask the irq line */
		irq_set_handler(i, NULL);
		irq_set_chip(i, &no_irq_chip);
		irq_set_chip_data(i, NULL);
		irq_modify_status(i, clr, set);
	}
}
EXPORT_SYMBOL_GPL(irq_remove_generic_chip);

static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
{
	unsigned int virq;

	if (!gc->domain)
		return irq_get_irq_data(gc->irq_base);

	/*
	 * We don't know which of the irqs has been actually
	 * installed. Use the first one.
	 */
	if (!gc->installed)
		return NULL;

	virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
	return virq ? irq_get_irq_data(virq) : NULL;
}

#ifdef CONFIG_PM
static int irq_gc_suspend(void)
{
	struct irq_chip_generic *gc;

	list_for_each_entry(gc, &gc_list, list) {
		struct irq_chip_type *ct = gc->chip_types;

		if (ct->chip.irq_suspend) {
			struct irq_data *data = irq_gc_get_irq_data(gc);

			if (data)
				ct->chip.irq_suspend(data);
		}

		if (gc->suspend)
			gc->suspend(gc);
	}
	return 0;
}

static void irq_gc_resume(void)
{
	struct irq_chip_generic *gc;

	list_for_each_entry(gc, &gc_list, list) {
		struct irq_chip_type *ct = gc->chip_types;

		if (gc->resume)
			gc->resume(gc);

		if (ct->chip.irq_resume) {
			struct irq_data *data = irq_gc_get_irq_data(gc);

			if (data)
				ct->chip.irq_resume(data);
		}
	}
}
#else
#define irq_gc_suspend NULL
#define irq_gc_resume NULL
#endif

static void irq_gc_shutdown(void)
{
	struct irq_chip_generic *gc;

	list_for_each_entry(gc, &gc_list, list) {
		struct irq_chip_type *ct = gc->chip_types;

		if (ct->chip.irq_pm_shutdown) {
			struct irq_data *data = irq_gc_get_irq_data(gc);

			if (data)
				ct->chip.irq_pm_shutdown(data);
		}
	}
}

static struct syscore_ops irq_gc_syscore_ops = {
	.suspend = irq_gc_suspend,
	.resume = irq_gc_resume,
	.shutdown = irq_gc_shutdown,
};

static int __init irq_gc_init_ops(void)
{
	register_syscore_ops(&irq_gc_syscore_ops);
	return 0;
}
device_initcall(irq_gc_init_ops);
Commit	Line	Data
7d828062 TG	1	/*
	2	* Library implementing the most common irq chip callback functions
	3	*
	4	* Copyright (C) 2011, Thomas Gleixner
	5	*/
	6	#include <linux/io.h>
	7	#include <linux/irq.h>
	8	#include <linux/slab.h>
6e5fdeed	9	#include <linux/export.h>
088f40b7	10	#include <linux/irqdomain.h>
7d828062 TG	11	#include <linux/interrupt.h>
7d828062 TG	12	#include <linux/kernel_stat.h>
cfefd21e	13	#include <linux/syscore_ops.h>
7d828062 TG	14
	15	#include "internals.h"
	16
cfefd21e TG	17	static LIST_HEAD(gc_list);
	18	static DEFINE_RAW_SPINLOCK(gc_lock);
	19
7d828062 TG	20	/**
	21	* irq_gc_noop - NOOP function
	22	* @d: irq_data
	23	*/
	24	void irq_gc_noop(struct irq_data *d)
	25	{
	26	}
	27
	28	/**
	29	* irq_gc_mask_disable_reg - Mask chip via disable register
	30	* @d: irq_data
	31	*
	32	* Chip has separate enable/disable registers instead of a single mask
	33	* register.
	34	*/
	35	void irq_gc_mask_disable_reg(struct irq_data *d)
	36	{
	37	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	38	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	39	u32 mask = d->mask;
7d828062 TG	40
7d828062 TG	41	irq_gc_lock(gc);
332fd7c4	42	irq_reg_writel(gc, mask, ct->regs.disable);
899f0e66	43	*ct->mask_cache &= ~mask;
7d828062 TG	44	irq_gc_unlock(gc);
	45	}
	46
	47	/**
ccc414f8	48	* irq_gc_mask_set_bit - Mask chip via setting bit in mask register
7d828062 TG	49	* @d: irq_data
	50	*
	51	* Chip has a single mask register. Values of this register are cached
	52	* and protected by gc->lock
	53	*/
	54	void irq_gc_mask_set_bit(struct irq_data *d)
	55	{
	56	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	57	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	58	u32 mask = d->mask;
7d828062 TG	59
7d828062 TG	60	irq_gc_lock(gc);
899f0e66	61	*ct->mask_cache \|= mask;
332fd7c4	62	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
7d828062 TG	63	irq_gc_unlock(gc);
7d828062 TG	64	}
d55f0cc4	65	EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
7d828062 TG	66
7d828062 TG	67	/**
ccc414f8	68	* irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
7d828062 TG	69	* @d: irq_data
	70	*
	71	* Chip has a single mask register. Values of this register are cached
	72	* and protected by gc->lock
	73	*/
	74	void irq_gc_mask_clr_bit(struct irq_data *d)
	75	{
	76	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	77	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	78	u32 mask = d->mask;
7d828062 TG	79
7d828062 TG	80	irq_gc_lock(gc);
899f0e66	81	*ct->mask_cache &= ~mask;
332fd7c4	82	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
7d828062 TG	83	irq_gc_unlock(gc);
7d828062 TG	84	}
d55f0cc4	85	EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
7d828062 TG	86
	87	/**
	88	* irq_gc_unmask_enable_reg - Unmask chip via enable register
	89	* @d: irq_data
	90	*
	91	* Chip has separate enable/disable registers instead of a single mask
	92	* register.
	93	*/
	94	void irq_gc_unmask_enable_reg(struct irq_data *d)
	95	{
	96	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	97	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	98	u32 mask = d->mask;
7d828062 TG	99
7d828062 TG	100	irq_gc_lock(gc);
332fd7c4	101	irq_reg_writel(gc, mask, ct->regs.enable);
899f0e66	102	*ct->mask_cache \|= mask;
7d828062 TG	103	irq_gc_unlock(gc);
	104	}
	105
	106	/**
659fb32d	107	* irq_gc_ack_set_bit - Ack pending interrupt via setting bit
7d828062 TG	108	* @d: irq_data
7d828062 TG	109	*/
659fb32d	110	void irq_gc_ack_set_bit(struct irq_data *d)
7d828062 TG	111	{
7d828062 TG	112	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	113	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	114	u32 mask = d->mask;
7d828062 TG	115
7d828062 TG	116	irq_gc_lock(gc);
332fd7c4	117	irq_reg_writel(gc, mask, ct->regs.ack);
7d828062 TG	118	irq_gc_unlock(gc);
7d828062 TG	119	}
d55f0cc4	120	EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
7d828062	121
659fb32d SG	122	/**
	123	* irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
	124	* @d: irq_data
	125	*/
	126	void irq_gc_ack_clr_bit(struct irq_data *d)
	127	{
	128	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	129	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	130	u32 mask = ~d->mask;
659fb32d SG	131
659fb32d SG	132	irq_gc_lock(gc);
332fd7c4	133	irq_reg_writel(gc, mask, ct->regs.ack);
659fb32d SG	134	irq_gc_unlock(gc);
	135	}
	136
7d828062	137	/**
37074c5a	138	* irq_gc_mask_disable_reg_and_ack - Mask and ack pending interrupt
7d828062 TG	139	* @d: irq_data
	140	*/
	141	void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
	142	{
	143	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	144	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	145	u32 mask = d->mask;
7d828062 TG	146
7d828062 TG	147	irq_gc_lock(gc);
332fd7c4 KC	148	irq_reg_writel(gc, mask, ct->regs.mask);
332fd7c4 KC	149	irq_reg_writel(gc, mask, ct->regs.ack);
7d828062 TG	150	irq_gc_unlock(gc);
	151	}
	152
	153	/**
	154	* irq_gc_eoi - EOI interrupt
	155	* @d: irq_data
	156	*/
	157	void irq_gc_eoi(struct irq_data *d)
	158	{
	159	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
cfeaa93f	160	struct irq_chip_type *ct = irq_data_get_chip_type(d);
966dc736	161	u32 mask = d->mask;
7d828062 TG	162
7d828062 TG	163	irq_gc_lock(gc);
332fd7c4	164	irq_reg_writel(gc, mask, ct->regs.eoi);
7d828062 TG	165	irq_gc_unlock(gc);
	166	}
	167
	168	/**
	169	* irq_gc_set_wake - Set/clr wake bit for an interrupt
ccc414f8 TG	170	* @d: irq_data
ccc414f8 TG	171	* @on: Indicates whether the wake bit should be set or cleared
7d828062 TG	172	*
	173	* For chips where the wake from suspend functionality is not
	174	* configured in a separate register and the wakeup active state is
	175	* just stored in a bitmask.
	176	*/
	177	int irq_gc_set_wake(struct irq_data *d, unsigned int on)
	178	{
	179	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
966dc736	180	u32 mask = d->mask;
7d828062 TG	181
	182	if (!(mask & gc->wake_enabled))
	183	return -EINVAL;
	184
	185	irq_gc_lock(gc);
	186	if (on)
	187	gc->wake_active \|= mask;
	188	else
	189	gc->wake_active &= ~mask;
	190	irq_gc_unlock(gc);
	191	return 0;
	192	}
	193
b7905595 KC	194	static u32 irq_readl_be(void __iomem *addr)
	195	{
	196	return ioread32be(addr);
	197	}
	198
	199	static void irq_writel_be(u32 val, void __iomem *addr)
	200	{
	201	iowrite32be(val, addr);
	202	}
	203
f1602039 BG	204	void irq_init_generic_chip(struct irq_chip_generic gc, const char name,
	205	int num_ct, unsigned int irq_base,
	206	void __iomem *reg_base, irq_flow_handler_t handler)
3528d82b TG	207	{
	208	raw_spin_lock_init(&gc->lock);
	209	gc->num_ct = num_ct;
	210	gc->irq_base = irq_base;
	211	gc->reg_base = reg_base;
	212	gc->chip_types->chip.name = name;
	213	gc->chip_types->handler = handler;
	214	}
	215
7d828062 TG	216	/**
	217	* irq_alloc_generic_chip - Allocate a generic chip and initialize it
	218	* @name: Name of the irq chip
	219	* @num_ct: Number of irq_chip_type instances associated with this
	220	* @irq_base: Interrupt base nr for this chip
	221	* @reg_base: Register base address (virtual)
	222	* @handler: Default flow handler associated with this chip
	223	*
	224	* Returns an initialized irq_chip_generic structure. The chip defaults
	225	* to the primary (index 0) irq_chip_type and @handler
	226	*/
	227	struct irq_chip_generic *
	228	irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
	229	void __iomem *reg_base, irq_flow_handler_t handler)
	230	{
	231	struct irq_chip_generic *gc;
	232	unsigned long sz = sizeof(gc) + num_ct sizeof(struct irq_chip_type);
	233
	234	gc = kzalloc(sz, GFP_KERNEL);
	235	if (gc) {
3528d82b TG	236	irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
3528d82b TG	237	handler);
7d828062 TG	238	}
	239	return gc;
	240	}
825de2e9	241	EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
7d828062	242
3528d82b TG	243	static void
	244	irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
	245	{
	246	struct irq_chip_type *ct = gc->chip_types;
	247	u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
	248	int i;
	249
	250	for (i = 0; i < gc->num_ct; i++) {
	251	if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
	252	mskptr = &ct[i].mask_cache_priv;
	253	mskreg = ct[i].regs.mask;
	254	}
	255	ct[i].mask_cache = mskptr;
	256	if (flags & IRQ_GC_INIT_MASK_CACHE)
332fd7c4	257	*mskptr = irq_reg_readl(gc, mskreg);
3528d82b TG	258	}
	259	}
	260
088f40b7	261	/**
f88eecfe	262	* __irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain
088f40b7	263	* @d: irq domain for which to allocate chips
f88eecfe	264	* @irqs_per_chip: Number of interrupts each chip handles (max 32)
088f40b7 TG	265	* @num_ct: Number of irq_chip_type instances associated with this
	266	* @name: Name of the irq chip
	267	* @handler: Default flow handler associated with these chips
	268	* @clr: IRQ_* bits to clear in the mapping function
	269	* @set: IRQ_* bits to set in the mapping function
6fff8314	270	* @gcflags: Generic chip specific setup flags
088f40b7	271	*/
f88eecfe SF	272	int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
	273	int num_ct, const char *name,
	274	irq_flow_handler_t handler,
	275	unsigned int clr, unsigned int set,
	276	enum irq_gc_flags gcflags)
088f40b7 TG	277	{
	278	struct irq_domain_chip_generic *dgc;
	279	struct irq_chip_generic *gc;
	280	int numchips, sz, i;
	281	unsigned long flags;
	282	void *tmp;
	283
	284	if (d->gc)
	285	return -EBUSY;
	286
505608d2	287	numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);
088f40b7 TG	288	if (!numchips)
	289	return -EINVAL;
	290
	291	/* Allocate a pointer, generic chip and chiptypes for each chip */
	292	sz = sizeof(dgc) + numchips sizeof(gc);
	293	sz += numchips * (sizeof(gc) + num_ct sizeof(struct irq_chip_type));
	294
	295	tmp = dgc = kzalloc(sz, GFP_KERNEL);
	296	if (!dgc)
	297	return -ENOMEM;
	298	dgc->irqs_per_chip = irqs_per_chip;
	299	dgc->num_chips = numchips;
	300	dgc->irq_flags_to_set = set;
	301	dgc->irq_flags_to_clear = clr;
	302	dgc->gc_flags = gcflags;
	303	d->gc = dgc;
	304
	305	/* Calc pointer to the first generic chip */
	306	tmp += sizeof(dgc) + numchips sizeof(gc);
	307	for (i = 0; i < numchips; i++) {
	308	/* Store the pointer to the generic chip */
	309	dgc->gc[i] = gc = tmp;
	310	irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
	311	NULL, handler);
b7905595	312
088f40b7	313	gc->domain = d;
b7905595 KC	314	if (gcflags & IRQ_GC_BE_IO) {
	315	gc->reg_readl = &irq_readl_be;
	316	gc->reg_writel = &irq_writel_be;
	317	}
	318
088f40b7 TG	319	raw_spin_lock_irqsave(&gc_lock, flags);
	320	list_add_tail(&gc->list, &gc_list);
	321	raw_spin_unlock_irqrestore(&gc_lock, flags);
	322	/* Calc pointer to the next generic chip */
	323	tmp += sizeof(gc) + num_ct sizeof(struct irq_chip_type);
	324	}
0bb4afb4	325	d->name = name;
088f40b7 TG	326	return 0;
088f40b7 TG	327	}
f88eecfe	328	EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);
088f40b7	329
f0c450ea SF	330	static struct irq_chip_generic *
	331	__irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
	332	{
	333	struct irq_domain_chip_generic *dgc = d->gc;
	334	int idx;
	335
	336	if (!dgc)
	337	return ERR_PTR(-ENODEV);
	338	idx = hw_irq / dgc->irqs_per_chip;
	339	if (idx >= dgc->num_chips)
	340	return ERR_PTR(-EINVAL);
	341	return dgc->gc[idx];
	342	}
	343
088f40b7 TG	344	/**
	345	* irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
	346	* @d: irq domain pointer
	347	* @hw_irq: Hardware interrupt number
	348	*/
	349	struct irq_chip_generic *
	350	irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
	351	{
f0c450ea	352	struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);
088f40b7	353
f0c450ea	354	return !IS_ERR(gc) ? gc : NULL;
088f40b7 TG	355	}
	356	EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
	357
7d828062 TG	358	/*
	359	* Separate lockdep class for interrupt chip which can nest irq_desc
	360	* lock.
	361	*/
	362	static struct lock_class_key irq_nested_lock_class;
	363
ccc414f8	364	/*
088f40b7 TG	365	* irq_map_generic_chip - Map a generic chip for an irq domain
088f40b7 TG	366	*/
a5152c8a BB	367	int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
a5152c8a BB	368	irq_hw_number_t hw_irq)
088f40b7	369	{
c5863484	370	struct irq_data *data = irq_domain_get_irq_data(d, virq);
088f40b7 TG	371	struct irq_domain_chip_generic *dgc = d->gc;
	372	struct irq_chip_generic *gc;
	373	struct irq_chip_type *ct;
	374	struct irq_chip *chip;
	375	unsigned long flags;
	376	int idx;
	377
f0c450ea SF	378	gc = __irq_get_domain_generic_chip(d, hw_irq);
	379	if (IS_ERR(gc))
	380	return PTR_ERR(gc);
088f40b7 TG	381
	382	idx = hw_irq % dgc->irqs_per_chip;
	383
e8bd834f GL	384	if (test_bit(idx, &gc->unused))
	385	return -ENOTSUPP;
	386
088f40b7 TG	387	if (test_bit(idx, &gc->installed))
	388	return -EBUSY;
	389
	390	ct = gc->chip_types;
	391	chip = &ct->chip;
	392
	393	/* We only init the cache for the first mapping of a generic chip */
	394	if (!gc->installed) {
	395	raw_spin_lock_irqsave(&gc->lock, flags);
	396	irq_gc_init_mask_cache(gc, dgc->gc_flags);
	397	raw_spin_unlock_irqrestore(&gc->lock, flags);
	398	}
	399
	400	/* Mark the interrupt as installed */
	401	set_bit(idx, &gc->installed);
	402
	403	if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
	404	irq_set_lockdep_class(virq, &irq_nested_lock_class);
	405
	406	if (chip->irq_calc_mask)
	407	chip->irq_calc_mask(data);
	408	else
	409	data->mask = 1 << idx;
	410
c5863484	411	irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
088f40b7 TG	412	irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
	413	return 0;
	414	}
	415
ee26c013 SF	416	static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
	417	{
	418	struct irq_data *data = irq_domain_get_irq_data(d, virq);
	419	struct irq_domain_chip_generic *dgc = d->gc;
	420	unsigned int hw_irq = data->hwirq;
	421	struct irq_chip_generic *gc;
	422	int irq_idx;
	423
	424	gc = irq_get_domain_generic_chip(d, hw_irq);
	425	if (!gc)
	426	return;
	427
	428	irq_idx = hw_irq % dgc->irqs_per_chip;
	429
	430	clear_bit(irq_idx, &gc->installed);
	431	irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL,
	432	NULL);
	433
	434	}
	435
088f40b7 TG	436	struct irq_domain_ops irq_generic_chip_ops = {
088f40b7 TG	437	.map = irq_map_generic_chip,
ee26c013	438	.unmap = irq_unmap_generic_chip,
088f40b7 TG	439	.xlate = irq_domain_xlate_onetwocell,
	440	};
	441	EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
	442
7d828062 TG	443	/**
	444	* irq_setup_generic_chip - Setup a range of interrupts with a generic chip
	445	* @gc: Generic irq chip holding all data
	446	* @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
	447	* @flags: Flags for initialization
	448	* @clr: IRQ_* bits to clear
	449	* @set: IRQ_* bits to set
	450	*
	451	* Set up max. 32 interrupts starting from gc->irq_base. Note, this
	452	* initializes all interrupts to the primary irq_chip_type and its
	453	* associated handler.
	454	*/
	455	void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
	456	enum irq_gc_flags flags, unsigned int clr,
	457	unsigned int set)
	458	{
	459	struct irq_chip_type *ct = gc->chip_types;
d0051816	460	struct irq_chip *chip = &ct->chip;
7d828062 TG	461	unsigned int i;
7d828062 TG	462
cfefd21e TG	463	raw_spin_lock(&gc_lock);
	464	list_add_tail(&gc->list, &gc_list);
	465	raw_spin_unlock(&gc_lock);
	466
3528d82b	467	irq_gc_init_mask_cache(gc, flags);
899f0e66	468
7d828062	469	for (i = gc->irq_base; msk; msk >>= 1, i++) {
1dd75f91	470	if (!(msk & 0x01))
7d828062 TG	471	continue;
	472
	473	if (flags & IRQ_GC_INIT_NESTED_LOCK)
	474	irq_set_lockdep_class(i, &irq_nested_lock_class);
	475
966dc736 TG	476	if (!(flags & IRQ_GC_NO_MASK)) {
	477	struct irq_data *d = irq_get_irq_data(i);
	478
d0051816 TG	479	if (chip->irq_calc_mask)
	480	chip->irq_calc_mask(d);
	481	else
	482	d->mask = 1 << (i - gc->irq_base);
966dc736	483	}
d0051816	484	irq_set_chip_and_handler(i, chip, ct->handler);
7d828062 TG	485	irq_set_chip_data(i, gc);
	486	irq_modify_status(i, clr, set);
	487	}
	488	gc->irq_cnt = i - gc->irq_base;
	489	}
825de2e9	490	EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
7d828062 TG	491
	492	/**
	493	* irq_setup_alt_chip - Switch to alternative chip
	494	* @d: irq_data for this interrupt
ccc414f8	495	* @type: Flow type to be initialized
7d828062 TG	496	*
	497	* Only to be called from chip->irq_set_type() callbacks.
	498	*/
	499	int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
	500	{
	501	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	502	struct irq_chip_type *ct = gc->chip_types;
	503	unsigned int i;
	504
	505	for (i = 0; i < gc->num_ct; i++, ct++) {
	506	if (ct->type & type) {
	507	d->chip = &ct->chip;
	508	irq_data_to_desc(d)->handle_irq = ct->handler;
	509	return 0;
	510	}
	511	}
	512	return -EINVAL;
	513	}
825de2e9	514	EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
cfefd21e TG	515
	516	/**
	517	* irq_remove_generic_chip - Remove a chip
	518	* @gc: Generic irq chip holding all data
	519	* @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
	520	* @clr: IRQ_* bits to clear
	521	* @set: IRQ_* bits to set
	522	*
	523	* Remove up to 32 interrupts starting from gc->irq_base.
	524	*/
	525	void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
	526	unsigned int clr, unsigned int set)
	527	{
	528	unsigned int i = gc->irq_base;
	529
	530	raw_spin_lock(&gc_lock);
	531	list_del(&gc->list);
	532	raw_spin_unlock(&gc_lock);
	533
	534	for (; msk; msk >>= 1, i++) {
1dd75f91	535	if (!(msk & 0x01))
cfefd21e TG	536	continue;
	537
	538	/* Remove handler first. That will mask the irq line */
	539	irq_set_handler(i, NULL);
	540	irq_set_chip(i, &no_irq_chip);
	541	irq_set_chip_data(i, NULL);
	542	irq_modify_status(i, clr, set);
	543	}
	544	}
825de2e9	545	EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
cfefd21e	546
088f40b7 TG	547	static struct irq_data irq_gc_get_irq_data(struct irq_chip_generic gc)
	548	{
	549	unsigned int virq;
	550
	551	if (!gc->domain)
	552	return irq_get_irq_data(gc->irq_base);
	553
	554	/*
	555	* We don't know which of the irqs has been actually
	556	* installed. Use the first one.
	557	*/
	558	if (!gc->installed)
	559	return NULL;
	560
	561	virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
	562	return virq ? irq_get_irq_data(virq) : NULL;
	563	}
	564
cfefd21e TG	565	#ifdef CONFIG_PM
	566	static int irq_gc_suspend(void)
	567	{
	568	struct irq_chip_generic *gc;
	569
	570	list_for_each_entry(gc, &gc_list, list) {
	571	struct irq_chip_type *ct = gc->chip_types;
	572
088f40b7 TG	573	if (ct->chip.irq_suspend) {
	574	struct irq_data *data = irq_gc_get_irq_data(gc);
	575
	576	if (data)
	577	ct->chip.irq_suspend(data);
	578	}
be9b22b6 BN	579
	580	if (gc->suspend)
	581	gc->suspend(gc);
cfefd21e TG	582	}
	583	return 0;
	584	}
	585
	586	static void irq_gc_resume(void)
	587	{
	588	struct irq_chip_generic *gc;
	589
	590	list_for_each_entry(gc, &gc_list, list) {
	591	struct irq_chip_type *ct = gc->chip_types;
	592
be9b22b6 BN	593	if (gc->resume)
	594	gc->resume(gc);
	595
088f40b7 TG	596	if (ct->chip.irq_resume) {
	597	struct irq_data *data = irq_gc_get_irq_data(gc);
	598
	599	if (data)
	600	ct->chip.irq_resume(data);
	601	}
cfefd21e TG	602	}
	603	}
	604	#else
	605	#define irq_gc_suspend NULL
	606	#define irq_gc_resume NULL
	607	#endif
	608
	609	static void irq_gc_shutdown(void)
	610	{
	611	struct irq_chip_generic *gc;
	612
	613	list_for_each_entry(gc, &gc_list, list) {
	614	struct irq_chip_type *ct = gc->chip_types;
	615
088f40b7 TG	616	if (ct->chip.irq_pm_shutdown) {
	617	struct irq_data *data = irq_gc_get_irq_data(gc);
	618
	619	if (data)
	620	ct->chip.irq_pm_shutdown(data);
	621	}
cfefd21e TG	622	}
	623	}
	624
	625	static struct syscore_ops irq_gc_syscore_ops = {
	626	.suspend = irq_gc_suspend,
	627	.resume = irq_gc_resume,
	628	.shutdown = irq_gc_shutdown,
	629	};
	630
	631	static int __init irq_gc_init_ops(void)
	632	{
	633	register_syscore_ops(&irq_gc_syscore_ops);
	634	return 0;
	635	}
	636	device_initcall(irq_gc_init_ops);