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CommitLineData
3795de23
TG
1/*
2 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
3 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
4 *
5 * This file contains the interrupt descriptor management code
6 *
7 * Detailed information is available in Documentation/DocBook/genericirq
8 *
9 */
10#include <linux/irq.h>
11#include <linux/slab.h>
ec53cf23 12#include <linux/export.h>
3795de23
TG
13#include <linux/interrupt.h>
14#include <linux/kernel_stat.h>
15#include <linux/radix-tree.h>
1f5a5b87 16#include <linux/bitmap.h>
3795de23
TG
17
18#include "internals.h"
19
20/*
21 * lockdep: we want to handle all irq_desc locks as a single lock-class:
22 */
78f90d91 23static struct lock_class_key irq_desc_lock_class;
3795de23 24
fe051434 25#if defined(CONFIG_SMP)
3795de23
TG
26static void __init init_irq_default_affinity(void)
27{
28 alloc_cpumask_var(&irq_default_affinity, GFP_NOWAIT);
29 cpumask_setall(irq_default_affinity);
30}
31#else
32static void __init init_irq_default_affinity(void)
33{
34}
35#endif
36
1f5a5b87
TG
37#ifdef CONFIG_SMP
38static int alloc_masks(struct irq_desc *desc, gfp_t gfp, int node)
39{
40 if (!zalloc_cpumask_var_node(&desc->irq_data.affinity, gfp, node))
41 return -ENOMEM;
42
43#ifdef CONFIG_GENERIC_PENDING_IRQ
44 if (!zalloc_cpumask_var_node(&desc->pending_mask, gfp, node)) {
45 free_cpumask_var(desc->irq_data.affinity);
46 return -ENOMEM;
47 }
48#endif
49 return 0;
50}
51
52static void desc_smp_init(struct irq_desc *desc, int node)
53{
aa99ec0f 54 desc->irq_data.node = node;
1f5a5b87 55 cpumask_copy(desc->irq_data.affinity, irq_default_affinity);
b7b29338
TG
56#ifdef CONFIG_GENERIC_PENDING_IRQ
57 cpumask_clear(desc->pending_mask);
58#endif
59}
60
61static inline int desc_node(struct irq_desc *desc)
62{
63 return desc->irq_data.node;
1f5a5b87
TG
64}
65
66#else
67static inline int
68alloc_masks(struct irq_desc *desc, gfp_t gfp, int node) { return 0; }
69static inline void desc_smp_init(struct irq_desc *desc, int node) { }
b7b29338 70static inline int desc_node(struct irq_desc *desc) { return 0; }
1f5a5b87
TG
71#endif
72
b6873807
SAS
73static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node,
74 struct module *owner)
1f5a5b87 75{
6c9ae009
ED
76 int cpu;
77
1f5a5b87
TG
78 desc->irq_data.irq = irq;
79 desc->irq_data.chip = &no_irq_chip;
80 desc->irq_data.chip_data = NULL;
81 desc->irq_data.handler_data = NULL;
82 desc->irq_data.msi_desc = NULL;
f9e4989e 83 irq_settings_clr_and_set(desc, ~0, _IRQ_DEFAULT_INIT_FLAGS);
801a0e9a 84 irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
1f5a5b87
TG
85 desc->handle_irq = handle_bad_irq;
86 desc->depth = 1;
b7b29338
TG
87 desc->irq_count = 0;
88 desc->irqs_unhandled = 0;
1f5a5b87 89 desc->name = NULL;
b6873807 90 desc->owner = owner;
6c9ae009
ED
91 for_each_possible_cpu(cpu)
92 *per_cpu_ptr(desc->kstat_irqs, cpu) = 0;
1f5a5b87
TG
93 desc_smp_init(desc, node);
94}
95
3795de23
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96int nr_irqs = NR_IRQS;
97EXPORT_SYMBOL_GPL(nr_irqs);
98
a05a900a 99static DEFINE_MUTEX(sparse_irq_lock);
c1ee6264 100static DECLARE_BITMAP(allocated_irqs, IRQ_BITMAP_BITS);
1f5a5b87 101
3795de23
TG
102#ifdef CONFIG_SPARSE_IRQ
103
baa0d233 104static RADIX_TREE(irq_desc_tree, GFP_KERNEL);
3795de23 105
1f5a5b87 106static void irq_insert_desc(unsigned int irq, struct irq_desc *desc)
3795de23
TG
107{
108 radix_tree_insert(&irq_desc_tree, irq, desc);
109}
110
111struct irq_desc *irq_to_desc(unsigned int irq)
112{
113 return radix_tree_lookup(&irq_desc_tree, irq);
114}
3911ff30 115EXPORT_SYMBOL(irq_to_desc);
3795de23 116
1f5a5b87
TG
117static void delete_irq_desc(unsigned int irq)
118{
119 radix_tree_delete(&irq_desc_tree, irq);
120}
121
122#ifdef CONFIG_SMP
123static void free_masks(struct irq_desc *desc)
124{
125#ifdef CONFIG_GENERIC_PENDING_IRQ
126 free_cpumask_var(desc->pending_mask);
127#endif
c0a19ebc 128 free_cpumask_var(desc->irq_data.affinity);
1f5a5b87
TG
129}
130#else
131static inline void free_masks(struct irq_desc *desc) { }
132#endif
133
b6873807 134static struct irq_desc *alloc_desc(int irq, int node, struct module *owner)
1f5a5b87
TG
135{
136 struct irq_desc *desc;
baa0d233 137 gfp_t gfp = GFP_KERNEL;
1f5a5b87
TG
138
139 desc = kzalloc_node(sizeof(*desc), gfp, node);
140 if (!desc)
141 return NULL;
142 /* allocate based on nr_cpu_ids */
6c9ae009 143 desc->kstat_irqs = alloc_percpu(unsigned int);
1f5a5b87
TG
144 if (!desc->kstat_irqs)
145 goto err_desc;
146
147 if (alloc_masks(desc, gfp, node))
148 goto err_kstat;
149
150 raw_spin_lock_init(&desc->lock);
151 lockdep_set_class(&desc->lock, &irq_desc_lock_class);
152
b6873807 153 desc_set_defaults(irq, desc, node, owner);
1f5a5b87
TG
154
155 return desc;
156
157err_kstat:
6c9ae009 158 free_percpu(desc->kstat_irqs);
1f5a5b87
TG
159err_desc:
160 kfree(desc);
161 return NULL;
162}
163
164static void free_desc(unsigned int irq)
165{
166 struct irq_desc *desc = irq_to_desc(irq);
1f5a5b87 167
13bfe99e
TG
168 unregister_irq_proc(irq, desc);
169
a05a900a 170 mutex_lock(&sparse_irq_lock);
1f5a5b87 171 delete_irq_desc(irq);
a05a900a 172 mutex_unlock(&sparse_irq_lock);
1f5a5b87
TG
173
174 free_masks(desc);
6c9ae009 175 free_percpu(desc->kstat_irqs);
1f5a5b87
TG
176 kfree(desc);
177}
178
b6873807
SAS
179static int alloc_descs(unsigned int start, unsigned int cnt, int node,
180 struct module *owner)
1f5a5b87
TG
181{
182 struct irq_desc *desc;
1f5a5b87
TG
183 int i;
184
185 for (i = 0; i < cnt; i++) {
b6873807 186 desc = alloc_desc(start + i, node, owner);
1f5a5b87
TG
187 if (!desc)
188 goto err;
a05a900a 189 mutex_lock(&sparse_irq_lock);
1f5a5b87 190 irq_insert_desc(start + i, desc);
a05a900a 191 mutex_unlock(&sparse_irq_lock);
1f5a5b87
TG
192 }
193 return start;
194
195err:
196 for (i--; i >= 0; i--)
197 free_desc(start + i);
198
a05a900a 199 mutex_lock(&sparse_irq_lock);
1f5a5b87 200 bitmap_clear(allocated_irqs, start, cnt);
a05a900a 201 mutex_unlock(&sparse_irq_lock);
1f5a5b87
TG
202 return -ENOMEM;
203}
204
ed4dea6e 205static int irq_expand_nr_irqs(unsigned int nr)
e7bcecb7 206{
ed4dea6e 207 if (nr > IRQ_BITMAP_BITS)
e7bcecb7 208 return -ENOMEM;
ed4dea6e 209 nr_irqs = nr;
e7bcecb7
TG
210 return 0;
211}
212
3795de23
TG
213int __init early_irq_init(void)
214{
b683de2b 215 int i, initcnt, node = first_online_node;
3795de23 216 struct irq_desc *desc;
3795de23
TG
217
218 init_irq_default_affinity();
219
b683de2b
TG
220 /* Let arch update nr_irqs and return the nr of preallocated irqs */
221 initcnt = arch_probe_nr_irqs();
222 printk(KERN_INFO "NR_IRQS:%d nr_irqs:%d %d\n", NR_IRQS, nr_irqs, initcnt);
3795de23 223
c1ee6264
TG
224 if (WARN_ON(nr_irqs > IRQ_BITMAP_BITS))
225 nr_irqs = IRQ_BITMAP_BITS;
226
227 if (WARN_ON(initcnt > IRQ_BITMAP_BITS))
228 initcnt = IRQ_BITMAP_BITS;
229
230 if (initcnt > nr_irqs)
231 nr_irqs = initcnt;
232
b683de2b 233 for (i = 0; i < initcnt; i++) {
b6873807 234 desc = alloc_desc(i, node, NULL);
aa99ec0f
TG
235 set_bit(i, allocated_irqs);
236 irq_insert_desc(i, desc);
3795de23 237 }
3795de23
TG
238 return arch_early_irq_init();
239}
240
3795de23
TG
241#else /* !CONFIG_SPARSE_IRQ */
242
243struct irq_desc irq_desc[NR_IRQS] __cacheline_aligned_in_smp = {
244 [0 ... NR_IRQS-1] = {
3795de23
TG
245 .handle_irq = handle_bad_irq,
246 .depth = 1,
247 .lock = __RAW_SPIN_LOCK_UNLOCKED(irq_desc->lock),
248 }
249};
250
3795de23
TG
251int __init early_irq_init(void)
252{
aa99ec0f 253 int count, i, node = first_online_node;
3795de23 254 struct irq_desc *desc;
3795de23
TG
255
256 init_irq_default_affinity();
257
258 printk(KERN_INFO "NR_IRQS:%d\n", NR_IRQS);
259
260 desc = irq_desc;
261 count = ARRAY_SIZE(irq_desc);
262
263 for (i = 0; i < count; i++) {
6c9ae009 264 desc[i].kstat_irqs = alloc_percpu(unsigned int);
e7fbad30
LW
265 alloc_masks(&desc[i], GFP_KERNEL, node);
266 raw_spin_lock_init(&desc[i].lock);
154cd387 267 lockdep_set_class(&desc[i].lock, &irq_desc_lock_class);
b6873807 268 desc_set_defaults(i, &desc[i], node, NULL);
3795de23
TG
269 }
270 return arch_early_irq_init();
271}
272
273struct irq_desc *irq_to_desc(unsigned int irq)
274{
275 return (irq < NR_IRQS) ? irq_desc + irq : NULL;
276}
2c45aada 277EXPORT_SYMBOL(irq_to_desc);
3795de23 278
1f5a5b87
TG
279static void free_desc(unsigned int irq)
280{
b7b29338 281 dynamic_irq_cleanup(irq);
1f5a5b87
TG
282}
283
b6873807
SAS
284static inline int alloc_descs(unsigned int start, unsigned int cnt, int node,
285 struct module *owner)
1f5a5b87 286{
b6873807
SAS
287 u32 i;
288
289 for (i = 0; i < cnt; i++) {
290 struct irq_desc *desc = irq_to_desc(start + i);
291
292 desc->owner = owner;
293 }
1f5a5b87
TG
294 return start;
295}
e7bcecb7 296
ed4dea6e 297static int irq_expand_nr_irqs(unsigned int nr)
e7bcecb7
TG
298{
299 return -ENOMEM;
300}
301
f63b6a05
TG
302void irq_mark_irq(unsigned int irq)
303{
304 mutex_lock(&sparse_irq_lock);
305 bitmap_set(allocated_irqs, irq, 1);
306 mutex_unlock(&sparse_irq_lock);
307}
308
3795de23
TG
309#endif /* !CONFIG_SPARSE_IRQ */
310
fe12bc2c
TG
311/**
312 * generic_handle_irq - Invoke the handler for a particular irq
313 * @irq: The irq number to handle
314 *
315 */
316int generic_handle_irq(unsigned int irq)
317{
318 struct irq_desc *desc = irq_to_desc(irq);
319
320 if (!desc)
321 return -EINVAL;
322 generic_handle_irq_desc(irq, desc);
323 return 0;
324}
edf76f83 325EXPORT_SYMBOL_GPL(generic_handle_irq);
fe12bc2c 326
1f5a5b87
TG
327/* Dynamic interrupt handling */
328
329/**
330 * irq_free_descs - free irq descriptors
331 * @from: Start of descriptor range
332 * @cnt: Number of consecutive irqs to free
333 */
334void irq_free_descs(unsigned int from, unsigned int cnt)
335{
1f5a5b87
TG
336 int i;
337
338 if (from >= nr_irqs || (from + cnt) > nr_irqs)
339 return;
340
341 for (i = 0; i < cnt; i++)
342 free_desc(from + i);
343
a05a900a 344 mutex_lock(&sparse_irq_lock);
1f5a5b87 345 bitmap_clear(allocated_irqs, from, cnt);
a05a900a 346 mutex_unlock(&sparse_irq_lock);
1f5a5b87 347}
edf76f83 348EXPORT_SYMBOL_GPL(irq_free_descs);
1f5a5b87
TG
349
350/**
351 * irq_alloc_descs - allocate and initialize a range of irq descriptors
352 * @irq: Allocate for specific irq number if irq >= 0
353 * @from: Start the search from this irq number
354 * @cnt: Number of consecutive irqs to allocate.
355 * @node: Preferred node on which the irq descriptor should be allocated
d522a0d1 356 * @owner: Owning module (can be NULL)
1f5a5b87
TG
357 *
358 * Returns the first irq number or error code
359 */
360int __ref
b6873807
SAS
361__irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
362 struct module *owner)
1f5a5b87 363{
1f5a5b87
TG
364 int start, ret;
365
366 if (!cnt)
367 return -EINVAL;
368
c5182b88
MB
369 if (irq >= 0) {
370 if (from > irq)
371 return -EINVAL;
372 from = irq;
62a08ae2
TG
373 } else {
374 /*
375 * For interrupts which are freely allocated the
376 * architecture can force a lower bound to the @from
377 * argument. x86 uses this to exclude the GSI space.
378 */
379 from = arch_dynirq_lower_bound(from);
c5182b88
MB
380 }
381
a05a900a 382 mutex_lock(&sparse_irq_lock);
1f5a5b87 383
ed4dea6e
YL
384 start = bitmap_find_next_zero_area(allocated_irqs, IRQ_BITMAP_BITS,
385 from, cnt, 0);
1f5a5b87
TG
386 ret = -EEXIST;
387 if (irq >=0 && start != irq)
388 goto err;
389
ed4dea6e
YL
390 if (start + cnt > nr_irqs) {
391 ret = irq_expand_nr_irqs(start + cnt);
e7bcecb7
TG
392 if (ret)
393 goto err;
394 }
1f5a5b87
TG
395
396 bitmap_set(allocated_irqs, start, cnt);
a05a900a 397 mutex_unlock(&sparse_irq_lock);
b6873807 398 return alloc_descs(start, cnt, node, owner);
1f5a5b87
TG
399
400err:
a05a900a 401 mutex_unlock(&sparse_irq_lock);
1f5a5b87
TG
402 return ret;
403}
b6873807 404EXPORT_SYMBOL_GPL(__irq_alloc_descs);
1f5a5b87 405
7b6ef126
TG
406#ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
407/**
408 * irq_alloc_hwirqs - Allocate an irq descriptor and initialize the hardware
409 * @cnt: number of interrupts to allocate
410 * @node: node on which to allocate
411 *
412 * Returns an interrupt number > 0 or 0, if the allocation fails.
413 */
414unsigned int irq_alloc_hwirqs(int cnt, int node)
415{
416 int i, irq = __irq_alloc_descs(-1, 0, cnt, node, NULL);
417
418 if (irq < 0)
419 return 0;
420
421 for (i = irq; cnt > 0; i++, cnt--) {
422 if (arch_setup_hwirq(i, node))
423 goto err;
424 irq_clear_status_flags(i, _IRQ_NOREQUEST);
425 }
426 return irq;
427
428err:
429 for (i--; i >= irq; i--) {
430 irq_set_status_flags(i, _IRQ_NOREQUEST | _IRQ_NOPROBE);
431 arch_teardown_hwirq(i);
432 }
433 irq_free_descs(irq, cnt);
434 return 0;
435}
436EXPORT_SYMBOL_GPL(irq_alloc_hwirqs);
437
438/**
439 * irq_free_hwirqs - Free irq descriptor and cleanup the hardware
440 * @from: Free from irq number
441 * @cnt: number of interrupts to free
442 *
443 */
444void irq_free_hwirqs(unsigned int from, int cnt)
445{
446 int i;
447
448 for (i = from; cnt > 0; i++, cnt--) {
449 irq_set_status_flags(i, _IRQ_NOREQUEST | _IRQ_NOPROBE);
450 arch_teardown_hwirq(i);
451 }
452 irq_free_descs(from, cnt);
453}
454EXPORT_SYMBOL_GPL(irq_free_hwirqs);
455#endif
456
a98d24b7
TG
457/**
458 * irq_get_next_irq - get next allocated irq number
459 * @offset: where to start the search
460 *
461 * Returns next irq number after offset or nr_irqs if none is found.
462 */
463unsigned int irq_get_next_irq(unsigned int offset)
464{
465 return find_next_bit(allocated_irqs, nr_irqs, offset);
466}
467
d5eb4ad2 468struct irq_desc *
31d9d9b6
MZ
469__irq_get_desc_lock(unsigned int irq, unsigned long *flags, bool bus,
470 unsigned int check)
d5eb4ad2
TG
471{
472 struct irq_desc *desc = irq_to_desc(irq);
473
474 if (desc) {
31d9d9b6
MZ
475 if (check & _IRQ_DESC_CHECK) {
476 if ((check & _IRQ_DESC_PERCPU) &&
477 !irq_settings_is_per_cpu_devid(desc))
478 return NULL;
479
480 if (!(check & _IRQ_DESC_PERCPU) &&
481 irq_settings_is_per_cpu_devid(desc))
482 return NULL;
483 }
484
d5eb4ad2
TG
485 if (bus)
486 chip_bus_lock(desc);
487 raw_spin_lock_irqsave(&desc->lock, *flags);
488 }
489 return desc;
490}
491
492void __irq_put_desc_unlock(struct irq_desc *desc, unsigned long flags, bool bus)
493{
494 raw_spin_unlock_irqrestore(&desc->lock, flags);
495 if (bus)
496 chip_bus_sync_unlock(desc);
497}
498
31d9d9b6
MZ
499int irq_set_percpu_devid(unsigned int irq)
500{
501 struct irq_desc *desc = irq_to_desc(irq);
502
503 if (!desc)
504 return -EINVAL;
505
506 if (desc->percpu_enabled)
507 return -EINVAL;
508
509 desc->percpu_enabled = kzalloc(sizeof(*desc->percpu_enabled), GFP_KERNEL);
510
511 if (!desc->percpu_enabled)
512 return -ENOMEM;
513
514 irq_set_percpu_devid_flags(irq);
515 return 0;
516}
517
b7b29338
TG
518/**
519 * dynamic_irq_cleanup - cleanup a dynamically allocated irq
520 * @irq: irq number to initialize
521 */
522void dynamic_irq_cleanup(unsigned int irq)
3795de23 523{
b7b29338
TG
524 struct irq_desc *desc = irq_to_desc(irq);
525 unsigned long flags;
526
527 raw_spin_lock_irqsave(&desc->lock, flags);
b6873807 528 desc_set_defaults(irq, desc, desc_node(desc), NULL);
b7b29338 529 raw_spin_unlock_irqrestore(&desc->lock, flags);
3795de23
TG
530}
531
792d0018
TG
532void kstat_incr_irq_this_cpu(unsigned int irq)
533{
534 kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
535}
536
3795de23
TG
537unsigned int kstat_irqs_cpu(unsigned int irq, int cpu)
538{
539 struct irq_desc *desc = irq_to_desc(irq);
6c9ae009
ED
540
541 return desc && desc->kstat_irqs ?
542 *per_cpu_ptr(desc->kstat_irqs, cpu) : 0;
3795de23 543}
478735e3 544
478735e3
KH
545unsigned int kstat_irqs(unsigned int irq)
546{
547 struct irq_desc *desc = irq_to_desc(irq);
548 int cpu;
549 int sum = 0;
550
6c9ae009 551 if (!desc || !desc->kstat_irqs)
478735e3
KH
552 return 0;
553 for_each_possible_cpu(cpu)
6c9ae009 554 sum += *per_cpu_ptr(desc->kstat_irqs, cpu);
478735e3
KH
555 return sum;
556}