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CommitLineData
3795de23
TG
1/*
2 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
3 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
4 *
5 * This file contains the interrupt descriptor management code
6 *
7 * Detailed information is available in Documentation/DocBook/genericirq
8 *
9 */
10#include <linux/irq.h>
11#include <linux/slab.h>
12#include <linux/module.h>
13#include <linux/interrupt.h>
14#include <linux/kernel_stat.h>
15#include <linux/radix-tree.h>
1f5a5b87 16#include <linux/bitmap.h>
3795de23
TG
17
18#include "internals.h"
19
20/*
21 * lockdep: we want to handle all irq_desc locks as a single lock-class:
22 */
78f90d91 23static struct lock_class_key irq_desc_lock_class;
3795de23 24
fe051434 25#if defined(CONFIG_SMP)
3795de23
TG
26static void __init init_irq_default_affinity(void)
27{
28 alloc_cpumask_var(&irq_default_affinity, GFP_NOWAIT);
29 cpumask_setall(irq_default_affinity);
30}
31#else
32static void __init init_irq_default_affinity(void)
33{
34}
35#endif
36
1f5a5b87
TG
37#ifdef CONFIG_SMP
38static int alloc_masks(struct irq_desc *desc, gfp_t gfp, int node)
39{
40 if (!zalloc_cpumask_var_node(&desc->irq_data.affinity, gfp, node))
41 return -ENOMEM;
42
43#ifdef CONFIG_GENERIC_PENDING_IRQ
44 if (!zalloc_cpumask_var_node(&desc->pending_mask, gfp, node)) {
45 free_cpumask_var(desc->irq_data.affinity);
46 return -ENOMEM;
47 }
48#endif
49 return 0;
50}
51
52static void desc_smp_init(struct irq_desc *desc, int node)
53{
aa99ec0f 54 desc->irq_data.node = node;
1f5a5b87 55 cpumask_copy(desc->irq_data.affinity, irq_default_affinity);
b7b29338
TG
56#ifdef CONFIG_GENERIC_PENDING_IRQ
57 cpumask_clear(desc->pending_mask);
58#endif
59}
60
61static inline int desc_node(struct irq_desc *desc)
62{
63 return desc->irq_data.node;
1f5a5b87
TG
64}
65
66#else
67static inline int
68alloc_masks(struct irq_desc *desc, gfp_t gfp, int node) { return 0; }
69static inline void desc_smp_init(struct irq_desc *desc, int node) { }
b7b29338 70static inline int desc_node(struct irq_desc *desc) { return 0; }
1f5a5b87
TG
71#endif
72
b6873807
SAS
73static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node,
74 struct module *owner)
1f5a5b87 75{
6c9ae009
ED
76 int cpu;
77
1f5a5b87
TG
78 desc->irq_data.irq = irq;
79 desc->irq_data.chip = &no_irq_chip;
80 desc->irq_data.chip_data = NULL;
81 desc->irq_data.handler_data = NULL;
82 desc->irq_data.msi_desc = NULL;
f9e4989e 83 irq_settings_clr_and_set(desc, ~0, _IRQ_DEFAULT_INIT_FLAGS);
801a0e9a 84 irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
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TG
85 desc->handle_irq = handle_bad_irq;
86 desc->depth = 1;
b7b29338
TG
87 desc->irq_count = 0;
88 desc->irqs_unhandled = 0;
1f5a5b87 89 desc->name = NULL;
b6873807 90 desc->owner = owner;
6c9ae009
ED
91 for_each_possible_cpu(cpu)
92 *per_cpu_ptr(desc->kstat_irqs, cpu) = 0;
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TG
93 desc_smp_init(desc, node);
94}
95
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96int nr_irqs = NR_IRQS;
97EXPORT_SYMBOL_GPL(nr_irqs);
98
a05a900a 99static DEFINE_MUTEX(sparse_irq_lock);
c1ee6264 100static DECLARE_BITMAP(allocated_irqs, IRQ_BITMAP_BITS);
1f5a5b87 101
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TG
102#ifdef CONFIG_SPARSE_IRQ
103
baa0d233 104static RADIX_TREE(irq_desc_tree, GFP_KERNEL);
3795de23 105
1f5a5b87 106static void irq_insert_desc(unsigned int irq, struct irq_desc *desc)
3795de23
TG
107{
108 radix_tree_insert(&irq_desc_tree, irq, desc);
109}
110
111struct irq_desc *irq_to_desc(unsigned int irq)
112{
113 return radix_tree_lookup(&irq_desc_tree, irq);
114}
115
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116static void delete_irq_desc(unsigned int irq)
117{
118 radix_tree_delete(&irq_desc_tree, irq);
119}
120
121#ifdef CONFIG_SMP
122static void free_masks(struct irq_desc *desc)
123{
124#ifdef CONFIG_GENERIC_PENDING_IRQ
125 free_cpumask_var(desc->pending_mask);
126#endif
c0a19ebc 127 free_cpumask_var(desc->irq_data.affinity);
1f5a5b87
TG
128}
129#else
130static inline void free_masks(struct irq_desc *desc) { }
131#endif
132
b6873807 133static struct irq_desc *alloc_desc(int irq, int node, struct module *owner)
1f5a5b87
TG
134{
135 struct irq_desc *desc;
baa0d233 136 gfp_t gfp = GFP_KERNEL;
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137
138 desc = kzalloc_node(sizeof(*desc), gfp, node);
139 if (!desc)
140 return NULL;
141 /* allocate based on nr_cpu_ids */
6c9ae009 142 desc->kstat_irqs = alloc_percpu(unsigned int);
1f5a5b87
TG
143 if (!desc->kstat_irqs)
144 goto err_desc;
145
146 if (alloc_masks(desc, gfp, node))
147 goto err_kstat;
148
149 raw_spin_lock_init(&desc->lock);
150 lockdep_set_class(&desc->lock, &irq_desc_lock_class);
151
b6873807 152 desc_set_defaults(irq, desc, node, owner);
1f5a5b87
TG
153
154 return desc;
155
156err_kstat:
6c9ae009 157 free_percpu(desc->kstat_irqs);
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TG
158err_desc:
159 kfree(desc);
160 return NULL;
161}
162
163static void free_desc(unsigned int irq)
164{
165 struct irq_desc *desc = irq_to_desc(irq);
1f5a5b87 166
13bfe99e
TG
167 unregister_irq_proc(irq, desc);
168
a05a900a 169 mutex_lock(&sparse_irq_lock);
1f5a5b87 170 delete_irq_desc(irq);
a05a900a 171 mutex_unlock(&sparse_irq_lock);
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TG
172
173 free_masks(desc);
6c9ae009 174 free_percpu(desc->kstat_irqs);
1f5a5b87
TG
175 kfree(desc);
176}
177
b6873807
SAS
178static int alloc_descs(unsigned int start, unsigned int cnt, int node,
179 struct module *owner)
1f5a5b87
TG
180{
181 struct irq_desc *desc;
1f5a5b87
TG
182 int i;
183
184 for (i = 0; i < cnt; i++) {
b6873807 185 desc = alloc_desc(start + i, node, owner);
1f5a5b87
TG
186 if (!desc)
187 goto err;
a05a900a 188 mutex_lock(&sparse_irq_lock);
1f5a5b87 189 irq_insert_desc(start + i, desc);
a05a900a 190 mutex_unlock(&sparse_irq_lock);
1f5a5b87
TG
191 }
192 return start;
193
194err:
195 for (i--; i >= 0; i--)
196 free_desc(start + i);
197
a05a900a 198 mutex_lock(&sparse_irq_lock);
1f5a5b87 199 bitmap_clear(allocated_irqs, start, cnt);
a05a900a 200 mutex_unlock(&sparse_irq_lock);
1f5a5b87
TG
201 return -ENOMEM;
202}
203
ed4dea6e 204static int irq_expand_nr_irqs(unsigned int nr)
e7bcecb7 205{
ed4dea6e 206 if (nr > IRQ_BITMAP_BITS)
e7bcecb7 207 return -ENOMEM;
ed4dea6e 208 nr_irqs = nr;
e7bcecb7
TG
209 return 0;
210}
211
3795de23
TG
212int __init early_irq_init(void)
213{
b683de2b 214 int i, initcnt, node = first_online_node;
3795de23 215 struct irq_desc *desc;
3795de23
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216
217 init_irq_default_affinity();
218
b683de2b
TG
219 /* Let arch update nr_irqs and return the nr of preallocated irqs */
220 initcnt = arch_probe_nr_irqs();
221 printk(KERN_INFO "NR_IRQS:%d nr_irqs:%d %d\n", NR_IRQS, nr_irqs, initcnt);
3795de23 222
c1ee6264
TG
223 if (WARN_ON(nr_irqs > IRQ_BITMAP_BITS))
224 nr_irqs = IRQ_BITMAP_BITS;
225
226 if (WARN_ON(initcnt > IRQ_BITMAP_BITS))
227 initcnt = IRQ_BITMAP_BITS;
228
229 if (initcnt > nr_irqs)
230 nr_irqs = initcnt;
231
b683de2b 232 for (i = 0; i < initcnt; i++) {
b6873807 233 desc = alloc_desc(i, node, NULL);
aa99ec0f
TG
234 set_bit(i, allocated_irqs);
235 irq_insert_desc(i, desc);
3795de23 236 }
3795de23
TG
237 return arch_early_irq_init();
238}
239
3795de23
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240#else /* !CONFIG_SPARSE_IRQ */
241
242struct irq_desc irq_desc[NR_IRQS] __cacheline_aligned_in_smp = {
243 [0 ... NR_IRQS-1] = {
3795de23
TG
244 .handle_irq = handle_bad_irq,
245 .depth = 1,
246 .lock = __RAW_SPIN_LOCK_UNLOCKED(irq_desc->lock),
247 }
248};
249
3795de23
TG
250int __init early_irq_init(void)
251{
aa99ec0f 252 int count, i, node = first_online_node;
3795de23 253 struct irq_desc *desc;
3795de23
TG
254
255 init_irq_default_affinity();
256
257 printk(KERN_INFO "NR_IRQS:%d\n", NR_IRQS);
258
259 desc = irq_desc;
260 count = ARRAY_SIZE(irq_desc);
261
262 for (i = 0; i < count; i++) {
6c9ae009 263 desc[i].kstat_irqs = alloc_percpu(unsigned int);
e7fbad30
LW
264 alloc_masks(&desc[i], GFP_KERNEL, node);
265 raw_spin_lock_init(&desc[i].lock);
154cd387 266 lockdep_set_class(&desc[i].lock, &irq_desc_lock_class);
b6873807 267 desc_set_defaults(i, &desc[i], node, NULL);
3795de23
TG
268 }
269 return arch_early_irq_init();
270}
271
272struct irq_desc *irq_to_desc(unsigned int irq)
273{
274 return (irq < NR_IRQS) ? irq_desc + irq : NULL;
275}
276
1f5a5b87
TG
277static void free_desc(unsigned int irq)
278{
b7b29338 279 dynamic_irq_cleanup(irq);
1f5a5b87
TG
280}
281
b6873807
SAS
282static inline int alloc_descs(unsigned int start, unsigned int cnt, int node,
283 struct module *owner)
1f5a5b87 284{
b6873807
SAS
285 u32 i;
286
287 for (i = 0; i < cnt; i++) {
288 struct irq_desc *desc = irq_to_desc(start + i);
289
290 desc->owner = owner;
291 }
1f5a5b87
TG
292 return start;
293}
e7bcecb7 294
ed4dea6e 295static int irq_expand_nr_irqs(unsigned int nr)
e7bcecb7
TG
296{
297 return -ENOMEM;
298}
299
3795de23
TG
300#endif /* !CONFIG_SPARSE_IRQ */
301
fe12bc2c
TG
302/**
303 * generic_handle_irq - Invoke the handler for a particular irq
304 * @irq: The irq number to handle
305 *
306 */
307int generic_handle_irq(unsigned int irq)
308{
309 struct irq_desc *desc = irq_to_desc(irq);
310
311 if (!desc)
312 return -EINVAL;
313 generic_handle_irq_desc(irq, desc);
314 return 0;
315}
edf76f83 316EXPORT_SYMBOL_GPL(generic_handle_irq);
fe12bc2c 317
1f5a5b87
TG
318/* Dynamic interrupt handling */
319
320/**
321 * irq_free_descs - free irq descriptors
322 * @from: Start of descriptor range
323 * @cnt: Number of consecutive irqs to free
324 */
325void irq_free_descs(unsigned int from, unsigned int cnt)
326{
1f5a5b87
TG
327 int i;
328
329 if (from >= nr_irqs || (from + cnt) > nr_irqs)
330 return;
331
332 for (i = 0; i < cnt; i++)
333 free_desc(from + i);
334
a05a900a 335 mutex_lock(&sparse_irq_lock);
1f5a5b87 336 bitmap_clear(allocated_irqs, from, cnt);
a05a900a 337 mutex_unlock(&sparse_irq_lock);
1f5a5b87 338}
edf76f83 339EXPORT_SYMBOL_GPL(irq_free_descs);
1f5a5b87
TG
340
341/**
342 * irq_alloc_descs - allocate and initialize a range of irq descriptors
343 * @irq: Allocate for specific irq number if irq >= 0
344 * @from: Start the search from this irq number
345 * @cnt: Number of consecutive irqs to allocate.
346 * @node: Preferred node on which the irq descriptor should be allocated
347 *
348 * Returns the first irq number or error code
349 */
350int __ref
b6873807
SAS
351__irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
352 struct module *owner)
1f5a5b87 353{
1f5a5b87
TG
354 int start, ret;
355
356 if (!cnt)
357 return -EINVAL;
358
c5182b88
MB
359 if (irq >= 0) {
360 if (from > irq)
361 return -EINVAL;
362 from = irq;
363 }
364
a05a900a 365 mutex_lock(&sparse_irq_lock);
1f5a5b87 366
ed4dea6e
YL
367 start = bitmap_find_next_zero_area(allocated_irqs, IRQ_BITMAP_BITS,
368 from, cnt, 0);
1f5a5b87
TG
369 ret = -EEXIST;
370 if (irq >=0 && start != irq)
371 goto err;
372
ed4dea6e
YL
373 if (start + cnt > nr_irqs) {
374 ret = irq_expand_nr_irqs(start + cnt);
e7bcecb7
TG
375 if (ret)
376 goto err;
377 }
1f5a5b87
TG
378
379 bitmap_set(allocated_irqs, start, cnt);
a05a900a 380 mutex_unlock(&sparse_irq_lock);
b6873807 381 return alloc_descs(start, cnt, node, owner);
1f5a5b87
TG
382
383err:
a05a900a 384 mutex_unlock(&sparse_irq_lock);
1f5a5b87
TG
385 return ret;
386}
b6873807 387EXPORT_SYMBOL_GPL(__irq_alloc_descs);
1f5a5b87 388
06f6c339
TG
389/**
390 * irq_reserve_irqs - mark irqs allocated
391 * @from: mark from irq number
392 * @cnt: number of irqs to mark
393 *
394 * Returns 0 on success or an appropriate error code
395 */
396int irq_reserve_irqs(unsigned int from, unsigned int cnt)
397{
06f6c339
TG
398 unsigned int start;
399 int ret = 0;
400
401 if (!cnt || (from + cnt) > nr_irqs)
402 return -EINVAL;
403
a05a900a 404 mutex_lock(&sparse_irq_lock);
06f6c339
TG
405 start = bitmap_find_next_zero_area(allocated_irqs, nr_irqs, from, cnt, 0);
406 if (start == from)
407 bitmap_set(allocated_irqs, start, cnt);
408 else
409 ret = -EEXIST;
a05a900a 410 mutex_unlock(&sparse_irq_lock);
06f6c339
TG
411 return ret;
412}
413
a98d24b7
TG
414/**
415 * irq_get_next_irq - get next allocated irq number
416 * @offset: where to start the search
417 *
418 * Returns next irq number after offset or nr_irqs if none is found.
419 */
420unsigned int irq_get_next_irq(unsigned int offset)
421{
422 return find_next_bit(allocated_irqs, nr_irqs, offset);
423}
424
d5eb4ad2
TG
425struct irq_desc *
426__irq_get_desc_lock(unsigned int irq, unsigned long *flags, bool bus)
427{
428 struct irq_desc *desc = irq_to_desc(irq);
429
430 if (desc) {
431 if (bus)
432 chip_bus_lock(desc);
433 raw_spin_lock_irqsave(&desc->lock, *flags);
434 }
435 return desc;
436}
437
438void __irq_put_desc_unlock(struct irq_desc *desc, unsigned long flags, bool bus)
439{
440 raw_spin_unlock_irqrestore(&desc->lock, flags);
441 if (bus)
442 chip_bus_sync_unlock(desc);
443}
444
b7b29338
TG
445/**
446 * dynamic_irq_cleanup - cleanup a dynamically allocated irq
447 * @irq: irq number to initialize
448 */
449void dynamic_irq_cleanup(unsigned int irq)
3795de23 450{
b7b29338
TG
451 struct irq_desc *desc = irq_to_desc(irq);
452 unsigned long flags;
453
454 raw_spin_lock_irqsave(&desc->lock, flags);
b6873807 455 desc_set_defaults(irq, desc, desc_node(desc), NULL);
b7b29338 456 raw_spin_unlock_irqrestore(&desc->lock, flags);
3795de23
TG
457}
458
3795de23
TG
459unsigned int kstat_irqs_cpu(unsigned int irq, int cpu)
460{
461 struct irq_desc *desc = irq_to_desc(irq);
6c9ae009
ED
462
463 return desc && desc->kstat_irqs ?
464 *per_cpu_ptr(desc->kstat_irqs, cpu) : 0;
3795de23 465}
478735e3 466
478735e3
KH
467unsigned int kstat_irqs(unsigned int irq)
468{
469 struct irq_desc *desc = irq_to_desc(irq);
470 int cpu;
471 int sum = 0;
472
6c9ae009 473 if (!desc || !desc->kstat_irqs)
478735e3
KH
474 return 0;
475 for_each_possible_cpu(cpu)
6c9ae009 476 sum += *per_cpu_ptr(desc->kstat_irqs, cpu);
478735e3
KH
477 return sum;
478}