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52a65ff5 1// SPDX-License-Identifier: GPL-2.0
3795de23
TG
2/*
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
5 *
99bfce5d
TG
6 * This file contains the interrupt descriptor management code. Detailed
7 * information is available in Documentation/core-api/genericirq.rst
3795de23
TG
8 *
9 */
10#include <linux/irq.h>
11#include <linux/slab.h>
ec53cf23 12#include <linux/export.h>
3795de23
TG
13#include <linux/interrupt.h>
14#include <linux/kernel_stat.h>
15#include <linux/radix-tree.h>
1f5a5b87 16#include <linux/bitmap.h>
76ba59f8 17#include <linux/irqdomain.h>
ecb3f394 18#include <linux/sysfs.h>
3795de23
TG
19
20#include "internals.h"
21
22/*
23 * lockdep: we want to handle all irq_desc locks as a single lock-class:
24 */
78f90d91 25static struct lock_class_key irq_desc_lock_class;
3795de23 26
fe051434 27#if defined(CONFIG_SMP)
fbf19803
TG
28static int __init irq_affinity_setup(char *str)
29{
10d94ff4 30 alloc_bootmem_cpumask_var(&irq_default_affinity);
fbf19803
TG
31 cpulist_parse(str, irq_default_affinity);
32 /*
33 * Set at least the boot cpu. We don't want to end up with
34 * bugreports caused by random comandline masks
35 */
36 cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
37 return 1;
38}
39__setup("irqaffinity=", irq_affinity_setup);
40
3795de23
TG
41static void __init init_irq_default_affinity(void)
42{
10d94ff4 43 if (!cpumask_available(irq_default_affinity))
fbf19803 44 zalloc_cpumask_var(&irq_default_affinity, GFP_NOWAIT);
fbf19803
TG
45 if (cpumask_empty(irq_default_affinity))
46 cpumask_setall(irq_default_affinity);
3795de23
TG
47}
48#else
49static void __init init_irq_default_affinity(void)
50{
51}
52#endif
53
1f5a5b87 54#ifdef CONFIG_SMP
4ab764c3 55static int alloc_masks(struct irq_desc *desc, int node)
1f5a5b87 56{
9df872fa 57 if (!zalloc_cpumask_var_node(&desc->irq_common_data.affinity,
4ab764c3 58 GFP_KERNEL, node))
1f5a5b87
TG
59 return -ENOMEM;
60
0d3f5425
TG
61#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
62 if (!zalloc_cpumask_var_node(&desc->irq_common_data.effective_affinity,
63 GFP_KERNEL, node)) {
64 free_cpumask_var(desc->irq_common_data.affinity);
65 return -ENOMEM;
66 }
67#endif
68
1f5a5b87 69#ifdef CONFIG_GENERIC_PENDING_IRQ
4ab764c3 70 if (!zalloc_cpumask_var_node(&desc->pending_mask, GFP_KERNEL, node)) {
0d3f5425
TG
71#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
72 free_cpumask_var(desc->irq_common_data.effective_affinity);
73#endif
9df872fa 74 free_cpumask_var(desc->irq_common_data.affinity);
1f5a5b87
TG
75 return -ENOMEM;
76 }
77#endif
78 return 0;
79}
80
45ddcecb
TG
81static void desc_smp_init(struct irq_desc *desc, int node,
82 const struct cpumask *affinity)
1f5a5b87 83{
45ddcecb
TG
84 if (!affinity)
85 affinity = irq_default_affinity;
86 cpumask_copy(desc->irq_common_data.affinity, affinity);
87
b7b29338
TG
88#ifdef CONFIG_GENERIC_PENDING_IRQ
89 cpumask_clear(desc->pending_mask);
90#endif
449e9cae
JL
91#ifdef CONFIG_NUMA
92 desc->irq_common_data.node = node;
93#endif
b7b29338
TG
94}
95
1f5a5b87
TG
96#else
97static inline int
4ab764c3 98alloc_masks(struct irq_desc *desc, int node) { return 0; }
45ddcecb
TG
99static inline void
100desc_smp_init(struct irq_desc *desc, int node, const struct cpumask *affinity) { }
1f5a5b87
TG
101#endif
102
b6873807 103static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node,
45ddcecb 104 const struct cpumask *affinity, struct module *owner)
1f5a5b87 105{
6c9ae009
ED
106 int cpu;
107
af7080e0 108 desc->irq_common_data.handler_data = NULL;
b237721c 109 desc->irq_common_data.msi_desc = NULL;
af7080e0 110
0d0b4c86 111 desc->irq_data.common = &desc->irq_common_data;
1f5a5b87
TG
112 desc->irq_data.irq = irq;
113 desc->irq_data.chip = &no_irq_chip;
114 desc->irq_data.chip_data = NULL;
f9e4989e 115 irq_settings_clr_and_set(desc, ~0, _IRQ_DEFAULT_INIT_FLAGS);
801a0e9a 116 irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
d829b8fb 117 irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
1f5a5b87
TG
118 desc->handle_irq = handle_bad_irq;
119 desc->depth = 1;
b7b29338
TG
120 desc->irq_count = 0;
121 desc->irqs_unhandled = 0;
1136b072 122 desc->tot_count = 0;
1f5a5b87 123 desc->name = NULL;
b6873807 124 desc->owner = owner;
6c9ae009
ED
125 for_each_possible_cpu(cpu)
126 *per_cpu_ptr(desc->kstat_irqs, cpu) = 0;
45ddcecb 127 desc_smp_init(desc, node, affinity);
1f5a5b87
TG
128}
129
3795de23
TG
130int nr_irqs = NR_IRQS;
131EXPORT_SYMBOL_GPL(nr_irqs);
132
a05a900a 133static DEFINE_MUTEX(sparse_irq_lock);
c1ee6264 134static DECLARE_BITMAP(allocated_irqs, IRQ_BITMAP_BITS);
1f5a5b87 135
3795de23
TG
136#ifdef CONFIG_SPARSE_IRQ
137
ecb3f394
CG
138static void irq_kobj_release(struct kobject *kobj);
139
140#ifdef CONFIG_SYSFS
141static struct kobject *irq_kobj_base;
142
143#define IRQ_ATTR_RO(_name) \
144static struct kobj_attribute _name##_attr = __ATTR_RO(_name)
145
146static ssize_t per_cpu_count_show(struct kobject *kobj,
147 struct kobj_attribute *attr, char *buf)
148{
149 struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj);
150 int cpu, irq = desc->irq_data.irq;
151 ssize_t ret = 0;
152 char *p = "";
153
154 for_each_possible_cpu(cpu) {
155 unsigned int c = kstat_irqs_cpu(irq, cpu);
156
157 ret += scnprintf(buf + ret, PAGE_SIZE - ret, "%s%u", p, c);
158 p = ",";
159 }
160
161 ret += scnprintf(buf + ret, PAGE_SIZE - ret, "\n");
162 return ret;
163}
164IRQ_ATTR_RO(per_cpu_count);
165
166static ssize_t chip_name_show(struct kobject *kobj,
167 struct kobj_attribute *attr, char *buf)
168{
169 struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj);
170 ssize_t ret = 0;
171
172 raw_spin_lock_irq(&desc->lock);
173 if (desc->irq_data.chip && desc->irq_data.chip->name) {
174 ret = scnprintf(buf, PAGE_SIZE, "%s\n",
175 desc->irq_data.chip->name);
176 }
177 raw_spin_unlock_irq(&desc->lock);
178
179 return ret;
180}
181IRQ_ATTR_RO(chip_name);
182
183static ssize_t hwirq_show(struct kobject *kobj,
184 struct kobj_attribute *attr, char *buf)
185{
186 struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj);
187 ssize_t ret = 0;
188
189 raw_spin_lock_irq(&desc->lock);
190 if (desc->irq_data.domain)
191 ret = sprintf(buf, "%d\n", (int)desc->irq_data.hwirq);
192 raw_spin_unlock_irq(&desc->lock);
193
194 return ret;
195}
196IRQ_ATTR_RO(hwirq);
197
198static ssize_t type_show(struct kobject *kobj,
199 struct kobj_attribute *attr, char *buf)
200{
201 struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj);
202 ssize_t ret = 0;
203
204 raw_spin_lock_irq(&desc->lock);
205 ret = sprintf(buf, "%s\n",
206 irqd_is_level_type(&desc->irq_data) ? "level" : "edge");
207 raw_spin_unlock_irq(&desc->lock);
208
209 return ret;
210
211}
212IRQ_ATTR_RO(type);
213
d61e2944
AS
214static ssize_t wakeup_show(struct kobject *kobj,
215 struct kobj_attribute *attr, char *buf)
216{
217 struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj);
218 ssize_t ret = 0;
219
220 raw_spin_lock_irq(&desc->lock);
221 ret = sprintf(buf, "%s\n",
222 irqd_is_wakeup_set(&desc->irq_data) ? "enabled" : "disabled");
223 raw_spin_unlock_irq(&desc->lock);
224
225 return ret;
226
227}
228IRQ_ATTR_RO(wakeup);
229
ecb3f394
CG
230static ssize_t name_show(struct kobject *kobj,
231 struct kobj_attribute *attr, char *buf)
232{
233 struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj);
234 ssize_t ret = 0;
235
236 raw_spin_lock_irq(&desc->lock);
237 if (desc->name)
238 ret = scnprintf(buf, PAGE_SIZE, "%s\n", desc->name);
239 raw_spin_unlock_irq(&desc->lock);
240
241 return ret;
242}
243IRQ_ATTR_RO(name);
244
245static ssize_t actions_show(struct kobject *kobj,
246 struct kobj_attribute *attr, char *buf)
247{
248 struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj);
249 struct irqaction *action;
250 ssize_t ret = 0;
251 char *p = "";
252
253 raw_spin_lock_irq(&desc->lock);
254 for (action = desc->action; action != NULL; action = action->next) {
255 ret += scnprintf(buf + ret, PAGE_SIZE - ret, "%s%s",
256 p, action->name);
257 p = ",";
258 }
259 raw_spin_unlock_irq(&desc->lock);
260
261 if (ret)
262 ret += scnprintf(buf + ret, PAGE_SIZE - ret, "\n");
263
264 return ret;
265}
266IRQ_ATTR_RO(actions);
267
268static struct attribute *irq_attrs[] = {
269 &per_cpu_count_attr.attr,
270 &chip_name_attr.attr,
271 &hwirq_attr.attr,
272 &type_attr.attr,
d61e2944 273 &wakeup_attr.attr,
ecb3f394
CG
274 &name_attr.attr,
275 &actions_attr.attr,
276 NULL
277};
278
279static struct kobj_type irq_kobj_type = {
280 .release = irq_kobj_release,
281 .sysfs_ops = &kobj_sysfs_ops,
282 .default_attrs = irq_attrs,
283};
284
285static void irq_sysfs_add(int irq, struct irq_desc *desc)
286{
287 if (irq_kobj_base) {
288 /*
289 * Continue even in case of failure as this is nothing
290 * crucial.
291 */
292 if (kobject_add(&desc->kobj, irq_kobj_base, "%d", irq))
293 pr_warn("Failed to add kobject for irq %d\n", irq);
294 }
295}
296
297static int __init irq_sysfs_init(void)
298{
299 struct irq_desc *desc;
300 int irq;
301
302 /* Prevent concurrent irq alloc/free */
303 irq_lock_sparse();
304
305 irq_kobj_base = kobject_create_and_add("irq", kernel_kobj);
306 if (!irq_kobj_base) {
307 irq_unlock_sparse();
308 return -ENOMEM;
309 }
310
311 /* Add the already allocated interrupts */
312 for_each_irq_desc(irq, desc)
313 irq_sysfs_add(irq, desc);
314 irq_unlock_sparse();
315
316 return 0;
317}
318postcore_initcall(irq_sysfs_init);
319
320#else /* !CONFIG_SYSFS */
321
322static struct kobj_type irq_kobj_type = {
323 .release = irq_kobj_release,
324};
325
326static void irq_sysfs_add(int irq, struct irq_desc *desc) {}
327
328#endif /* CONFIG_SYSFS */
329
baa0d233 330static RADIX_TREE(irq_desc_tree, GFP_KERNEL);
3795de23 331
1f5a5b87 332static void irq_insert_desc(unsigned int irq, struct irq_desc *desc)
3795de23
TG
333{
334 radix_tree_insert(&irq_desc_tree, irq, desc);
335}
336
337struct irq_desc *irq_to_desc(unsigned int irq)
338{
339 return radix_tree_lookup(&irq_desc_tree, irq);
340}
3911ff30 341EXPORT_SYMBOL(irq_to_desc);
3795de23 342
1f5a5b87
TG
343static void delete_irq_desc(unsigned int irq)
344{
345 radix_tree_delete(&irq_desc_tree, irq);
346}
347
348#ifdef CONFIG_SMP
349static void free_masks(struct irq_desc *desc)
350{
351#ifdef CONFIG_GENERIC_PENDING_IRQ
352 free_cpumask_var(desc->pending_mask);
353#endif
9df872fa 354 free_cpumask_var(desc->irq_common_data.affinity);
0d3f5425
TG
355#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
356 free_cpumask_var(desc->irq_common_data.effective_affinity);
357#endif
1f5a5b87
TG
358}
359#else
360static inline void free_masks(struct irq_desc *desc) { }
361#endif
362
c291ee62
TG
363void irq_lock_sparse(void)
364{
365 mutex_lock(&sparse_irq_lock);
366}
367
368void irq_unlock_sparse(void)
369{
370 mutex_unlock(&sparse_irq_lock);
371}
372
45ddcecb
TG
373static struct irq_desc *alloc_desc(int irq, int node, unsigned int flags,
374 const struct cpumask *affinity,
375 struct module *owner)
1f5a5b87
TG
376{
377 struct irq_desc *desc;
1f5a5b87 378
4ab764c3 379 desc = kzalloc_node(sizeof(*desc), GFP_KERNEL, node);
1f5a5b87
TG
380 if (!desc)
381 return NULL;
382 /* allocate based on nr_cpu_ids */
6c9ae009 383 desc->kstat_irqs = alloc_percpu(unsigned int);
1f5a5b87
TG
384 if (!desc->kstat_irqs)
385 goto err_desc;
386
4ab764c3 387 if (alloc_masks(desc, node))
1f5a5b87
TG
388 goto err_kstat;
389
390 raw_spin_lock_init(&desc->lock);
391 lockdep_set_class(&desc->lock, &irq_desc_lock_class);
9114014c 392 mutex_init(&desc->request_mutex);
425a5072 393 init_rcu_head(&desc->rcu);
1f5a5b87 394
45ddcecb
TG
395 desc_set_defaults(irq, desc, node, affinity, owner);
396 irqd_set(&desc->irq_data, flags);
ecb3f394 397 kobject_init(&desc->kobj, &irq_kobj_type);
1f5a5b87
TG
398
399 return desc;
400
401err_kstat:
6c9ae009 402 free_percpu(desc->kstat_irqs);
1f5a5b87
TG
403err_desc:
404 kfree(desc);
405 return NULL;
406}
407
ecb3f394 408static void irq_kobj_release(struct kobject *kobj)
425a5072 409{
ecb3f394 410 struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj);
425a5072
TG
411
412 free_masks(desc);
413 free_percpu(desc->kstat_irqs);
414 kfree(desc);
415}
416
ecb3f394
CG
417static void delayed_free_desc(struct rcu_head *rhp)
418{
419 struct irq_desc *desc = container_of(rhp, struct irq_desc, rcu);
420
421 kobject_put(&desc->kobj);
422}
423
1f5a5b87
TG
424static void free_desc(unsigned int irq)
425{
426 struct irq_desc *desc = irq_to_desc(irq);
1f5a5b87 427
087cdfb6 428 irq_remove_debugfs_entry(desc);
13bfe99e
TG
429 unregister_irq_proc(irq, desc);
430
c291ee62
TG
431 /*
432 * sparse_irq_lock protects also show_interrupts() and
433 * kstat_irq_usr(). Once we deleted the descriptor from the
434 * sparse tree we can free it. Access in proc will fail to
435 * lookup the descriptor.
ecb3f394
CG
436 *
437 * The sysfs entry must be serialized against a concurrent
438 * irq_sysfs_init() as well.
c291ee62 439 */
ecb3f394 440 kobject_del(&desc->kobj);
1f5a5b87 441 delete_irq_desc(irq);
1f5a5b87 442
425a5072
TG
443 /*
444 * We free the descriptor, masks and stat fields via RCU. That
445 * allows demultiplex interrupts to do rcu based management of
446 * the child interrupts.
4a5f4d2f 447 * This also allows us to use rcu in kstat_irqs_usr().
425a5072
TG
448 */
449 call_rcu(&desc->rcu, delayed_free_desc);
1f5a5b87
TG
450}
451
b6873807 452static int alloc_descs(unsigned int start, unsigned int cnt, int node,
bec04037
DL
453 const struct irq_affinity_desc *affinity,
454 struct module *owner)
1f5a5b87
TG
455{
456 struct irq_desc *desc;
e75eafb9 457 int i;
45ddcecb 458
e75eafb9
TG
459 /* Validate affinity mask(s) */
460 if (affinity) {
12fee4cd 461 for (i = 0; i < cnt; i++) {
bec04037 462 if (cpumask_empty(&affinity[i].mask))
e75eafb9
TG
463 return -EINVAL;
464 }
465 }
45ddcecb 466
1f5a5b87 467 for (i = 0; i < cnt; i++) {
bec04037 468 const struct cpumask *mask = NULL;
c410abbb 469 unsigned int flags = 0;
bec04037 470
45ddcecb 471 if (affinity) {
c410abbb
DL
472 if (affinity->is_managed) {
473 flags = IRQD_AFFINITY_MANAGED |
474 IRQD_MANAGED_SHUTDOWN;
475 }
bec04037 476 mask = &affinity->mask;
c410abbb 477 node = cpu_to_node(cpumask_first(mask));
e75eafb9 478 affinity++;
45ddcecb 479 }
c410abbb 480
45ddcecb 481 desc = alloc_desc(start + i, node, flags, mask, owner);
1f5a5b87
TG
482 if (!desc)
483 goto err;
1f5a5b87 484 irq_insert_desc(start + i, desc);
ecb3f394 485 irq_sysfs_add(start + i, desc);
e0b47794 486 irq_add_debugfs_entry(start + i, desc);
1f5a5b87 487 }
12ac1d0f 488 bitmap_set(allocated_irqs, start, cnt);
1f5a5b87
TG
489 return start;
490
491err:
492 for (i--; i >= 0; i--)
493 free_desc(start + i);
1f5a5b87
TG
494 return -ENOMEM;
495}
496
ed4dea6e 497static int irq_expand_nr_irqs(unsigned int nr)
e7bcecb7 498{
ed4dea6e 499 if (nr > IRQ_BITMAP_BITS)
e7bcecb7 500 return -ENOMEM;
ed4dea6e 501 nr_irqs = nr;
e7bcecb7
TG
502 return 0;
503}
504
3795de23
TG
505int __init early_irq_init(void)
506{
b683de2b 507 int i, initcnt, node = first_online_node;
3795de23 508 struct irq_desc *desc;
3795de23
TG
509
510 init_irq_default_affinity();
511
b683de2b
TG
512 /* Let arch update nr_irqs and return the nr of preallocated irqs */
513 initcnt = arch_probe_nr_irqs();
5a29ef22
VL
514 printk(KERN_INFO "NR_IRQS: %d, nr_irqs: %d, preallocated irqs: %d\n",
515 NR_IRQS, nr_irqs, initcnt);
3795de23 516
c1ee6264
TG
517 if (WARN_ON(nr_irqs > IRQ_BITMAP_BITS))
518 nr_irqs = IRQ_BITMAP_BITS;
519
520 if (WARN_ON(initcnt > IRQ_BITMAP_BITS))
521 initcnt = IRQ_BITMAP_BITS;
522
523 if (initcnt > nr_irqs)
524 nr_irqs = initcnt;
525
b683de2b 526 for (i = 0; i < initcnt; i++) {
45ddcecb 527 desc = alloc_desc(i, node, 0, NULL, NULL);
aa99ec0f
TG
528 set_bit(i, allocated_irqs);
529 irq_insert_desc(i, desc);
3795de23 530 }
3795de23
TG
531 return arch_early_irq_init();
532}
533
3795de23
TG
534#else /* !CONFIG_SPARSE_IRQ */
535
536struct irq_desc irq_desc[NR_IRQS] __cacheline_aligned_in_smp = {
537 [0 ... NR_IRQS-1] = {
3795de23
TG
538 .handle_irq = handle_bad_irq,
539 .depth = 1,
540 .lock = __RAW_SPIN_LOCK_UNLOCKED(irq_desc->lock),
541 }
542};
543
3795de23
TG
544int __init early_irq_init(void)
545{
aa99ec0f 546 int count, i, node = first_online_node;
3795de23 547 struct irq_desc *desc;
3795de23
TG
548
549 init_irq_default_affinity();
550
5a29ef22 551 printk(KERN_INFO "NR_IRQS: %d\n", NR_IRQS);
3795de23
TG
552
553 desc = irq_desc;
554 count = ARRAY_SIZE(irq_desc);
555
556 for (i = 0; i < count; i++) {
6c9ae009 557 desc[i].kstat_irqs = alloc_percpu(unsigned int);
4ab764c3 558 alloc_masks(&desc[i], node);
e7fbad30 559 raw_spin_lock_init(&desc[i].lock);
154cd387 560 lockdep_set_class(&desc[i].lock, &irq_desc_lock_class);
45ddcecb 561 desc_set_defaults(i, &desc[i], node, NULL, NULL);
3795de23
TG
562 }
563 return arch_early_irq_init();
564}
565
566struct irq_desc *irq_to_desc(unsigned int irq)
567{
568 return (irq < NR_IRQS) ? irq_desc + irq : NULL;
569}
2c45aada 570EXPORT_SYMBOL(irq_to_desc);
3795de23 571
1f5a5b87
TG
572static void free_desc(unsigned int irq)
573{
d8179bc0
TG
574 struct irq_desc *desc = irq_to_desc(irq);
575 unsigned long flags;
576
577 raw_spin_lock_irqsave(&desc->lock, flags);
45ddcecb 578 desc_set_defaults(irq, desc, irq_desc_get_node(desc), NULL, NULL);
d8179bc0 579 raw_spin_unlock_irqrestore(&desc->lock, flags);
1f5a5b87
TG
580}
581
b6873807 582static inline int alloc_descs(unsigned int start, unsigned int cnt, int node,
bec04037 583 const struct irq_affinity_desc *affinity,
b6873807 584 struct module *owner)
1f5a5b87 585{
b6873807
SAS
586 u32 i;
587
588 for (i = 0; i < cnt; i++) {
589 struct irq_desc *desc = irq_to_desc(start + i);
590
591 desc->owner = owner;
592 }
12ac1d0f 593 bitmap_set(allocated_irqs, start, cnt);
1f5a5b87
TG
594 return start;
595}
e7bcecb7 596
ed4dea6e 597static int irq_expand_nr_irqs(unsigned int nr)
e7bcecb7
TG
598{
599 return -ENOMEM;
600}
601
f63b6a05
TG
602void irq_mark_irq(unsigned int irq)
603{
604 mutex_lock(&sparse_irq_lock);
605 bitmap_set(allocated_irqs, irq, 1);
606 mutex_unlock(&sparse_irq_lock);
607}
608
c940e01c
TG
609#ifdef CONFIG_GENERIC_IRQ_LEGACY
610void irq_init_desc(unsigned int irq)
611{
d8179bc0 612 free_desc(irq);
c940e01c
TG
613}
614#endif
615
3795de23
TG
616#endif /* !CONFIG_SPARSE_IRQ */
617
fe12bc2c
TG
618/**
619 * generic_handle_irq - Invoke the handler for a particular irq
620 * @irq: The irq number to handle
621 *
622 */
623int generic_handle_irq(unsigned int irq)
624{
625 struct irq_desc *desc = irq_to_desc(irq);
626
627 if (!desc)
628 return -EINVAL;
bd0b9ac4 629 generic_handle_irq_desc(desc);
fe12bc2c
TG
630 return 0;
631}
edf76f83 632EXPORT_SYMBOL_GPL(generic_handle_irq);
fe12bc2c 633
76ba59f8
MZ
634#ifdef CONFIG_HANDLE_DOMAIN_IRQ
635/**
636 * __handle_domain_irq - Invoke the handler for a HW irq belonging to a domain
637 * @domain: The domain where to perform the lookup
638 * @hwirq: The HW irq number to convert to a logical one
639 * @lookup: Whether to perform the domain lookup or not
640 * @regs: Register file coming from the low-level handling code
641 *
642 * Returns: 0 on success, or -EINVAL if conversion has failed
643 */
644int __handle_domain_irq(struct irq_domain *domain, unsigned int hwirq,
645 bool lookup, struct pt_regs *regs)
646{
647 struct pt_regs *old_regs = set_irq_regs(regs);
648 unsigned int irq = hwirq;
649 int ret = 0;
650
651 irq_enter();
652
653#ifdef CONFIG_IRQ_DOMAIN
654 if (lookup)
655 irq = irq_find_mapping(domain, hwirq);
656#endif
657
658 /*
659 * Some hardware gives randomly wrong interrupts. Rather
660 * than crashing, do something sensible.
661 */
662 if (unlikely(!irq || irq >= nr_irqs)) {
663 ack_bad_irq(irq);
664 ret = -EINVAL;
665 } else {
666 generic_handle_irq(irq);
667 }
668
669 irq_exit();
670 set_irq_regs(old_regs);
671 return ret;
672}
6e4933a0
JT
673
674#ifdef CONFIG_IRQ_DOMAIN
675/**
676 * handle_domain_nmi - Invoke the handler for a HW irq belonging to a domain
677 * @domain: The domain where to perform the lookup
678 * @hwirq: The HW irq number to convert to a logical one
679 * @regs: Register file coming from the low-level handling code
680 *
681 * Returns: 0 on success, or -EINVAL if conversion has failed
682 */
683int handle_domain_nmi(struct irq_domain *domain, unsigned int hwirq,
684 struct pt_regs *regs)
685{
686 struct pt_regs *old_regs = set_irq_regs(regs);
687 unsigned int irq;
688 int ret = 0;
689
690 nmi_enter();
691
692 irq = irq_find_mapping(domain, hwirq);
693
694 /*
695 * ack_bad_irq is not NMI-safe, just report
696 * an invalid interrupt.
697 */
698 if (likely(irq))
699 generic_handle_irq(irq);
700 else
701 ret = -EINVAL;
702
703 nmi_exit();
704 set_irq_regs(old_regs);
705 return ret;
706}
707#endif
76ba59f8
MZ
708#endif
709
1f5a5b87
TG
710/* Dynamic interrupt handling */
711
712/**
713 * irq_free_descs - free irq descriptors
714 * @from: Start of descriptor range
715 * @cnt: Number of consecutive irqs to free
716 */
717void irq_free_descs(unsigned int from, unsigned int cnt)
718{
1f5a5b87
TG
719 int i;
720
721 if (from >= nr_irqs || (from + cnt) > nr_irqs)
722 return;
723
12ac1d0f 724 mutex_lock(&sparse_irq_lock);
1f5a5b87
TG
725 for (i = 0; i < cnt; i++)
726 free_desc(from + i);
727
1f5a5b87 728 bitmap_clear(allocated_irqs, from, cnt);
a05a900a 729 mutex_unlock(&sparse_irq_lock);
1f5a5b87 730}
edf76f83 731EXPORT_SYMBOL_GPL(irq_free_descs);
1f5a5b87
TG
732
733/**
734 * irq_alloc_descs - allocate and initialize a range of irq descriptors
735 * @irq: Allocate for specific irq number if irq >= 0
736 * @from: Start the search from this irq number
737 * @cnt: Number of consecutive irqs to allocate.
738 * @node: Preferred node on which the irq descriptor should be allocated
d522a0d1 739 * @owner: Owning module (can be NULL)
e75eafb9
TG
740 * @affinity: Optional pointer to an affinity mask array of size @cnt which
741 * hints where the irq descriptors should be allocated and which
742 * default affinities to use
1f5a5b87
TG
743 *
744 * Returns the first irq number or error code
745 */
746int __ref
b6873807 747__irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
bec04037 748 struct module *owner, const struct irq_affinity_desc *affinity)
1f5a5b87 749{
1f5a5b87
TG
750 int start, ret;
751
752 if (!cnt)
753 return -EINVAL;
754
c5182b88
MB
755 if (irq >= 0) {
756 if (from > irq)
757 return -EINVAL;
758 from = irq;
62a08ae2
TG
759 } else {
760 /*
761 * For interrupts which are freely allocated the
762 * architecture can force a lower bound to the @from
763 * argument. x86 uses this to exclude the GSI space.
764 */
765 from = arch_dynirq_lower_bound(from);
c5182b88
MB
766 }
767
a05a900a 768 mutex_lock(&sparse_irq_lock);
1f5a5b87 769
ed4dea6e
YL
770 start = bitmap_find_next_zero_area(allocated_irqs, IRQ_BITMAP_BITS,
771 from, cnt, 0);
1f5a5b87
TG
772 ret = -EEXIST;
773 if (irq >=0 && start != irq)
12ac1d0f 774 goto unlock;
1f5a5b87 775
ed4dea6e
YL
776 if (start + cnt > nr_irqs) {
777 ret = irq_expand_nr_irqs(start + cnt);
e7bcecb7 778 if (ret)
12ac1d0f 779 goto unlock;
e7bcecb7 780 }
12ac1d0f
TG
781 ret = alloc_descs(start, cnt, node, affinity, owner);
782unlock:
a05a900a 783 mutex_unlock(&sparse_irq_lock);
1f5a5b87
TG
784 return ret;
785}
b6873807 786EXPORT_SYMBOL_GPL(__irq_alloc_descs);
1f5a5b87 787
7b6ef126
TG
788#ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
789/**
790 * irq_alloc_hwirqs - Allocate an irq descriptor and initialize the hardware
791 * @cnt: number of interrupts to allocate
792 * @node: node on which to allocate
793 *
794 * Returns an interrupt number > 0 or 0, if the allocation fails.
795 */
796unsigned int irq_alloc_hwirqs(int cnt, int node)
797{
06ee6d57 798 int i, irq = __irq_alloc_descs(-1, 0, cnt, node, NULL, NULL);
7b6ef126
TG
799
800 if (irq < 0)
801 return 0;
802
803 for (i = irq; cnt > 0; i++, cnt--) {
804 if (arch_setup_hwirq(i, node))
805 goto err;
806 irq_clear_status_flags(i, _IRQ_NOREQUEST);
807 }
808 return irq;
809
810err:
811 for (i--; i >= irq; i--) {
812 irq_set_status_flags(i, _IRQ_NOREQUEST | _IRQ_NOPROBE);
813 arch_teardown_hwirq(i);
814 }
815 irq_free_descs(irq, cnt);
816 return 0;
817}
818EXPORT_SYMBOL_GPL(irq_alloc_hwirqs);
819
820/**
821 * irq_free_hwirqs - Free irq descriptor and cleanup the hardware
822 * @from: Free from irq number
823 * @cnt: number of interrupts to free
824 *
825 */
826void irq_free_hwirqs(unsigned int from, int cnt)
827{
8844aad8 828 int i, j;
7b6ef126 829
8844aad8 830 for (i = from, j = cnt; j > 0; i++, j--) {
7b6ef126
TG
831 irq_set_status_flags(i, _IRQ_NOREQUEST | _IRQ_NOPROBE);
832 arch_teardown_hwirq(i);
833 }
834 irq_free_descs(from, cnt);
835}
836EXPORT_SYMBOL_GPL(irq_free_hwirqs);
837#endif
838
a98d24b7
TG
839/**
840 * irq_get_next_irq - get next allocated irq number
841 * @offset: where to start the search
842 *
843 * Returns next irq number after offset or nr_irqs if none is found.
844 */
845unsigned int irq_get_next_irq(unsigned int offset)
846{
847 return find_next_bit(allocated_irqs, nr_irqs, offset);
848}
849
d5eb4ad2 850struct irq_desc *
31d9d9b6
MZ
851__irq_get_desc_lock(unsigned int irq, unsigned long *flags, bool bus,
852 unsigned int check)
d5eb4ad2
TG
853{
854 struct irq_desc *desc = irq_to_desc(irq);
855
856 if (desc) {
31d9d9b6
MZ
857 if (check & _IRQ_DESC_CHECK) {
858 if ((check & _IRQ_DESC_PERCPU) &&
859 !irq_settings_is_per_cpu_devid(desc))
860 return NULL;
861
862 if (!(check & _IRQ_DESC_PERCPU) &&
863 irq_settings_is_per_cpu_devid(desc))
864 return NULL;
865 }
866
d5eb4ad2
TG
867 if (bus)
868 chip_bus_lock(desc);
869 raw_spin_lock_irqsave(&desc->lock, *flags);
870 }
871 return desc;
872}
873
874void __irq_put_desc_unlock(struct irq_desc *desc, unsigned long flags, bool bus)
875{
876 raw_spin_unlock_irqrestore(&desc->lock, flags);
877 if (bus)
878 chip_bus_sync_unlock(desc);
879}
880
222df54f
MZ
881int irq_set_percpu_devid_partition(unsigned int irq,
882 const struct cpumask *affinity)
31d9d9b6
MZ
883{
884 struct irq_desc *desc = irq_to_desc(irq);
885
886 if (!desc)
887 return -EINVAL;
888
889 if (desc->percpu_enabled)
890 return -EINVAL;
891
892 desc->percpu_enabled = kzalloc(sizeof(*desc->percpu_enabled), GFP_KERNEL);
893
894 if (!desc->percpu_enabled)
895 return -ENOMEM;
896
222df54f
MZ
897 if (affinity)
898 desc->percpu_affinity = affinity;
899 else
900 desc->percpu_affinity = cpu_possible_mask;
901
31d9d9b6
MZ
902 irq_set_percpu_devid_flags(irq);
903 return 0;
904}
905
222df54f
MZ
906int irq_set_percpu_devid(unsigned int irq)
907{
908 return irq_set_percpu_devid_partition(irq, NULL);
909}
910
911int irq_get_percpu_devid_partition(unsigned int irq, struct cpumask *affinity)
912{
913 struct irq_desc *desc = irq_to_desc(irq);
914
915 if (!desc || !desc->percpu_enabled)
916 return -EINVAL;
917
918 if (affinity)
919 cpumask_copy(affinity, desc->percpu_affinity);
920
921 return 0;
922}
5ffeb050 923EXPORT_SYMBOL_GPL(irq_get_percpu_devid_partition);
222df54f 924
792d0018
TG
925void kstat_incr_irq_this_cpu(unsigned int irq)
926{
b51bf95c 927 kstat_incr_irqs_this_cpu(irq_to_desc(irq));
792d0018
TG
928}
929
c291ee62
TG
930/**
931 * kstat_irqs_cpu - Get the statistics for an interrupt on a cpu
932 * @irq: The interrupt number
933 * @cpu: The cpu number
934 *
935 * Returns the sum of interrupt counts on @cpu since boot for
936 * @irq. The caller must ensure that the interrupt is not removed
937 * concurrently.
938 */
3795de23
TG
939unsigned int kstat_irqs_cpu(unsigned int irq, int cpu)
940{
941 struct irq_desc *desc = irq_to_desc(irq);
6c9ae009
ED
942
943 return desc && desc->kstat_irqs ?
944 *per_cpu_ptr(desc->kstat_irqs, cpu) : 0;
3795de23 945}
478735e3 946
c291ee62
TG
947/**
948 * kstat_irqs - Get the statistics for an interrupt
949 * @irq: The interrupt number
950 *
951 * Returns the sum of interrupt counts on all cpus since boot for
952 * @irq. The caller must ensure that the interrupt is not removed
953 * concurrently.
954 */
478735e3
KH
955unsigned int kstat_irqs(unsigned int irq)
956{
957 struct irq_desc *desc = irq_to_desc(irq);
5e9662fa 958 unsigned int sum = 0;
1136b072 959 int cpu;
478735e3 960
6c9ae009 961 if (!desc || !desc->kstat_irqs)
478735e3 962 return 0;
1136b072
TG
963 if (!irq_settings_is_per_cpu_devid(desc) &&
964 !irq_settings_is_per_cpu(desc))
965 return desc->tot_count;
966
478735e3 967 for_each_possible_cpu(cpu)
6c9ae009 968 sum += *per_cpu_ptr(desc->kstat_irqs, cpu);
478735e3
KH
969 return sum;
970}
c291ee62
TG
971
972/**
973 * kstat_irqs_usr - Get the statistics for an interrupt
974 * @irq: The interrupt number
975 *
4a5f4d2f
ED
976 * Returns the sum of interrupt counts on all cpus since boot for @irq.
977 * Contrary to kstat_irqs() this can be called from any context.
978 * It uses rcu since a concurrent removal of an interrupt descriptor is
979 * observing an rcu grace period before delayed_free_desc()/irq_kobj_release().
c291ee62
TG
980 */
981unsigned int kstat_irqs_usr(unsigned int irq)
982{
7df0b278 983 unsigned int sum;
c291ee62 984
4a5f4d2f 985 rcu_read_lock();
c291ee62 986 sum = kstat_irqs(irq);
4a5f4d2f 987 rcu_read_unlock();
c291ee62
TG
988 return sum;
989}