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52a65ff5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
3795de23 TG |
2 | /* |
3 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
4 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
5 | * | |
99bfce5d TG |
6 | * This file contains the interrupt descriptor management code. Detailed |
7 | * information is available in Documentation/core-api/genericirq.rst | |
3795de23 TG |
8 | * |
9 | */ | |
10 | #include <linux/irq.h> | |
11 | #include <linux/slab.h> | |
ec53cf23 | 12 | #include <linux/export.h> |
3795de23 TG |
13 | #include <linux/interrupt.h> |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/radix-tree.h> | |
1f5a5b87 | 16 | #include <linux/bitmap.h> |
76ba59f8 | 17 | #include <linux/irqdomain.h> |
ecb3f394 | 18 | #include <linux/sysfs.h> |
3795de23 TG |
19 | |
20 | #include "internals.h" | |
21 | ||
22 | /* | |
23 | * lockdep: we want to handle all irq_desc locks as a single lock-class: | |
24 | */ | |
78f90d91 | 25 | static struct lock_class_key irq_desc_lock_class; |
3795de23 | 26 | |
fe051434 | 27 | #if defined(CONFIG_SMP) |
fbf19803 TG |
28 | static int __init irq_affinity_setup(char *str) |
29 | { | |
10d94ff4 | 30 | alloc_bootmem_cpumask_var(&irq_default_affinity); |
fbf19803 TG |
31 | cpulist_parse(str, irq_default_affinity); |
32 | /* | |
33 | * Set at least the boot cpu. We don't want to end up with | |
34 | * bugreports caused by random comandline masks | |
35 | */ | |
36 | cpumask_set_cpu(smp_processor_id(), irq_default_affinity); | |
37 | return 1; | |
38 | } | |
39 | __setup("irqaffinity=", irq_affinity_setup); | |
40 | ||
3795de23 TG |
41 | static void __init init_irq_default_affinity(void) |
42 | { | |
10d94ff4 | 43 | if (!cpumask_available(irq_default_affinity)) |
fbf19803 | 44 | zalloc_cpumask_var(&irq_default_affinity, GFP_NOWAIT); |
fbf19803 TG |
45 | if (cpumask_empty(irq_default_affinity)) |
46 | cpumask_setall(irq_default_affinity); | |
3795de23 TG |
47 | } |
48 | #else | |
49 | static void __init init_irq_default_affinity(void) | |
50 | { | |
51 | } | |
52 | #endif | |
53 | ||
1f5a5b87 | 54 | #ifdef CONFIG_SMP |
4ab764c3 | 55 | static int alloc_masks(struct irq_desc *desc, int node) |
1f5a5b87 | 56 | { |
9df872fa | 57 | if (!zalloc_cpumask_var_node(&desc->irq_common_data.affinity, |
4ab764c3 | 58 | GFP_KERNEL, node)) |
1f5a5b87 TG |
59 | return -ENOMEM; |
60 | ||
0d3f5425 TG |
61 | #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK |
62 | if (!zalloc_cpumask_var_node(&desc->irq_common_data.effective_affinity, | |
63 | GFP_KERNEL, node)) { | |
64 | free_cpumask_var(desc->irq_common_data.affinity); | |
65 | return -ENOMEM; | |
66 | } | |
67 | #endif | |
68 | ||
1f5a5b87 | 69 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
4ab764c3 | 70 | if (!zalloc_cpumask_var_node(&desc->pending_mask, GFP_KERNEL, node)) { |
0d3f5425 TG |
71 | #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK |
72 | free_cpumask_var(desc->irq_common_data.effective_affinity); | |
73 | #endif | |
9df872fa | 74 | free_cpumask_var(desc->irq_common_data.affinity); |
1f5a5b87 TG |
75 | return -ENOMEM; |
76 | } | |
77 | #endif | |
78 | return 0; | |
79 | } | |
80 | ||
45ddcecb TG |
81 | static void desc_smp_init(struct irq_desc *desc, int node, |
82 | const struct cpumask *affinity) | |
1f5a5b87 | 83 | { |
45ddcecb TG |
84 | if (!affinity) |
85 | affinity = irq_default_affinity; | |
86 | cpumask_copy(desc->irq_common_data.affinity, affinity); | |
87 | ||
b7b29338 TG |
88 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
89 | cpumask_clear(desc->pending_mask); | |
90 | #endif | |
449e9cae JL |
91 | #ifdef CONFIG_NUMA |
92 | desc->irq_common_data.node = node; | |
93 | #endif | |
b7b29338 TG |
94 | } |
95 | ||
1f5a5b87 TG |
96 | #else |
97 | static inline int | |
4ab764c3 | 98 | alloc_masks(struct irq_desc *desc, int node) { return 0; } |
45ddcecb TG |
99 | static inline void |
100 | desc_smp_init(struct irq_desc *desc, int node, const struct cpumask *affinity) { } | |
1f5a5b87 TG |
101 | #endif |
102 | ||
b6873807 | 103 | static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node, |
45ddcecb | 104 | const struct cpumask *affinity, struct module *owner) |
1f5a5b87 | 105 | { |
6c9ae009 ED |
106 | int cpu; |
107 | ||
af7080e0 | 108 | desc->irq_common_data.handler_data = NULL; |
b237721c | 109 | desc->irq_common_data.msi_desc = NULL; |
af7080e0 | 110 | |
0d0b4c86 | 111 | desc->irq_data.common = &desc->irq_common_data; |
1f5a5b87 TG |
112 | desc->irq_data.irq = irq; |
113 | desc->irq_data.chip = &no_irq_chip; | |
114 | desc->irq_data.chip_data = NULL; | |
f9e4989e | 115 | irq_settings_clr_and_set(desc, ~0, _IRQ_DEFAULT_INIT_FLAGS); |
801a0e9a | 116 | irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); |
d829b8fb | 117 | irqd_set(&desc->irq_data, IRQD_IRQ_MASKED); |
1f5a5b87 TG |
118 | desc->handle_irq = handle_bad_irq; |
119 | desc->depth = 1; | |
b7b29338 TG |
120 | desc->irq_count = 0; |
121 | desc->irqs_unhandled = 0; | |
1136b072 | 122 | desc->tot_count = 0; |
1f5a5b87 | 123 | desc->name = NULL; |
b6873807 | 124 | desc->owner = owner; |
6c9ae009 ED |
125 | for_each_possible_cpu(cpu) |
126 | *per_cpu_ptr(desc->kstat_irqs, cpu) = 0; | |
45ddcecb | 127 | desc_smp_init(desc, node, affinity); |
1f5a5b87 TG |
128 | } |
129 | ||
3795de23 TG |
130 | int nr_irqs = NR_IRQS; |
131 | EXPORT_SYMBOL_GPL(nr_irqs); | |
132 | ||
a05a900a | 133 | static DEFINE_MUTEX(sparse_irq_lock); |
c1ee6264 | 134 | static DECLARE_BITMAP(allocated_irqs, IRQ_BITMAP_BITS); |
1f5a5b87 | 135 | |
3795de23 TG |
136 | #ifdef CONFIG_SPARSE_IRQ |
137 | ||
ecb3f394 CG |
138 | static void irq_kobj_release(struct kobject *kobj); |
139 | ||
140 | #ifdef CONFIG_SYSFS | |
141 | static struct kobject *irq_kobj_base; | |
142 | ||
143 | #define IRQ_ATTR_RO(_name) \ | |
144 | static struct kobj_attribute _name##_attr = __ATTR_RO(_name) | |
145 | ||
146 | static ssize_t per_cpu_count_show(struct kobject *kobj, | |
147 | struct kobj_attribute *attr, char *buf) | |
148 | { | |
149 | struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj); | |
150 | int cpu, irq = desc->irq_data.irq; | |
151 | ssize_t ret = 0; | |
152 | char *p = ""; | |
153 | ||
154 | for_each_possible_cpu(cpu) { | |
155 | unsigned int c = kstat_irqs_cpu(irq, cpu); | |
156 | ||
157 | ret += scnprintf(buf + ret, PAGE_SIZE - ret, "%s%u", p, c); | |
158 | p = ","; | |
159 | } | |
160 | ||
161 | ret += scnprintf(buf + ret, PAGE_SIZE - ret, "\n"); | |
162 | return ret; | |
163 | } | |
164 | IRQ_ATTR_RO(per_cpu_count); | |
165 | ||
166 | static ssize_t chip_name_show(struct kobject *kobj, | |
167 | struct kobj_attribute *attr, char *buf) | |
168 | { | |
169 | struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj); | |
170 | ssize_t ret = 0; | |
171 | ||
172 | raw_spin_lock_irq(&desc->lock); | |
173 | if (desc->irq_data.chip && desc->irq_data.chip->name) { | |
174 | ret = scnprintf(buf, PAGE_SIZE, "%s\n", | |
175 | desc->irq_data.chip->name); | |
176 | } | |
177 | raw_spin_unlock_irq(&desc->lock); | |
178 | ||
179 | return ret; | |
180 | } | |
181 | IRQ_ATTR_RO(chip_name); | |
182 | ||
183 | static ssize_t hwirq_show(struct kobject *kobj, | |
184 | struct kobj_attribute *attr, char *buf) | |
185 | { | |
186 | struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj); | |
187 | ssize_t ret = 0; | |
188 | ||
189 | raw_spin_lock_irq(&desc->lock); | |
190 | if (desc->irq_data.domain) | |
191 | ret = sprintf(buf, "%d\n", (int)desc->irq_data.hwirq); | |
192 | raw_spin_unlock_irq(&desc->lock); | |
193 | ||
194 | return ret; | |
195 | } | |
196 | IRQ_ATTR_RO(hwirq); | |
197 | ||
198 | static ssize_t type_show(struct kobject *kobj, | |
199 | struct kobj_attribute *attr, char *buf) | |
200 | { | |
201 | struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj); | |
202 | ssize_t ret = 0; | |
203 | ||
204 | raw_spin_lock_irq(&desc->lock); | |
205 | ret = sprintf(buf, "%s\n", | |
206 | irqd_is_level_type(&desc->irq_data) ? "level" : "edge"); | |
207 | raw_spin_unlock_irq(&desc->lock); | |
208 | ||
209 | return ret; | |
210 | ||
211 | } | |
212 | IRQ_ATTR_RO(type); | |
213 | ||
d61e2944 AS |
214 | static ssize_t wakeup_show(struct kobject *kobj, |
215 | struct kobj_attribute *attr, char *buf) | |
216 | { | |
217 | struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj); | |
218 | ssize_t ret = 0; | |
219 | ||
220 | raw_spin_lock_irq(&desc->lock); | |
221 | ret = sprintf(buf, "%s\n", | |
222 | irqd_is_wakeup_set(&desc->irq_data) ? "enabled" : "disabled"); | |
223 | raw_spin_unlock_irq(&desc->lock); | |
224 | ||
225 | return ret; | |
226 | ||
227 | } | |
228 | IRQ_ATTR_RO(wakeup); | |
229 | ||
ecb3f394 CG |
230 | static ssize_t name_show(struct kobject *kobj, |
231 | struct kobj_attribute *attr, char *buf) | |
232 | { | |
233 | struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj); | |
234 | ssize_t ret = 0; | |
235 | ||
236 | raw_spin_lock_irq(&desc->lock); | |
237 | if (desc->name) | |
238 | ret = scnprintf(buf, PAGE_SIZE, "%s\n", desc->name); | |
239 | raw_spin_unlock_irq(&desc->lock); | |
240 | ||
241 | return ret; | |
242 | } | |
243 | IRQ_ATTR_RO(name); | |
244 | ||
245 | static ssize_t actions_show(struct kobject *kobj, | |
246 | struct kobj_attribute *attr, char *buf) | |
247 | { | |
248 | struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj); | |
249 | struct irqaction *action; | |
250 | ssize_t ret = 0; | |
251 | char *p = ""; | |
252 | ||
253 | raw_spin_lock_irq(&desc->lock); | |
254 | for (action = desc->action; action != NULL; action = action->next) { | |
255 | ret += scnprintf(buf + ret, PAGE_SIZE - ret, "%s%s", | |
256 | p, action->name); | |
257 | p = ","; | |
258 | } | |
259 | raw_spin_unlock_irq(&desc->lock); | |
260 | ||
261 | if (ret) | |
262 | ret += scnprintf(buf + ret, PAGE_SIZE - ret, "\n"); | |
263 | ||
264 | return ret; | |
265 | } | |
266 | IRQ_ATTR_RO(actions); | |
267 | ||
268 | static struct attribute *irq_attrs[] = { | |
269 | &per_cpu_count_attr.attr, | |
270 | &chip_name_attr.attr, | |
271 | &hwirq_attr.attr, | |
272 | &type_attr.attr, | |
d61e2944 | 273 | &wakeup_attr.attr, |
ecb3f394 CG |
274 | &name_attr.attr, |
275 | &actions_attr.attr, | |
276 | NULL | |
277 | }; | |
52ba92f5 | 278 | ATTRIBUTE_GROUPS(irq); |
ecb3f394 CG |
279 | |
280 | static struct kobj_type irq_kobj_type = { | |
281 | .release = irq_kobj_release, | |
282 | .sysfs_ops = &kobj_sysfs_ops, | |
52ba92f5 | 283 | .default_groups = irq_groups, |
ecb3f394 CG |
284 | }; |
285 | ||
286 | static void irq_sysfs_add(int irq, struct irq_desc *desc) | |
287 | { | |
288 | if (irq_kobj_base) { | |
289 | /* | |
290 | * Continue even in case of failure as this is nothing | |
291 | * crucial. | |
292 | */ | |
293 | if (kobject_add(&desc->kobj, irq_kobj_base, "%d", irq)) | |
294 | pr_warn("Failed to add kobject for irq %d\n", irq); | |
295 | } | |
296 | } | |
297 | ||
298 | static int __init irq_sysfs_init(void) | |
299 | { | |
300 | struct irq_desc *desc; | |
301 | int irq; | |
302 | ||
303 | /* Prevent concurrent irq alloc/free */ | |
304 | irq_lock_sparse(); | |
305 | ||
306 | irq_kobj_base = kobject_create_and_add("irq", kernel_kobj); | |
307 | if (!irq_kobj_base) { | |
308 | irq_unlock_sparse(); | |
309 | return -ENOMEM; | |
310 | } | |
311 | ||
312 | /* Add the already allocated interrupts */ | |
313 | for_each_irq_desc(irq, desc) | |
314 | irq_sysfs_add(irq, desc); | |
315 | irq_unlock_sparse(); | |
316 | ||
317 | return 0; | |
318 | } | |
319 | postcore_initcall(irq_sysfs_init); | |
320 | ||
321 | #else /* !CONFIG_SYSFS */ | |
322 | ||
323 | static struct kobj_type irq_kobj_type = { | |
324 | .release = irq_kobj_release, | |
325 | }; | |
326 | ||
327 | static void irq_sysfs_add(int irq, struct irq_desc *desc) {} | |
328 | ||
329 | #endif /* CONFIG_SYSFS */ | |
330 | ||
baa0d233 | 331 | static RADIX_TREE(irq_desc_tree, GFP_KERNEL); |
3795de23 | 332 | |
1f5a5b87 | 333 | static void irq_insert_desc(unsigned int irq, struct irq_desc *desc) |
3795de23 TG |
334 | { |
335 | radix_tree_insert(&irq_desc_tree, irq, desc); | |
336 | } | |
337 | ||
338 | struct irq_desc *irq_to_desc(unsigned int irq) | |
339 | { | |
340 | return radix_tree_lookup(&irq_desc_tree, irq); | |
341 | } | |
3911ff30 | 342 | EXPORT_SYMBOL(irq_to_desc); |
3795de23 | 343 | |
1f5a5b87 TG |
344 | static void delete_irq_desc(unsigned int irq) |
345 | { | |
346 | radix_tree_delete(&irq_desc_tree, irq); | |
347 | } | |
348 | ||
349 | #ifdef CONFIG_SMP | |
350 | static void free_masks(struct irq_desc *desc) | |
351 | { | |
352 | #ifdef CONFIG_GENERIC_PENDING_IRQ | |
353 | free_cpumask_var(desc->pending_mask); | |
354 | #endif | |
9df872fa | 355 | free_cpumask_var(desc->irq_common_data.affinity); |
0d3f5425 TG |
356 | #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK |
357 | free_cpumask_var(desc->irq_common_data.effective_affinity); | |
358 | #endif | |
1f5a5b87 TG |
359 | } |
360 | #else | |
361 | static inline void free_masks(struct irq_desc *desc) { } | |
362 | #endif | |
363 | ||
c291ee62 TG |
364 | void irq_lock_sparse(void) |
365 | { | |
366 | mutex_lock(&sparse_irq_lock); | |
367 | } | |
368 | ||
369 | void irq_unlock_sparse(void) | |
370 | { | |
371 | mutex_unlock(&sparse_irq_lock); | |
372 | } | |
373 | ||
45ddcecb TG |
374 | static struct irq_desc *alloc_desc(int irq, int node, unsigned int flags, |
375 | const struct cpumask *affinity, | |
376 | struct module *owner) | |
1f5a5b87 TG |
377 | { |
378 | struct irq_desc *desc; | |
1f5a5b87 | 379 | |
4ab764c3 | 380 | desc = kzalloc_node(sizeof(*desc), GFP_KERNEL, node); |
1f5a5b87 TG |
381 | if (!desc) |
382 | return NULL; | |
383 | /* allocate based on nr_cpu_ids */ | |
6c9ae009 | 384 | desc->kstat_irqs = alloc_percpu(unsigned int); |
1f5a5b87 TG |
385 | if (!desc->kstat_irqs) |
386 | goto err_desc; | |
387 | ||
4ab764c3 | 388 | if (alloc_masks(desc, node)) |
1f5a5b87 TG |
389 | goto err_kstat; |
390 | ||
391 | raw_spin_lock_init(&desc->lock); | |
392 | lockdep_set_class(&desc->lock, &irq_desc_lock_class); | |
9114014c | 393 | mutex_init(&desc->request_mutex); |
425a5072 | 394 | init_rcu_head(&desc->rcu); |
1f5a5b87 | 395 | |
45ddcecb TG |
396 | desc_set_defaults(irq, desc, node, affinity, owner); |
397 | irqd_set(&desc->irq_data, flags); | |
ecb3f394 | 398 | kobject_init(&desc->kobj, &irq_kobj_type); |
1f5a5b87 TG |
399 | |
400 | return desc; | |
401 | ||
402 | err_kstat: | |
6c9ae009 | 403 | free_percpu(desc->kstat_irqs); |
1f5a5b87 TG |
404 | err_desc: |
405 | kfree(desc); | |
406 | return NULL; | |
407 | } | |
408 | ||
ecb3f394 | 409 | static void irq_kobj_release(struct kobject *kobj) |
425a5072 | 410 | { |
ecb3f394 | 411 | struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj); |
425a5072 TG |
412 | |
413 | free_masks(desc); | |
414 | free_percpu(desc->kstat_irqs); | |
415 | kfree(desc); | |
416 | } | |
417 | ||
ecb3f394 CG |
418 | static void delayed_free_desc(struct rcu_head *rhp) |
419 | { | |
420 | struct irq_desc *desc = container_of(rhp, struct irq_desc, rcu); | |
421 | ||
422 | kobject_put(&desc->kobj); | |
423 | } | |
424 | ||
1f5a5b87 TG |
425 | static void free_desc(unsigned int irq) |
426 | { | |
427 | struct irq_desc *desc = irq_to_desc(irq); | |
1f5a5b87 | 428 | |
087cdfb6 | 429 | irq_remove_debugfs_entry(desc); |
13bfe99e TG |
430 | unregister_irq_proc(irq, desc); |
431 | ||
c291ee62 TG |
432 | /* |
433 | * sparse_irq_lock protects also show_interrupts() and | |
434 | * kstat_irq_usr(). Once we deleted the descriptor from the | |
435 | * sparse tree we can free it. Access in proc will fail to | |
436 | * lookup the descriptor. | |
ecb3f394 CG |
437 | * |
438 | * The sysfs entry must be serialized against a concurrent | |
439 | * irq_sysfs_init() as well. | |
c291ee62 | 440 | */ |
ecb3f394 | 441 | kobject_del(&desc->kobj); |
1f5a5b87 | 442 | delete_irq_desc(irq); |
1f5a5b87 | 443 | |
425a5072 TG |
444 | /* |
445 | * We free the descriptor, masks and stat fields via RCU. That | |
446 | * allows demultiplex interrupts to do rcu based management of | |
447 | * the child interrupts. | |
4a5f4d2f | 448 | * This also allows us to use rcu in kstat_irqs_usr(). |
425a5072 TG |
449 | */ |
450 | call_rcu(&desc->rcu, delayed_free_desc); | |
1f5a5b87 TG |
451 | } |
452 | ||
b6873807 | 453 | static int alloc_descs(unsigned int start, unsigned int cnt, int node, |
bec04037 DL |
454 | const struct irq_affinity_desc *affinity, |
455 | struct module *owner) | |
1f5a5b87 TG |
456 | { |
457 | struct irq_desc *desc; | |
e75eafb9 | 458 | int i; |
45ddcecb | 459 | |
e75eafb9 TG |
460 | /* Validate affinity mask(s) */ |
461 | if (affinity) { | |
12fee4cd | 462 | for (i = 0; i < cnt; i++) { |
bec04037 | 463 | if (cpumask_empty(&affinity[i].mask)) |
e75eafb9 TG |
464 | return -EINVAL; |
465 | } | |
466 | } | |
45ddcecb | 467 | |
1f5a5b87 | 468 | for (i = 0; i < cnt; i++) { |
bec04037 | 469 | const struct cpumask *mask = NULL; |
c410abbb | 470 | unsigned int flags = 0; |
bec04037 | 471 | |
45ddcecb | 472 | if (affinity) { |
c410abbb DL |
473 | if (affinity->is_managed) { |
474 | flags = IRQD_AFFINITY_MANAGED | | |
475 | IRQD_MANAGED_SHUTDOWN; | |
476 | } | |
bec04037 | 477 | mask = &affinity->mask; |
c410abbb | 478 | node = cpu_to_node(cpumask_first(mask)); |
e75eafb9 | 479 | affinity++; |
45ddcecb | 480 | } |
c410abbb | 481 | |
45ddcecb | 482 | desc = alloc_desc(start + i, node, flags, mask, owner); |
1f5a5b87 TG |
483 | if (!desc) |
484 | goto err; | |
1f5a5b87 | 485 | irq_insert_desc(start + i, desc); |
ecb3f394 | 486 | irq_sysfs_add(start + i, desc); |
e0b47794 | 487 | irq_add_debugfs_entry(start + i, desc); |
1f5a5b87 | 488 | } |
12ac1d0f | 489 | bitmap_set(allocated_irqs, start, cnt); |
1f5a5b87 TG |
490 | return start; |
491 | ||
492 | err: | |
493 | for (i--; i >= 0; i--) | |
494 | free_desc(start + i); | |
1f5a5b87 TG |
495 | return -ENOMEM; |
496 | } | |
497 | ||
ed4dea6e | 498 | static int irq_expand_nr_irqs(unsigned int nr) |
e7bcecb7 | 499 | { |
ed4dea6e | 500 | if (nr > IRQ_BITMAP_BITS) |
e7bcecb7 | 501 | return -ENOMEM; |
ed4dea6e | 502 | nr_irqs = nr; |
e7bcecb7 TG |
503 | return 0; |
504 | } | |
505 | ||
3795de23 TG |
506 | int __init early_irq_init(void) |
507 | { | |
b683de2b | 508 | int i, initcnt, node = first_online_node; |
3795de23 | 509 | struct irq_desc *desc; |
3795de23 TG |
510 | |
511 | init_irq_default_affinity(); | |
512 | ||
b683de2b TG |
513 | /* Let arch update nr_irqs and return the nr of preallocated irqs */ |
514 | initcnt = arch_probe_nr_irqs(); | |
5a29ef22 VL |
515 | printk(KERN_INFO "NR_IRQS: %d, nr_irqs: %d, preallocated irqs: %d\n", |
516 | NR_IRQS, nr_irqs, initcnt); | |
3795de23 | 517 | |
c1ee6264 TG |
518 | if (WARN_ON(nr_irqs > IRQ_BITMAP_BITS)) |
519 | nr_irqs = IRQ_BITMAP_BITS; | |
520 | ||
521 | if (WARN_ON(initcnt > IRQ_BITMAP_BITS)) | |
522 | initcnt = IRQ_BITMAP_BITS; | |
523 | ||
524 | if (initcnt > nr_irqs) | |
525 | nr_irqs = initcnt; | |
526 | ||
b683de2b | 527 | for (i = 0; i < initcnt; i++) { |
45ddcecb | 528 | desc = alloc_desc(i, node, 0, NULL, NULL); |
aa99ec0f TG |
529 | set_bit(i, allocated_irqs); |
530 | irq_insert_desc(i, desc); | |
3795de23 | 531 | } |
3795de23 TG |
532 | return arch_early_irq_init(); |
533 | } | |
534 | ||
3795de23 TG |
535 | #else /* !CONFIG_SPARSE_IRQ */ |
536 | ||
537 | struct irq_desc irq_desc[NR_IRQS] __cacheline_aligned_in_smp = { | |
538 | [0 ... NR_IRQS-1] = { | |
3795de23 TG |
539 | .handle_irq = handle_bad_irq, |
540 | .depth = 1, | |
541 | .lock = __RAW_SPIN_LOCK_UNLOCKED(irq_desc->lock), | |
542 | } | |
543 | }; | |
544 | ||
3795de23 TG |
545 | int __init early_irq_init(void) |
546 | { | |
aa99ec0f | 547 | int count, i, node = first_online_node; |
3795de23 | 548 | struct irq_desc *desc; |
3795de23 TG |
549 | |
550 | init_irq_default_affinity(); | |
551 | ||
5a29ef22 | 552 | printk(KERN_INFO "NR_IRQS: %d\n", NR_IRQS); |
3795de23 TG |
553 | |
554 | desc = irq_desc; | |
555 | count = ARRAY_SIZE(irq_desc); | |
556 | ||
557 | for (i = 0; i < count; i++) { | |
6c9ae009 | 558 | desc[i].kstat_irqs = alloc_percpu(unsigned int); |
4ab764c3 | 559 | alloc_masks(&desc[i], node); |
e7fbad30 | 560 | raw_spin_lock_init(&desc[i].lock); |
154cd387 | 561 | lockdep_set_class(&desc[i].lock, &irq_desc_lock_class); |
e8458e7a | 562 | mutex_init(&desc[i].request_mutex); |
45ddcecb | 563 | desc_set_defaults(i, &desc[i], node, NULL, NULL); |
3795de23 TG |
564 | } |
565 | return arch_early_irq_init(); | |
566 | } | |
567 | ||
568 | struct irq_desc *irq_to_desc(unsigned int irq) | |
569 | { | |
570 | return (irq < NR_IRQS) ? irq_desc + irq : NULL; | |
571 | } | |
2c45aada | 572 | EXPORT_SYMBOL(irq_to_desc); |
3795de23 | 573 | |
1f5a5b87 TG |
574 | static void free_desc(unsigned int irq) |
575 | { | |
d8179bc0 TG |
576 | struct irq_desc *desc = irq_to_desc(irq); |
577 | unsigned long flags; | |
578 | ||
579 | raw_spin_lock_irqsave(&desc->lock, flags); | |
45ddcecb | 580 | desc_set_defaults(irq, desc, irq_desc_get_node(desc), NULL, NULL); |
d8179bc0 | 581 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1f5a5b87 TG |
582 | } |
583 | ||
b6873807 | 584 | static inline int alloc_descs(unsigned int start, unsigned int cnt, int node, |
bec04037 | 585 | const struct irq_affinity_desc *affinity, |
b6873807 | 586 | struct module *owner) |
1f5a5b87 | 587 | { |
b6873807 SAS |
588 | u32 i; |
589 | ||
590 | for (i = 0; i < cnt; i++) { | |
591 | struct irq_desc *desc = irq_to_desc(start + i); | |
592 | ||
593 | desc->owner = owner; | |
594 | } | |
12ac1d0f | 595 | bitmap_set(allocated_irqs, start, cnt); |
1f5a5b87 TG |
596 | return start; |
597 | } | |
e7bcecb7 | 598 | |
ed4dea6e | 599 | static int irq_expand_nr_irqs(unsigned int nr) |
e7bcecb7 TG |
600 | { |
601 | return -ENOMEM; | |
602 | } | |
603 | ||
f63b6a05 TG |
604 | void irq_mark_irq(unsigned int irq) |
605 | { | |
606 | mutex_lock(&sparse_irq_lock); | |
607 | bitmap_set(allocated_irqs, irq, 1); | |
608 | mutex_unlock(&sparse_irq_lock); | |
609 | } | |
610 | ||
c940e01c TG |
611 | #ifdef CONFIG_GENERIC_IRQ_LEGACY |
612 | void irq_init_desc(unsigned int irq) | |
613 | { | |
d8179bc0 | 614 | free_desc(irq); |
c940e01c TG |
615 | } |
616 | #endif | |
617 | ||
3795de23 TG |
618 | #endif /* !CONFIG_SPARSE_IRQ */ |
619 | ||
fe12bc2c TG |
620 | /** |
621 | * generic_handle_irq - Invoke the handler for a particular irq | |
622 | * @irq: The irq number to handle | |
623 | * | |
624 | */ | |
625 | int generic_handle_irq(unsigned int irq) | |
626 | { | |
627 | struct irq_desc *desc = irq_to_desc(irq); | |
628 | ||
629 | if (!desc) | |
630 | return -EINVAL; | |
bd0b9ac4 | 631 | generic_handle_irq_desc(desc); |
fe12bc2c TG |
632 | return 0; |
633 | } | |
edf76f83 | 634 | EXPORT_SYMBOL_GPL(generic_handle_irq); |
fe12bc2c | 635 | |
76ba59f8 MZ |
636 | #ifdef CONFIG_HANDLE_DOMAIN_IRQ |
637 | /** | |
638 | * __handle_domain_irq - Invoke the handler for a HW irq belonging to a domain | |
639 | * @domain: The domain where to perform the lookup | |
640 | * @hwirq: The HW irq number to convert to a logical one | |
641 | * @lookup: Whether to perform the domain lookup or not | |
642 | * @regs: Register file coming from the low-level handling code | |
643 | * | |
644 | * Returns: 0 on success, or -EINVAL if conversion has failed | |
645 | */ | |
646 | int __handle_domain_irq(struct irq_domain *domain, unsigned int hwirq, | |
647 | bool lookup, struct pt_regs *regs) | |
648 | { | |
649 | struct pt_regs *old_regs = set_irq_regs(regs); | |
650 | unsigned int irq = hwirq; | |
651 | int ret = 0; | |
652 | ||
653 | irq_enter(); | |
654 | ||
655 | #ifdef CONFIG_IRQ_DOMAIN | |
656 | if (lookup) | |
657 | irq = irq_find_mapping(domain, hwirq); | |
658 | #endif | |
659 | ||
660 | /* | |
661 | * Some hardware gives randomly wrong interrupts. Rather | |
662 | * than crashing, do something sensible. | |
663 | */ | |
664 | if (unlikely(!irq || irq >= nr_irqs)) { | |
665 | ack_bad_irq(irq); | |
666 | ret = -EINVAL; | |
667 | } else { | |
668 | generic_handle_irq(irq); | |
669 | } | |
670 | ||
671 | irq_exit(); | |
672 | set_irq_regs(old_regs); | |
673 | return ret; | |
674 | } | |
6e4933a0 JT |
675 | |
676 | #ifdef CONFIG_IRQ_DOMAIN | |
677 | /** | |
678 | * handle_domain_nmi - Invoke the handler for a HW irq belonging to a domain | |
679 | * @domain: The domain where to perform the lookup | |
680 | * @hwirq: The HW irq number to convert to a logical one | |
681 | * @regs: Register file coming from the low-level handling code | |
682 | * | |
683 | * Returns: 0 on success, or -EINVAL if conversion has failed | |
684 | */ | |
685 | int handle_domain_nmi(struct irq_domain *domain, unsigned int hwirq, | |
686 | struct pt_regs *regs) | |
687 | { | |
688 | struct pt_regs *old_regs = set_irq_regs(regs); | |
689 | unsigned int irq; | |
690 | int ret = 0; | |
691 | ||
692 | nmi_enter(); | |
693 | ||
694 | irq = irq_find_mapping(domain, hwirq); | |
695 | ||
696 | /* | |
697 | * ack_bad_irq is not NMI-safe, just report | |
698 | * an invalid interrupt. | |
699 | */ | |
700 | if (likely(irq)) | |
701 | generic_handle_irq(irq); | |
702 | else | |
703 | ret = -EINVAL; | |
704 | ||
705 | nmi_exit(); | |
706 | set_irq_regs(old_regs); | |
707 | return ret; | |
708 | } | |
709 | #endif | |
76ba59f8 MZ |
710 | #endif |
711 | ||
1f5a5b87 TG |
712 | /* Dynamic interrupt handling */ |
713 | ||
714 | /** | |
715 | * irq_free_descs - free irq descriptors | |
716 | * @from: Start of descriptor range | |
717 | * @cnt: Number of consecutive irqs to free | |
718 | */ | |
719 | void irq_free_descs(unsigned int from, unsigned int cnt) | |
720 | { | |
1f5a5b87 TG |
721 | int i; |
722 | ||
723 | if (from >= nr_irqs || (from + cnt) > nr_irqs) | |
724 | return; | |
725 | ||
12ac1d0f | 726 | mutex_lock(&sparse_irq_lock); |
1f5a5b87 TG |
727 | for (i = 0; i < cnt; i++) |
728 | free_desc(from + i); | |
729 | ||
1f5a5b87 | 730 | bitmap_clear(allocated_irqs, from, cnt); |
a05a900a | 731 | mutex_unlock(&sparse_irq_lock); |
1f5a5b87 | 732 | } |
edf76f83 | 733 | EXPORT_SYMBOL_GPL(irq_free_descs); |
1f5a5b87 TG |
734 | |
735 | /** | |
736 | * irq_alloc_descs - allocate and initialize a range of irq descriptors | |
737 | * @irq: Allocate for specific irq number if irq >= 0 | |
738 | * @from: Start the search from this irq number | |
739 | * @cnt: Number of consecutive irqs to allocate. | |
740 | * @node: Preferred node on which the irq descriptor should be allocated | |
d522a0d1 | 741 | * @owner: Owning module (can be NULL) |
e75eafb9 TG |
742 | * @affinity: Optional pointer to an affinity mask array of size @cnt which |
743 | * hints where the irq descriptors should be allocated and which | |
744 | * default affinities to use | |
1f5a5b87 TG |
745 | * |
746 | * Returns the first irq number or error code | |
747 | */ | |
748 | int __ref | |
b6873807 | 749 | __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, |
bec04037 | 750 | struct module *owner, const struct irq_affinity_desc *affinity) |
1f5a5b87 | 751 | { |
1f5a5b87 TG |
752 | int start, ret; |
753 | ||
754 | if (!cnt) | |
755 | return -EINVAL; | |
756 | ||
c5182b88 MB |
757 | if (irq >= 0) { |
758 | if (from > irq) | |
759 | return -EINVAL; | |
760 | from = irq; | |
62a08ae2 TG |
761 | } else { |
762 | /* | |
763 | * For interrupts which are freely allocated the | |
764 | * architecture can force a lower bound to the @from | |
765 | * argument. x86 uses this to exclude the GSI space. | |
766 | */ | |
767 | from = arch_dynirq_lower_bound(from); | |
c5182b88 MB |
768 | } |
769 | ||
a05a900a | 770 | mutex_lock(&sparse_irq_lock); |
1f5a5b87 | 771 | |
ed4dea6e YL |
772 | start = bitmap_find_next_zero_area(allocated_irqs, IRQ_BITMAP_BITS, |
773 | from, cnt, 0); | |
1f5a5b87 TG |
774 | ret = -EEXIST; |
775 | if (irq >=0 && start != irq) | |
12ac1d0f | 776 | goto unlock; |
1f5a5b87 | 777 | |
ed4dea6e YL |
778 | if (start + cnt > nr_irqs) { |
779 | ret = irq_expand_nr_irqs(start + cnt); | |
e7bcecb7 | 780 | if (ret) |
12ac1d0f | 781 | goto unlock; |
e7bcecb7 | 782 | } |
12ac1d0f TG |
783 | ret = alloc_descs(start, cnt, node, affinity, owner); |
784 | unlock: | |
a05a900a | 785 | mutex_unlock(&sparse_irq_lock); |
1f5a5b87 TG |
786 | return ret; |
787 | } | |
b6873807 | 788 | EXPORT_SYMBOL_GPL(__irq_alloc_descs); |
1f5a5b87 | 789 | |
7b6ef126 TG |
790 | #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ |
791 | /** | |
792 | * irq_alloc_hwirqs - Allocate an irq descriptor and initialize the hardware | |
793 | * @cnt: number of interrupts to allocate | |
794 | * @node: node on which to allocate | |
795 | * | |
796 | * Returns an interrupt number > 0 or 0, if the allocation fails. | |
797 | */ | |
798 | unsigned int irq_alloc_hwirqs(int cnt, int node) | |
799 | { | |
06ee6d57 | 800 | int i, irq = __irq_alloc_descs(-1, 0, cnt, node, NULL, NULL); |
7b6ef126 TG |
801 | |
802 | if (irq < 0) | |
803 | return 0; | |
804 | ||
805 | for (i = irq; cnt > 0; i++, cnt--) { | |
806 | if (arch_setup_hwirq(i, node)) | |
807 | goto err; | |
808 | irq_clear_status_flags(i, _IRQ_NOREQUEST); | |
809 | } | |
810 | return irq; | |
811 | ||
812 | err: | |
813 | for (i--; i >= irq; i--) { | |
814 | irq_set_status_flags(i, _IRQ_NOREQUEST | _IRQ_NOPROBE); | |
815 | arch_teardown_hwirq(i); | |
816 | } | |
817 | irq_free_descs(irq, cnt); | |
818 | return 0; | |
819 | } | |
820 | EXPORT_SYMBOL_GPL(irq_alloc_hwirqs); | |
821 | ||
822 | /** | |
823 | * irq_free_hwirqs - Free irq descriptor and cleanup the hardware | |
824 | * @from: Free from irq number | |
825 | * @cnt: number of interrupts to free | |
826 | * | |
827 | */ | |
828 | void irq_free_hwirqs(unsigned int from, int cnt) | |
829 | { | |
8844aad8 | 830 | int i, j; |
7b6ef126 | 831 | |
8844aad8 | 832 | for (i = from, j = cnt; j > 0; i++, j--) { |
7b6ef126 TG |
833 | irq_set_status_flags(i, _IRQ_NOREQUEST | _IRQ_NOPROBE); |
834 | arch_teardown_hwirq(i); | |
835 | } | |
836 | irq_free_descs(from, cnt); | |
837 | } | |
838 | EXPORT_SYMBOL_GPL(irq_free_hwirqs); | |
839 | #endif | |
840 | ||
a98d24b7 TG |
841 | /** |
842 | * irq_get_next_irq - get next allocated irq number | |
843 | * @offset: where to start the search | |
844 | * | |
845 | * Returns next irq number after offset or nr_irqs if none is found. | |
846 | */ | |
847 | unsigned int irq_get_next_irq(unsigned int offset) | |
848 | { | |
849 | return find_next_bit(allocated_irqs, nr_irqs, offset); | |
850 | } | |
851 | ||
d5eb4ad2 | 852 | struct irq_desc * |
31d9d9b6 MZ |
853 | __irq_get_desc_lock(unsigned int irq, unsigned long *flags, bool bus, |
854 | unsigned int check) | |
d5eb4ad2 TG |
855 | { |
856 | struct irq_desc *desc = irq_to_desc(irq); | |
857 | ||
858 | if (desc) { | |
31d9d9b6 MZ |
859 | if (check & _IRQ_DESC_CHECK) { |
860 | if ((check & _IRQ_DESC_PERCPU) && | |
861 | !irq_settings_is_per_cpu_devid(desc)) | |
862 | return NULL; | |
863 | ||
864 | if (!(check & _IRQ_DESC_PERCPU) && | |
865 | irq_settings_is_per_cpu_devid(desc)) | |
866 | return NULL; | |
867 | } | |
868 | ||
d5eb4ad2 TG |
869 | if (bus) |
870 | chip_bus_lock(desc); | |
871 | raw_spin_lock_irqsave(&desc->lock, *flags); | |
872 | } | |
873 | return desc; | |
874 | } | |
875 | ||
876 | void __irq_put_desc_unlock(struct irq_desc *desc, unsigned long flags, bool bus) | |
877 | { | |
878 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
879 | if (bus) | |
880 | chip_bus_sync_unlock(desc); | |
881 | } | |
882 | ||
222df54f MZ |
883 | int irq_set_percpu_devid_partition(unsigned int irq, |
884 | const struct cpumask *affinity) | |
31d9d9b6 MZ |
885 | { |
886 | struct irq_desc *desc = irq_to_desc(irq); | |
887 | ||
888 | if (!desc) | |
889 | return -EINVAL; | |
890 | ||
891 | if (desc->percpu_enabled) | |
892 | return -EINVAL; | |
893 | ||
894 | desc->percpu_enabled = kzalloc(sizeof(*desc->percpu_enabled), GFP_KERNEL); | |
895 | ||
896 | if (!desc->percpu_enabled) | |
897 | return -ENOMEM; | |
898 | ||
222df54f MZ |
899 | if (affinity) |
900 | desc->percpu_affinity = affinity; | |
901 | else | |
902 | desc->percpu_affinity = cpu_possible_mask; | |
903 | ||
31d9d9b6 MZ |
904 | irq_set_percpu_devid_flags(irq); |
905 | return 0; | |
906 | } | |
907 | ||
222df54f MZ |
908 | int irq_set_percpu_devid(unsigned int irq) |
909 | { | |
910 | return irq_set_percpu_devid_partition(irq, NULL); | |
911 | } | |
912 | ||
913 | int irq_get_percpu_devid_partition(unsigned int irq, struct cpumask *affinity) | |
914 | { | |
915 | struct irq_desc *desc = irq_to_desc(irq); | |
916 | ||
917 | if (!desc || !desc->percpu_enabled) | |
918 | return -EINVAL; | |
919 | ||
920 | if (affinity) | |
921 | cpumask_copy(affinity, desc->percpu_affinity); | |
922 | ||
923 | return 0; | |
924 | } | |
5ffeb050 | 925 | EXPORT_SYMBOL_GPL(irq_get_percpu_devid_partition); |
222df54f | 926 | |
792d0018 TG |
927 | void kstat_incr_irq_this_cpu(unsigned int irq) |
928 | { | |
b51bf95c | 929 | kstat_incr_irqs_this_cpu(irq_to_desc(irq)); |
792d0018 TG |
930 | } |
931 | ||
c291ee62 TG |
932 | /** |
933 | * kstat_irqs_cpu - Get the statistics for an interrupt on a cpu | |
934 | * @irq: The interrupt number | |
935 | * @cpu: The cpu number | |
936 | * | |
937 | * Returns the sum of interrupt counts on @cpu since boot for | |
938 | * @irq. The caller must ensure that the interrupt is not removed | |
939 | * concurrently. | |
940 | */ | |
3795de23 TG |
941 | unsigned int kstat_irqs_cpu(unsigned int irq, int cpu) |
942 | { | |
943 | struct irq_desc *desc = irq_to_desc(irq); | |
6c9ae009 ED |
944 | |
945 | return desc && desc->kstat_irqs ? | |
946 | *per_cpu_ptr(desc->kstat_irqs, cpu) : 0; | |
3795de23 | 947 | } |
478735e3 | 948 | |
c291ee62 TG |
949 | /** |
950 | * kstat_irqs - Get the statistics for an interrupt | |
951 | * @irq: The interrupt number | |
952 | * | |
953 | * Returns the sum of interrupt counts on all cpus since boot for | |
954 | * @irq. The caller must ensure that the interrupt is not removed | |
955 | * concurrently. | |
956 | */ | |
478735e3 KH |
957 | unsigned int kstat_irqs(unsigned int irq) |
958 | { | |
959 | struct irq_desc *desc = irq_to_desc(irq); | |
5e9662fa | 960 | unsigned int sum = 0; |
1136b072 | 961 | int cpu; |
478735e3 | 962 | |
6c9ae009 | 963 | if (!desc || !desc->kstat_irqs) |
478735e3 | 964 | return 0; |
1136b072 TG |
965 | if (!irq_settings_is_per_cpu_devid(desc) && |
966 | !irq_settings_is_per_cpu(desc)) | |
967 | return desc->tot_count; | |
968 | ||
478735e3 | 969 | for_each_possible_cpu(cpu) |
6c9ae009 | 970 | sum += *per_cpu_ptr(desc->kstat_irqs, cpu); |
478735e3 KH |
971 | return sum; |
972 | } | |
c291ee62 TG |
973 | |
974 | /** | |
975 | * kstat_irqs_usr - Get the statistics for an interrupt | |
976 | * @irq: The interrupt number | |
977 | * | |
4a5f4d2f ED |
978 | * Returns the sum of interrupt counts on all cpus since boot for @irq. |
979 | * Contrary to kstat_irqs() this can be called from any context. | |
980 | * It uses rcu since a concurrent removal of an interrupt descriptor is | |
981 | * observing an rcu grace period before delayed_free_desc()/irq_kobj_release(). | |
c291ee62 TG |
982 | */ |
983 | unsigned int kstat_irqs_usr(unsigned int irq) | |
984 | { | |
7df0b278 | 985 | unsigned int sum; |
c291ee62 | 986 | |
4a5f4d2f | 987 | rcu_read_lock(); |
c291ee62 | 988 | sum = kstat_irqs(irq); |
4a5f4d2f | 989 | rcu_read_unlock(); |
c291ee62 TG |
990 | return sum; |
991 | } |