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genirq/irqdomain: Add map counter
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CommitLineData
3795de23
TG
1/*
2 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
3 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
4 *
5 * This file contains the interrupt descriptor management code
6 *
7 * Detailed information is available in Documentation/DocBook/genericirq
8 *
9 */
10#include <linux/irq.h>
11#include <linux/slab.h>
ec53cf23 12#include <linux/export.h>
3795de23
TG
13#include <linux/interrupt.h>
14#include <linux/kernel_stat.h>
15#include <linux/radix-tree.h>
1f5a5b87 16#include <linux/bitmap.h>
76ba59f8 17#include <linux/irqdomain.h>
ecb3f394 18#include <linux/sysfs.h>
3795de23
TG
19
20#include "internals.h"
21
22/*
23 * lockdep: we want to handle all irq_desc locks as a single lock-class:
24 */
78f90d91 25static struct lock_class_key irq_desc_lock_class;
3795de23 26
fe051434 27#if defined(CONFIG_SMP)
fbf19803
TG
28static int __init irq_affinity_setup(char *str)
29{
30 zalloc_cpumask_var(&irq_default_affinity, GFP_NOWAIT);
31 cpulist_parse(str, irq_default_affinity);
32 /*
33 * Set at least the boot cpu. We don't want to end up with
34 * bugreports caused by random comandline masks
35 */
36 cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
37 return 1;
38}
39__setup("irqaffinity=", irq_affinity_setup);
40
3795de23
TG
41static void __init init_irq_default_affinity(void)
42{
fbf19803
TG
43#ifdef CONFIG_CPUMASK_OFFSTACK
44 if (!irq_default_affinity)
45 zalloc_cpumask_var(&irq_default_affinity, GFP_NOWAIT);
46#endif
47 if (cpumask_empty(irq_default_affinity))
48 cpumask_setall(irq_default_affinity);
3795de23
TG
49}
50#else
51static void __init init_irq_default_affinity(void)
52{
53}
54#endif
55
1f5a5b87
TG
56#ifdef CONFIG_SMP
57static int alloc_masks(struct irq_desc *desc, gfp_t gfp, int node)
58{
9df872fa
JL
59 if (!zalloc_cpumask_var_node(&desc->irq_common_data.affinity,
60 gfp, node))
1f5a5b87
TG
61 return -ENOMEM;
62
63#ifdef CONFIG_GENERIC_PENDING_IRQ
64 if (!zalloc_cpumask_var_node(&desc->pending_mask, gfp, node)) {
9df872fa 65 free_cpumask_var(desc->irq_common_data.affinity);
1f5a5b87
TG
66 return -ENOMEM;
67 }
68#endif
69 return 0;
70}
71
45ddcecb
TG
72static void desc_smp_init(struct irq_desc *desc, int node,
73 const struct cpumask *affinity)
1f5a5b87 74{
45ddcecb
TG
75 if (!affinity)
76 affinity = irq_default_affinity;
77 cpumask_copy(desc->irq_common_data.affinity, affinity);
78
b7b29338
TG
79#ifdef CONFIG_GENERIC_PENDING_IRQ
80 cpumask_clear(desc->pending_mask);
81#endif
449e9cae
JL
82#ifdef CONFIG_NUMA
83 desc->irq_common_data.node = node;
84#endif
b7b29338
TG
85}
86
1f5a5b87
TG
87#else
88static inline int
89alloc_masks(struct irq_desc *desc, gfp_t gfp, int node) { return 0; }
45ddcecb
TG
90static inline void
91desc_smp_init(struct irq_desc *desc, int node, const struct cpumask *affinity) { }
1f5a5b87
TG
92#endif
93
b6873807 94static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node,
45ddcecb 95 const struct cpumask *affinity, struct module *owner)
1f5a5b87 96{
6c9ae009
ED
97 int cpu;
98
af7080e0 99 desc->irq_common_data.handler_data = NULL;
b237721c 100 desc->irq_common_data.msi_desc = NULL;
af7080e0 101
0d0b4c86 102 desc->irq_data.common = &desc->irq_common_data;
1f5a5b87
TG
103 desc->irq_data.irq = irq;
104 desc->irq_data.chip = &no_irq_chip;
105 desc->irq_data.chip_data = NULL;
f9e4989e 106 irq_settings_clr_and_set(desc, ~0, _IRQ_DEFAULT_INIT_FLAGS);
801a0e9a 107 irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
1f5a5b87
TG
108 desc->handle_irq = handle_bad_irq;
109 desc->depth = 1;
b7b29338
TG
110 desc->irq_count = 0;
111 desc->irqs_unhandled = 0;
1f5a5b87 112 desc->name = NULL;
b6873807 113 desc->owner = owner;
6c9ae009
ED
114 for_each_possible_cpu(cpu)
115 *per_cpu_ptr(desc->kstat_irqs, cpu) = 0;
45ddcecb 116 desc_smp_init(desc, node, affinity);
1f5a5b87
TG
117}
118
3795de23
TG
119int nr_irqs = NR_IRQS;
120EXPORT_SYMBOL_GPL(nr_irqs);
121
a05a900a 122static DEFINE_MUTEX(sparse_irq_lock);
c1ee6264 123static DECLARE_BITMAP(allocated_irqs, IRQ_BITMAP_BITS);
1f5a5b87 124
3795de23
TG
125#ifdef CONFIG_SPARSE_IRQ
126
ecb3f394
CG
127static void irq_kobj_release(struct kobject *kobj);
128
129#ifdef CONFIG_SYSFS
130static struct kobject *irq_kobj_base;
131
132#define IRQ_ATTR_RO(_name) \
133static struct kobj_attribute _name##_attr = __ATTR_RO(_name)
134
135static ssize_t per_cpu_count_show(struct kobject *kobj,
136 struct kobj_attribute *attr, char *buf)
137{
138 struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj);
139 int cpu, irq = desc->irq_data.irq;
140 ssize_t ret = 0;
141 char *p = "";
142
143 for_each_possible_cpu(cpu) {
144 unsigned int c = kstat_irqs_cpu(irq, cpu);
145
146 ret += scnprintf(buf + ret, PAGE_SIZE - ret, "%s%u", p, c);
147 p = ",";
148 }
149
150 ret += scnprintf(buf + ret, PAGE_SIZE - ret, "\n");
151 return ret;
152}
153IRQ_ATTR_RO(per_cpu_count);
154
155static ssize_t chip_name_show(struct kobject *kobj,
156 struct kobj_attribute *attr, char *buf)
157{
158 struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj);
159 ssize_t ret = 0;
160
161 raw_spin_lock_irq(&desc->lock);
162 if (desc->irq_data.chip && desc->irq_data.chip->name) {
163 ret = scnprintf(buf, PAGE_SIZE, "%s\n",
164 desc->irq_data.chip->name);
165 }
166 raw_spin_unlock_irq(&desc->lock);
167
168 return ret;
169}
170IRQ_ATTR_RO(chip_name);
171
172static ssize_t hwirq_show(struct kobject *kobj,
173 struct kobj_attribute *attr, char *buf)
174{
175 struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj);
176 ssize_t ret = 0;
177
178 raw_spin_lock_irq(&desc->lock);
179 if (desc->irq_data.domain)
180 ret = sprintf(buf, "%d\n", (int)desc->irq_data.hwirq);
181 raw_spin_unlock_irq(&desc->lock);
182
183 return ret;
184}
185IRQ_ATTR_RO(hwirq);
186
187static ssize_t type_show(struct kobject *kobj,
188 struct kobj_attribute *attr, char *buf)
189{
190 struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj);
191 ssize_t ret = 0;
192
193 raw_spin_lock_irq(&desc->lock);
194 ret = sprintf(buf, "%s\n",
195 irqd_is_level_type(&desc->irq_data) ? "level" : "edge");
196 raw_spin_unlock_irq(&desc->lock);
197
198 return ret;
199
200}
201IRQ_ATTR_RO(type);
202
203static ssize_t name_show(struct kobject *kobj,
204 struct kobj_attribute *attr, char *buf)
205{
206 struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj);
207 ssize_t ret = 0;
208
209 raw_spin_lock_irq(&desc->lock);
210 if (desc->name)
211 ret = scnprintf(buf, PAGE_SIZE, "%s\n", desc->name);
212 raw_spin_unlock_irq(&desc->lock);
213
214 return ret;
215}
216IRQ_ATTR_RO(name);
217
218static ssize_t actions_show(struct kobject *kobj,
219 struct kobj_attribute *attr, char *buf)
220{
221 struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj);
222 struct irqaction *action;
223 ssize_t ret = 0;
224 char *p = "";
225
226 raw_spin_lock_irq(&desc->lock);
227 for (action = desc->action; action != NULL; action = action->next) {
228 ret += scnprintf(buf + ret, PAGE_SIZE - ret, "%s%s",
229 p, action->name);
230 p = ",";
231 }
232 raw_spin_unlock_irq(&desc->lock);
233
234 if (ret)
235 ret += scnprintf(buf + ret, PAGE_SIZE - ret, "\n");
236
237 return ret;
238}
239IRQ_ATTR_RO(actions);
240
241static struct attribute *irq_attrs[] = {
242 &per_cpu_count_attr.attr,
243 &chip_name_attr.attr,
244 &hwirq_attr.attr,
245 &type_attr.attr,
246 &name_attr.attr,
247 &actions_attr.attr,
248 NULL
249};
250
251static struct kobj_type irq_kobj_type = {
252 .release = irq_kobj_release,
253 .sysfs_ops = &kobj_sysfs_ops,
254 .default_attrs = irq_attrs,
255};
256
257static void irq_sysfs_add(int irq, struct irq_desc *desc)
258{
259 if (irq_kobj_base) {
260 /*
261 * Continue even in case of failure as this is nothing
262 * crucial.
263 */
264 if (kobject_add(&desc->kobj, irq_kobj_base, "%d", irq))
265 pr_warn("Failed to add kobject for irq %d\n", irq);
266 }
267}
268
269static int __init irq_sysfs_init(void)
270{
271 struct irq_desc *desc;
272 int irq;
273
274 /* Prevent concurrent irq alloc/free */
275 irq_lock_sparse();
276
277 irq_kobj_base = kobject_create_and_add("irq", kernel_kobj);
278 if (!irq_kobj_base) {
279 irq_unlock_sparse();
280 return -ENOMEM;
281 }
282
283 /* Add the already allocated interrupts */
284 for_each_irq_desc(irq, desc)
285 irq_sysfs_add(irq, desc);
286 irq_unlock_sparse();
287
288 return 0;
289}
290postcore_initcall(irq_sysfs_init);
291
292#else /* !CONFIG_SYSFS */
293
294static struct kobj_type irq_kobj_type = {
295 .release = irq_kobj_release,
296};
297
298static void irq_sysfs_add(int irq, struct irq_desc *desc) {}
299
300#endif /* CONFIG_SYSFS */
301
baa0d233 302static RADIX_TREE(irq_desc_tree, GFP_KERNEL);
3795de23 303
1f5a5b87 304static void irq_insert_desc(unsigned int irq, struct irq_desc *desc)
3795de23
TG
305{
306 radix_tree_insert(&irq_desc_tree, irq, desc);
307}
308
309struct irq_desc *irq_to_desc(unsigned int irq)
310{
311 return radix_tree_lookup(&irq_desc_tree, irq);
312}
3911ff30 313EXPORT_SYMBOL(irq_to_desc);
3795de23 314
1f5a5b87
TG
315static void delete_irq_desc(unsigned int irq)
316{
317 radix_tree_delete(&irq_desc_tree, irq);
318}
319
320#ifdef CONFIG_SMP
321static void free_masks(struct irq_desc *desc)
322{
323#ifdef CONFIG_GENERIC_PENDING_IRQ
324 free_cpumask_var(desc->pending_mask);
325#endif
9df872fa 326 free_cpumask_var(desc->irq_common_data.affinity);
1f5a5b87
TG
327}
328#else
329static inline void free_masks(struct irq_desc *desc) { }
330#endif
331
c291ee62
TG
332void irq_lock_sparse(void)
333{
334 mutex_lock(&sparse_irq_lock);
335}
336
337void irq_unlock_sparse(void)
338{
339 mutex_unlock(&sparse_irq_lock);
340}
341
45ddcecb
TG
342static struct irq_desc *alloc_desc(int irq, int node, unsigned int flags,
343 const struct cpumask *affinity,
344 struct module *owner)
1f5a5b87
TG
345{
346 struct irq_desc *desc;
baa0d233 347 gfp_t gfp = GFP_KERNEL;
1f5a5b87
TG
348
349 desc = kzalloc_node(sizeof(*desc), gfp, node);
350 if (!desc)
351 return NULL;
352 /* allocate based on nr_cpu_ids */
6c9ae009 353 desc->kstat_irqs = alloc_percpu(unsigned int);
1f5a5b87
TG
354 if (!desc->kstat_irqs)
355 goto err_desc;
356
357 if (alloc_masks(desc, gfp, node))
358 goto err_kstat;
359
360 raw_spin_lock_init(&desc->lock);
361 lockdep_set_class(&desc->lock, &irq_desc_lock_class);
425a5072 362 init_rcu_head(&desc->rcu);
1f5a5b87 363
45ddcecb
TG
364 desc_set_defaults(irq, desc, node, affinity, owner);
365 irqd_set(&desc->irq_data, flags);
ecb3f394 366 kobject_init(&desc->kobj, &irq_kobj_type);
1f5a5b87
TG
367
368 return desc;
369
370err_kstat:
6c9ae009 371 free_percpu(desc->kstat_irqs);
1f5a5b87
TG
372err_desc:
373 kfree(desc);
374 return NULL;
375}
376
ecb3f394 377static void irq_kobj_release(struct kobject *kobj)
425a5072 378{
ecb3f394 379 struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj);
425a5072
TG
380
381 free_masks(desc);
382 free_percpu(desc->kstat_irqs);
383 kfree(desc);
384}
385
ecb3f394
CG
386static void delayed_free_desc(struct rcu_head *rhp)
387{
388 struct irq_desc *desc = container_of(rhp, struct irq_desc, rcu);
389
390 kobject_put(&desc->kobj);
391}
392
1f5a5b87
TG
393static void free_desc(unsigned int irq)
394{
395 struct irq_desc *desc = irq_to_desc(irq);
1f5a5b87 396
13bfe99e
TG
397 unregister_irq_proc(irq, desc);
398
c291ee62
TG
399 /*
400 * sparse_irq_lock protects also show_interrupts() and
401 * kstat_irq_usr(). Once we deleted the descriptor from the
402 * sparse tree we can free it. Access in proc will fail to
403 * lookup the descriptor.
ecb3f394
CG
404 *
405 * The sysfs entry must be serialized against a concurrent
406 * irq_sysfs_init() as well.
c291ee62 407 */
a05a900a 408 mutex_lock(&sparse_irq_lock);
ecb3f394 409 kobject_del(&desc->kobj);
1f5a5b87 410 delete_irq_desc(irq);
a05a900a 411 mutex_unlock(&sparse_irq_lock);
1f5a5b87 412
425a5072
TG
413 /*
414 * We free the descriptor, masks and stat fields via RCU. That
415 * allows demultiplex interrupts to do rcu based management of
416 * the child interrupts.
417 */
418 call_rcu(&desc->rcu, delayed_free_desc);
1f5a5b87
TG
419}
420
b6873807 421static int alloc_descs(unsigned int start, unsigned int cnt, int node,
06ee6d57 422 const struct cpumask *affinity, struct module *owner)
1f5a5b87 423{
45ddcecb 424 const struct cpumask *mask = NULL;
1f5a5b87 425 struct irq_desc *desc;
45ddcecb 426 unsigned int flags;
e75eafb9 427 int i;
45ddcecb 428
e75eafb9
TG
429 /* Validate affinity mask(s) */
430 if (affinity) {
431 for (i = 0, mask = affinity; i < cnt; i++, mask++) {
432 if (cpumask_empty(mask))
433 return -EINVAL;
434 }
435 }
45ddcecb
TG
436
437 flags = affinity ? IRQD_AFFINITY_MANAGED : 0;
e75eafb9 438 mask = NULL;
1f5a5b87
TG
439
440 for (i = 0; i < cnt; i++) {
45ddcecb 441 if (affinity) {
e75eafb9
TG
442 node = cpu_to_node(cpumask_first(affinity));
443 mask = affinity;
444 affinity++;
45ddcecb
TG
445 }
446 desc = alloc_desc(start + i, node, flags, mask, owner);
1f5a5b87
TG
447 if (!desc)
448 goto err;
a05a900a 449 mutex_lock(&sparse_irq_lock);
1f5a5b87 450 irq_insert_desc(start + i, desc);
ecb3f394 451 irq_sysfs_add(start + i, desc);
a05a900a 452 mutex_unlock(&sparse_irq_lock);
1f5a5b87
TG
453 }
454 return start;
455
456err:
457 for (i--; i >= 0; i--)
458 free_desc(start + i);
459
a05a900a 460 mutex_lock(&sparse_irq_lock);
1f5a5b87 461 bitmap_clear(allocated_irqs, start, cnt);
a05a900a 462 mutex_unlock(&sparse_irq_lock);
1f5a5b87
TG
463 return -ENOMEM;
464}
465
ed4dea6e 466static int irq_expand_nr_irqs(unsigned int nr)
e7bcecb7 467{
ed4dea6e 468 if (nr > IRQ_BITMAP_BITS)
e7bcecb7 469 return -ENOMEM;
ed4dea6e 470 nr_irqs = nr;
e7bcecb7
TG
471 return 0;
472}
473
3795de23
TG
474int __init early_irq_init(void)
475{
b683de2b 476 int i, initcnt, node = first_online_node;
3795de23 477 struct irq_desc *desc;
3795de23
TG
478
479 init_irq_default_affinity();
480
b683de2b
TG
481 /* Let arch update nr_irqs and return the nr of preallocated irqs */
482 initcnt = arch_probe_nr_irqs();
5a29ef22
VL
483 printk(KERN_INFO "NR_IRQS: %d, nr_irqs: %d, preallocated irqs: %d\n",
484 NR_IRQS, nr_irqs, initcnt);
3795de23 485
c1ee6264
TG
486 if (WARN_ON(nr_irqs > IRQ_BITMAP_BITS))
487 nr_irqs = IRQ_BITMAP_BITS;
488
489 if (WARN_ON(initcnt > IRQ_BITMAP_BITS))
490 initcnt = IRQ_BITMAP_BITS;
491
492 if (initcnt > nr_irqs)
493 nr_irqs = initcnt;
494
b683de2b 495 for (i = 0; i < initcnt; i++) {
45ddcecb 496 desc = alloc_desc(i, node, 0, NULL, NULL);
aa99ec0f
TG
497 set_bit(i, allocated_irqs);
498 irq_insert_desc(i, desc);
3795de23 499 }
3795de23
TG
500 return arch_early_irq_init();
501}
502
3795de23
TG
503#else /* !CONFIG_SPARSE_IRQ */
504
505struct irq_desc irq_desc[NR_IRQS] __cacheline_aligned_in_smp = {
506 [0 ... NR_IRQS-1] = {
3795de23
TG
507 .handle_irq = handle_bad_irq,
508 .depth = 1,
509 .lock = __RAW_SPIN_LOCK_UNLOCKED(irq_desc->lock),
510 }
511};
512
3795de23
TG
513int __init early_irq_init(void)
514{
aa99ec0f 515 int count, i, node = first_online_node;
3795de23 516 struct irq_desc *desc;
3795de23
TG
517
518 init_irq_default_affinity();
519
5a29ef22 520 printk(KERN_INFO "NR_IRQS: %d\n", NR_IRQS);
3795de23
TG
521
522 desc = irq_desc;
523 count = ARRAY_SIZE(irq_desc);
524
525 for (i = 0; i < count; i++) {
6c9ae009 526 desc[i].kstat_irqs = alloc_percpu(unsigned int);
e7fbad30
LW
527 alloc_masks(&desc[i], GFP_KERNEL, node);
528 raw_spin_lock_init(&desc[i].lock);
154cd387 529 lockdep_set_class(&desc[i].lock, &irq_desc_lock_class);
45ddcecb 530 desc_set_defaults(i, &desc[i], node, NULL, NULL);
3795de23
TG
531 }
532 return arch_early_irq_init();
533}
534
535struct irq_desc *irq_to_desc(unsigned int irq)
536{
537 return (irq < NR_IRQS) ? irq_desc + irq : NULL;
538}
2c45aada 539EXPORT_SYMBOL(irq_to_desc);
3795de23 540
1f5a5b87
TG
541static void free_desc(unsigned int irq)
542{
d8179bc0
TG
543 struct irq_desc *desc = irq_to_desc(irq);
544 unsigned long flags;
545
546 raw_spin_lock_irqsave(&desc->lock, flags);
45ddcecb 547 desc_set_defaults(irq, desc, irq_desc_get_node(desc), NULL, NULL);
d8179bc0 548 raw_spin_unlock_irqrestore(&desc->lock, flags);
1f5a5b87
TG
549}
550
b6873807 551static inline int alloc_descs(unsigned int start, unsigned int cnt, int node,
06ee6d57 552 const struct cpumask *affinity,
b6873807 553 struct module *owner)
1f5a5b87 554{
b6873807
SAS
555 u32 i;
556
557 for (i = 0; i < cnt; i++) {
558 struct irq_desc *desc = irq_to_desc(start + i);
559
560 desc->owner = owner;
561 }
1f5a5b87
TG
562 return start;
563}
e7bcecb7 564
ed4dea6e 565static int irq_expand_nr_irqs(unsigned int nr)
e7bcecb7
TG
566{
567 return -ENOMEM;
568}
569
f63b6a05
TG
570void irq_mark_irq(unsigned int irq)
571{
572 mutex_lock(&sparse_irq_lock);
573 bitmap_set(allocated_irqs, irq, 1);
574 mutex_unlock(&sparse_irq_lock);
575}
576
c940e01c
TG
577#ifdef CONFIG_GENERIC_IRQ_LEGACY
578void irq_init_desc(unsigned int irq)
579{
d8179bc0 580 free_desc(irq);
c940e01c
TG
581}
582#endif
583
3795de23
TG
584#endif /* !CONFIG_SPARSE_IRQ */
585
fe12bc2c
TG
586/**
587 * generic_handle_irq - Invoke the handler for a particular irq
588 * @irq: The irq number to handle
589 *
590 */
591int generic_handle_irq(unsigned int irq)
592{
593 struct irq_desc *desc = irq_to_desc(irq);
594
595 if (!desc)
596 return -EINVAL;
bd0b9ac4 597 generic_handle_irq_desc(desc);
fe12bc2c
TG
598 return 0;
599}
edf76f83 600EXPORT_SYMBOL_GPL(generic_handle_irq);
fe12bc2c 601
76ba59f8
MZ
602#ifdef CONFIG_HANDLE_DOMAIN_IRQ
603/**
604 * __handle_domain_irq - Invoke the handler for a HW irq belonging to a domain
605 * @domain: The domain where to perform the lookup
606 * @hwirq: The HW irq number to convert to a logical one
607 * @lookup: Whether to perform the domain lookup or not
608 * @regs: Register file coming from the low-level handling code
609 *
610 * Returns: 0 on success, or -EINVAL if conversion has failed
611 */
612int __handle_domain_irq(struct irq_domain *domain, unsigned int hwirq,
613 bool lookup, struct pt_regs *regs)
614{
615 struct pt_regs *old_regs = set_irq_regs(regs);
616 unsigned int irq = hwirq;
617 int ret = 0;
618
619 irq_enter();
620
621#ifdef CONFIG_IRQ_DOMAIN
622 if (lookup)
623 irq = irq_find_mapping(domain, hwirq);
624#endif
625
626 /*
627 * Some hardware gives randomly wrong interrupts. Rather
628 * than crashing, do something sensible.
629 */
630 if (unlikely(!irq || irq >= nr_irqs)) {
631 ack_bad_irq(irq);
632 ret = -EINVAL;
633 } else {
634 generic_handle_irq(irq);
635 }
636
637 irq_exit();
638 set_irq_regs(old_regs);
639 return ret;
640}
641#endif
642
1f5a5b87
TG
643/* Dynamic interrupt handling */
644
645/**
646 * irq_free_descs - free irq descriptors
647 * @from: Start of descriptor range
648 * @cnt: Number of consecutive irqs to free
649 */
650void irq_free_descs(unsigned int from, unsigned int cnt)
651{
1f5a5b87
TG
652 int i;
653
654 if (from >= nr_irqs || (from + cnt) > nr_irqs)
655 return;
656
657 for (i = 0; i < cnt; i++)
658 free_desc(from + i);
659
a05a900a 660 mutex_lock(&sparse_irq_lock);
1f5a5b87 661 bitmap_clear(allocated_irqs, from, cnt);
a05a900a 662 mutex_unlock(&sparse_irq_lock);
1f5a5b87 663}
edf76f83 664EXPORT_SYMBOL_GPL(irq_free_descs);
1f5a5b87
TG
665
666/**
667 * irq_alloc_descs - allocate and initialize a range of irq descriptors
668 * @irq: Allocate for specific irq number if irq >= 0
669 * @from: Start the search from this irq number
670 * @cnt: Number of consecutive irqs to allocate.
671 * @node: Preferred node on which the irq descriptor should be allocated
d522a0d1 672 * @owner: Owning module (can be NULL)
e75eafb9
TG
673 * @affinity: Optional pointer to an affinity mask array of size @cnt which
674 * hints where the irq descriptors should be allocated and which
675 * default affinities to use
1f5a5b87
TG
676 *
677 * Returns the first irq number or error code
678 */
679int __ref
b6873807 680__irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
06ee6d57 681 struct module *owner, const struct cpumask *affinity)
1f5a5b87 682{
1f5a5b87
TG
683 int start, ret;
684
685 if (!cnt)
686 return -EINVAL;
687
c5182b88
MB
688 if (irq >= 0) {
689 if (from > irq)
690 return -EINVAL;
691 from = irq;
62a08ae2
TG
692 } else {
693 /*
694 * For interrupts which are freely allocated the
695 * architecture can force a lower bound to the @from
696 * argument. x86 uses this to exclude the GSI space.
697 */
698 from = arch_dynirq_lower_bound(from);
c5182b88
MB
699 }
700
a05a900a 701 mutex_lock(&sparse_irq_lock);
1f5a5b87 702
ed4dea6e
YL
703 start = bitmap_find_next_zero_area(allocated_irqs, IRQ_BITMAP_BITS,
704 from, cnt, 0);
1f5a5b87
TG
705 ret = -EEXIST;
706 if (irq >=0 && start != irq)
707 goto err;
708
ed4dea6e
YL
709 if (start + cnt > nr_irqs) {
710 ret = irq_expand_nr_irqs(start + cnt);
e7bcecb7
TG
711 if (ret)
712 goto err;
713 }
1f5a5b87
TG
714
715 bitmap_set(allocated_irqs, start, cnt);
a05a900a 716 mutex_unlock(&sparse_irq_lock);
06ee6d57 717 return alloc_descs(start, cnt, node, affinity, owner);
1f5a5b87
TG
718
719err:
a05a900a 720 mutex_unlock(&sparse_irq_lock);
1f5a5b87
TG
721 return ret;
722}
b6873807 723EXPORT_SYMBOL_GPL(__irq_alloc_descs);
1f5a5b87 724
7b6ef126
TG
725#ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
726/**
727 * irq_alloc_hwirqs - Allocate an irq descriptor and initialize the hardware
728 * @cnt: number of interrupts to allocate
729 * @node: node on which to allocate
730 *
731 * Returns an interrupt number > 0 or 0, if the allocation fails.
732 */
733unsigned int irq_alloc_hwirqs(int cnt, int node)
734{
06ee6d57 735 int i, irq = __irq_alloc_descs(-1, 0, cnt, node, NULL, NULL);
7b6ef126
TG
736
737 if (irq < 0)
738 return 0;
739
740 for (i = irq; cnt > 0; i++, cnt--) {
741 if (arch_setup_hwirq(i, node))
742 goto err;
743 irq_clear_status_flags(i, _IRQ_NOREQUEST);
744 }
745 return irq;
746
747err:
748 for (i--; i >= irq; i--) {
749 irq_set_status_flags(i, _IRQ_NOREQUEST | _IRQ_NOPROBE);
750 arch_teardown_hwirq(i);
751 }
752 irq_free_descs(irq, cnt);
753 return 0;
754}
755EXPORT_SYMBOL_GPL(irq_alloc_hwirqs);
756
757/**
758 * irq_free_hwirqs - Free irq descriptor and cleanup the hardware
759 * @from: Free from irq number
760 * @cnt: number of interrupts to free
761 *
762 */
763void irq_free_hwirqs(unsigned int from, int cnt)
764{
8844aad8 765 int i, j;
7b6ef126 766
8844aad8 767 for (i = from, j = cnt; j > 0; i++, j--) {
7b6ef126
TG
768 irq_set_status_flags(i, _IRQ_NOREQUEST | _IRQ_NOPROBE);
769 arch_teardown_hwirq(i);
770 }
771 irq_free_descs(from, cnt);
772}
773EXPORT_SYMBOL_GPL(irq_free_hwirqs);
774#endif
775
a98d24b7
TG
776/**
777 * irq_get_next_irq - get next allocated irq number
778 * @offset: where to start the search
779 *
780 * Returns next irq number after offset or nr_irqs if none is found.
781 */
782unsigned int irq_get_next_irq(unsigned int offset)
783{
784 return find_next_bit(allocated_irqs, nr_irqs, offset);
785}
786
d5eb4ad2 787struct irq_desc *
31d9d9b6
MZ
788__irq_get_desc_lock(unsigned int irq, unsigned long *flags, bool bus,
789 unsigned int check)
d5eb4ad2
TG
790{
791 struct irq_desc *desc = irq_to_desc(irq);
792
793 if (desc) {
31d9d9b6
MZ
794 if (check & _IRQ_DESC_CHECK) {
795 if ((check & _IRQ_DESC_PERCPU) &&
796 !irq_settings_is_per_cpu_devid(desc))
797 return NULL;
798
799 if (!(check & _IRQ_DESC_PERCPU) &&
800 irq_settings_is_per_cpu_devid(desc))
801 return NULL;
802 }
803
d5eb4ad2
TG
804 if (bus)
805 chip_bus_lock(desc);
806 raw_spin_lock_irqsave(&desc->lock, *flags);
807 }
808 return desc;
809}
810
811void __irq_put_desc_unlock(struct irq_desc *desc, unsigned long flags, bool bus)
812{
813 raw_spin_unlock_irqrestore(&desc->lock, flags);
814 if (bus)
815 chip_bus_sync_unlock(desc);
816}
817
222df54f
MZ
818int irq_set_percpu_devid_partition(unsigned int irq,
819 const struct cpumask *affinity)
31d9d9b6
MZ
820{
821 struct irq_desc *desc = irq_to_desc(irq);
822
823 if (!desc)
824 return -EINVAL;
825
826 if (desc->percpu_enabled)
827 return -EINVAL;
828
829 desc->percpu_enabled = kzalloc(sizeof(*desc->percpu_enabled), GFP_KERNEL);
830
831 if (!desc->percpu_enabled)
832 return -ENOMEM;
833
222df54f
MZ
834 if (affinity)
835 desc->percpu_affinity = affinity;
836 else
837 desc->percpu_affinity = cpu_possible_mask;
838
31d9d9b6
MZ
839 irq_set_percpu_devid_flags(irq);
840 return 0;
841}
842
222df54f
MZ
843int irq_set_percpu_devid(unsigned int irq)
844{
845 return irq_set_percpu_devid_partition(irq, NULL);
846}
847
848int irq_get_percpu_devid_partition(unsigned int irq, struct cpumask *affinity)
849{
850 struct irq_desc *desc = irq_to_desc(irq);
851
852 if (!desc || !desc->percpu_enabled)
853 return -EINVAL;
854
855 if (affinity)
856 cpumask_copy(affinity, desc->percpu_affinity);
857
858 return 0;
859}
860
792d0018
TG
861void kstat_incr_irq_this_cpu(unsigned int irq)
862{
b51bf95c 863 kstat_incr_irqs_this_cpu(irq_to_desc(irq));
792d0018
TG
864}
865
c291ee62
TG
866/**
867 * kstat_irqs_cpu - Get the statistics for an interrupt on a cpu
868 * @irq: The interrupt number
869 * @cpu: The cpu number
870 *
871 * Returns the sum of interrupt counts on @cpu since boot for
872 * @irq. The caller must ensure that the interrupt is not removed
873 * concurrently.
874 */
3795de23
TG
875unsigned int kstat_irqs_cpu(unsigned int irq, int cpu)
876{
877 struct irq_desc *desc = irq_to_desc(irq);
6c9ae009
ED
878
879 return desc && desc->kstat_irqs ?
880 *per_cpu_ptr(desc->kstat_irqs, cpu) : 0;
3795de23 881}
478735e3 882
c291ee62
TG
883/**
884 * kstat_irqs - Get the statistics for an interrupt
885 * @irq: The interrupt number
886 *
887 * Returns the sum of interrupt counts on all cpus since boot for
888 * @irq. The caller must ensure that the interrupt is not removed
889 * concurrently.
890 */
478735e3
KH
891unsigned int kstat_irqs(unsigned int irq)
892{
893 struct irq_desc *desc = irq_to_desc(irq);
894 int cpu;
5e9662fa 895 unsigned int sum = 0;
478735e3 896
6c9ae009 897 if (!desc || !desc->kstat_irqs)
478735e3
KH
898 return 0;
899 for_each_possible_cpu(cpu)
6c9ae009 900 sum += *per_cpu_ptr(desc->kstat_irqs, cpu);
478735e3
KH
901 return sum;
902}
c291ee62
TG
903
904/**
905 * kstat_irqs_usr - Get the statistics for an interrupt
906 * @irq: The interrupt number
907 *
908 * Returns the sum of interrupt counts on all cpus since boot for
909 * @irq. Contrary to kstat_irqs() this can be called from any
910 * preemptible context. It's protected against concurrent removal of
911 * an interrupt descriptor when sparse irqs are enabled.
912 */
913unsigned int kstat_irqs_usr(unsigned int irq)
914{
7df0b278 915 unsigned int sum;
c291ee62
TG
916
917 irq_lock_sparse();
918 sum = kstat_irqs(irq);
919 irq_unlock_sparse();
920 return sum;
921}