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3795de23 TG |
1 | /* |
2 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
3 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
4 | * | |
5 | * This file contains the interrupt descriptor management code | |
6 | * | |
c0c6e085 | 7 | * Detailed information is available in Documentation/core-api/genericirq.rst |
3795de23 TG |
8 | * |
9 | */ | |
10 | #include <linux/irq.h> | |
11 | #include <linux/slab.h> | |
ec53cf23 | 12 | #include <linux/export.h> |
3795de23 TG |
13 | #include <linux/interrupt.h> |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/radix-tree.h> | |
1f5a5b87 | 16 | #include <linux/bitmap.h> |
76ba59f8 | 17 | #include <linux/irqdomain.h> |
ecb3f394 | 18 | #include <linux/sysfs.h> |
3795de23 TG |
19 | |
20 | #include "internals.h" | |
21 | ||
22 | /* | |
23 | * lockdep: we want to handle all irq_desc locks as a single lock-class: | |
24 | */ | |
78f90d91 | 25 | static struct lock_class_key irq_desc_lock_class; |
3795de23 | 26 | |
fe051434 | 27 | #if defined(CONFIG_SMP) |
fbf19803 TG |
28 | static int __init irq_affinity_setup(char *str) |
29 | { | |
10d94ff4 | 30 | alloc_bootmem_cpumask_var(&irq_default_affinity); |
fbf19803 TG |
31 | cpulist_parse(str, irq_default_affinity); |
32 | /* | |
33 | * Set at least the boot cpu. We don't want to end up with | |
34 | * bugreports caused by random comandline masks | |
35 | */ | |
36 | cpumask_set_cpu(smp_processor_id(), irq_default_affinity); | |
37 | return 1; | |
38 | } | |
39 | __setup("irqaffinity=", irq_affinity_setup); | |
40 | ||
3795de23 TG |
41 | static void __init init_irq_default_affinity(void) |
42 | { | |
10d94ff4 | 43 | if (!cpumask_available(irq_default_affinity)) |
fbf19803 | 44 | zalloc_cpumask_var(&irq_default_affinity, GFP_NOWAIT); |
fbf19803 TG |
45 | if (cpumask_empty(irq_default_affinity)) |
46 | cpumask_setall(irq_default_affinity); | |
3795de23 TG |
47 | } |
48 | #else | |
49 | static void __init init_irq_default_affinity(void) | |
50 | { | |
51 | } | |
52 | #endif | |
53 | ||
1f5a5b87 | 54 | #ifdef CONFIG_SMP |
4ab764c3 | 55 | static int alloc_masks(struct irq_desc *desc, int node) |
1f5a5b87 | 56 | { |
9df872fa | 57 | if (!zalloc_cpumask_var_node(&desc->irq_common_data.affinity, |
4ab764c3 | 58 | GFP_KERNEL, node)) |
1f5a5b87 TG |
59 | return -ENOMEM; |
60 | ||
0d3f5425 TG |
61 | #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK |
62 | if (!zalloc_cpumask_var_node(&desc->irq_common_data.effective_affinity, | |
63 | GFP_KERNEL, node)) { | |
64 | free_cpumask_var(desc->irq_common_data.affinity); | |
65 | return -ENOMEM; | |
66 | } | |
67 | #endif | |
68 | ||
1f5a5b87 | 69 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
4ab764c3 | 70 | if (!zalloc_cpumask_var_node(&desc->pending_mask, GFP_KERNEL, node)) { |
0d3f5425 TG |
71 | #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK |
72 | free_cpumask_var(desc->irq_common_data.effective_affinity); | |
73 | #endif | |
9df872fa | 74 | free_cpumask_var(desc->irq_common_data.affinity); |
1f5a5b87 TG |
75 | return -ENOMEM; |
76 | } | |
77 | #endif | |
78 | return 0; | |
79 | } | |
80 | ||
45ddcecb TG |
81 | static void desc_smp_init(struct irq_desc *desc, int node, |
82 | const struct cpumask *affinity) | |
1f5a5b87 | 83 | { |
45ddcecb TG |
84 | if (!affinity) |
85 | affinity = irq_default_affinity; | |
86 | cpumask_copy(desc->irq_common_data.affinity, affinity); | |
87 | ||
b7b29338 TG |
88 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
89 | cpumask_clear(desc->pending_mask); | |
90 | #endif | |
449e9cae JL |
91 | #ifdef CONFIG_NUMA |
92 | desc->irq_common_data.node = node; | |
93 | #endif | |
b7b29338 TG |
94 | } |
95 | ||
1f5a5b87 TG |
96 | #else |
97 | static inline int | |
4ab764c3 | 98 | alloc_masks(struct irq_desc *desc, int node) { return 0; } |
45ddcecb TG |
99 | static inline void |
100 | desc_smp_init(struct irq_desc *desc, int node, const struct cpumask *affinity) { } | |
1f5a5b87 TG |
101 | #endif |
102 | ||
b6873807 | 103 | static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node, |
45ddcecb | 104 | const struct cpumask *affinity, struct module *owner) |
1f5a5b87 | 105 | { |
6c9ae009 ED |
106 | int cpu; |
107 | ||
af7080e0 | 108 | desc->irq_common_data.handler_data = NULL; |
b237721c | 109 | desc->irq_common_data.msi_desc = NULL; |
af7080e0 | 110 | |
0d0b4c86 | 111 | desc->irq_data.common = &desc->irq_common_data; |
1f5a5b87 TG |
112 | desc->irq_data.irq = irq; |
113 | desc->irq_data.chip = &no_irq_chip; | |
114 | desc->irq_data.chip_data = NULL; | |
f9e4989e | 115 | irq_settings_clr_and_set(desc, ~0, _IRQ_DEFAULT_INIT_FLAGS); |
801a0e9a | 116 | irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); |
d829b8fb | 117 | irqd_set(&desc->irq_data, IRQD_IRQ_MASKED); |
1f5a5b87 TG |
118 | desc->handle_irq = handle_bad_irq; |
119 | desc->depth = 1; | |
b7b29338 TG |
120 | desc->irq_count = 0; |
121 | desc->irqs_unhandled = 0; | |
1f5a5b87 | 122 | desc->name = NULL; |
b6873807 | 123 | desc->owner = owner; |
6c9ae009 ED |
124 | for_each_possible_cpu(cpu) |
125 | *per_cpu_ptr(desc->kstat_irqs, cpu) = 0; | |
45ddcecb | 126 | desc_smp_init(desc, node, affinity); |
1f5a5b87 TG |
127 | } |
128 | ||
3795de23 TG |
129 | int nr_irqs = NR_IRQS; |
130 | EXPORT_SYMBOL_GPL(nr_irqs); | |
131 | ||
a05a900a | 132 | static DEFINE_MUTEX(sparse_irq_lock); |
c1ee6264 | 133 | static DECLARE_BITMAP(allocated_irqs, IRQ_BITMAP_BITS); |
1f5a5b87 | 134 | |
3795de23 TG |
135 | #ifdef CONFIG_SPARSE_IRQ |
136 | ||
ecb3f394 CG |
137 | static void irq_kobj_release(struct kobject *kobj); |
138 | ||
139 | #ifdef CONFIG_SYSFS | |
140 | static struct kobject *irq_kobj_base; | |
141 | ||
142 | #define IRQ_ATTR_RO(_name) \ | |
143 | static struct kobj_attribute _name##_attr = __ATTR_RO(_name) | |
144 | ||
145 | static ssize_t per_cpu_count_show(struct kobject *kobj, | |
146 | struct kobj_attribute *attr, char *buf) | |
147 | { | |
148 | struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj); | |
149 | int cpu, irq = desc->irq_data.irq; | |
150 | ssize_t ret = 0; | |
151 | char *p = ""; | |
152 | ||
153 | for_each_possible_cpu(cpu) { | |
154 | unsigned int c = kstat_irqs_cpu(irq, cpu); | |
155 | ||
156 | ret += scnprintf(buf + ret, PAGE_SIZE - ret, "%s%u", p, c); | |
157 | p = ","; | |
158 | } | |
159 | ||
160 | ret += scnprintf(buf + ret, PAGE_SIZE - ret, "\n"); | |
161 | return ret; | |
162 | } | |
163 | IRQ_ATTR_RO(per_cpu_count); | |
164 | ||
165 | static ssize_t chip_name_show(struct kobject *kobj, | |
166 | struct kobj_attribute *attr, char *buf) | |
167 | { | |
168 | struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj); | |
169 | ssize_t ret = 0; | |
170 | ||
171 | raw_spin_lock_irq(&desc->lock); | |
172 | if (desc->irq_data.chip && desc->irq_data.chip->name) { | |
173 | ret = scnprintf(buf, PAGE_SIZE, "%s\n", | |
174 | desc->irq_data.chip->name); | |
175 | } | |
176 | raw_spin_unlock_irq(&desc->lock); | |
177 | ||
178 | return ret; | |
179 | } | |
180 | IRQ_ATTR_RO(chip_name); | |
181 | ||
182 | static ssize_t hwirq_show(struct kobject *kobj, | |
183 | struct kobj_attribute *attr, char *buf) | |
184 | { | |
185 | struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj); | |
186 | ssize_t ret = 0; | |
187 | ||
188 | raw_spin_lock_irq(&desc->lock); | |
189 | if (desc->irq_data.domain) | |
190 | ret = sprintf(buf, "%d\n", (int)desc->irq_data.hwirq); | |
191 | raw_spin_unlock_irq(&desc->lock); | |
192 | ||
193 | return ret; | |
194 | } | |
195 | IRQ_ATTR_RO(hwirq); | |
196 | ||
197 | static ssize_t type_show(struct kobject *kobj, | |
198 | struct kobj_attribute *attr, char *buf) | |
199 | { | |
200 | struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj); | |
201 | ssize_t ret = 0; | |
202 | ||
203 | raw_spin_lock_irq(&desc->lock); | |
204 | ret = sprintf(buf, "%s\n", | |
205 | irqd_is_level_type(&desc->irq_data) ? "level" : "edge"); | |
206 | raw_spin_unlock_irq(&desc->lock); | |
207 | ||
208 | return ret; | |
209 | ||
210 | } | |
211 | IRQ_ATTR_RO(type); | |
212 | ||
213 | static ssize_t name_show(struct kobject *kobj, | |
214 | struct kobj_attribute *attr, char *buf) | |
215 | { | |
216 | struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj); | |
217 | ssize_t ret = 0; | |
218 | ||
219 | raw_spin_lock_irq(&desc->lock); | |
220 | if (desc->name) | |
221 | ret = scnprintf(buf, PAGE_SIZE, "%s\n", desc->name); | |
222 | raw_spin_unlock_irq(&desc->lock); | |
223 | ||
224 | return ret; | |
225 | } | |
226 | IRQ_ATTR_RO(name); | |
227 | ||
228 | static ssize_t actions_show(struct kobject *kobj, | |
229 | struct kobj_attribute *attr, char *buf) | |
230 | { | |
231 | struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj); | |
232 | struct irqaction *action; | |
233 | ssize_t ret = 0; | |
234 | char *p = ""; | |
235 | ||
236 | raw_spin_lock_irq(&desc->lock); | |
237 | for (action = desc->action; action != NULL; action = action->next) { | |
238 | ret += scnprintf(buf + ret, PAGE_SIZE - ret, "%s%s", | |
239 | p, action->name); | |
240 | p = ","; | |
241 | } | |
242 | raw_spin_unlock_irq(&desc->lock); | |
243 | ||
244 | if (ret) | |
245 | ret += scnprintf(buf + ret, PAGE_SIZE - ret, "\n"); | |
246 | ||
247 | return ret; | |
248 | } | |
249 | IRQ_ATTR_RO(actions); | |
250 | ||
251 | static struct attribute *irq_attrs[] = { | |
252 | &per_cpu_count_attr.attr, | |
253 | &chip_name_attr.attr, | |
254 | &hwirq_attr.attr, | |
255 | &type_attr.attr, | |
256 | &name_attr.attr, | |
257 | &actions_attr.attr, | |
258 | NULL | |
259 | }; | |
260 | ||
261 | static struct kobj_type irq_kobj_type = { | |
262 | .release = irq_kobj_release, | |
263 | .sysfs_ops = &kobj_sysfs_ops, | |
264 | .default_attrs = irq_attrs, | |
265 | }; | |
266 | ||
267 | static void irq_sysfs_add(int irq, struct irq_desc *desc) | |
268 | { | |
269 | if (irq_kobj_base) { | |
270 | /* | |
271 | * Continue even in case of failure as this is nothing | |
272 | * crucial. | |
273 | */ | |
274 | if (kobject_add(&desc->kobj, irq_kobj_base, "%d", irq)) | |
275 | pr_warn("Failed to add kobject for irq %d\n", irq); | |
276 | } | |
277 | } | |
278 | ||
279 | static int __init irq_sysfs_init(void) | |
280 | { | |
281 | struct irq_desc *desc; | |
282 | int irq; | |
283 | ||
284 | /* Prevent concurrent irq alloc/free */ | |
285 | irq_lock_sparse(); | |
286 | ||
287 | irq_kobj_base = kobject_create_and_add("irq", kernel_kobj); | |
288 | if (!irq_kobj_base) { | |
289 | irq_unlock_sparse(); | |
290 | return -ENOMEM; | |
291 | } | |
292 | ||
293 | /* Add the already allocated interrupts */ | |
294 | for_each_irq_desc(irq, desc) | |
295 | irq_sysfs_add(irq, desc); | |
296 | irq_unlock_sparse(); | |
297 | ||
298 | return 0; | |
299 | } | |
300 | postcore_initcall(irq_sysfs_init); | |
301 | ||
302 | #else /* !CONFIG_SYSFS */ | |
303 | ||
304 | static struct kobj_type irq_kobj_type = { | |
305 | .release = irq_kobj_release, | |
306 | }; | |
307 | ||
308 | static void irq_sysfs_add(int irq, struct irq_desc *desc) {} | |
309 | ||
310 | #endif /* CONFIG_SYSFS */ | |
311 | ||
baa0d233 | 312 | static RADIX_TREE(irq_desc_tree, GFP_KERNEL); |
3795de23 | 313 | |
1f5a5b87 | 314 | static void irq_insert_desc(unsigned int irq, struct irq_desc *desc) |
3795de23 TG |
315 | { |
316 | radix_tree_insert(&irq_desc_tree, irq, desc); | |
317 | } | |
318 | ||
319 | struct irq_desc *irq_to_desc(unsigned int irq) | |
320 | { | |
321 | return radix_tree_lookup(&irq_desc_tree, irq); | |
322 | } | |
3911ff30 | 323 | EXPORT_SYMBOL(irq_to_desc); |
3795de23 | 324 | |
1f5a5b87 TG |
325 | static void delete_irq_desc(unsigned int irq) |
326 | { | |
327 | radix_tree_delete(&irq_desc_tree, irq); | |
328 | } | |
329 | ||
330 | #ifdef CONFIG_SMP | |
331 | static void free_masks(struct irq_desc *desc) | |
332 | { | |
333 | #ifdef CONFIG_GENERIC_PENDING_IRQ | |
334 | free_cpumask_var(desc->pending_mask); | |
335 | #endif | |
9df872fa | 336 | free_cpumask_var(desc->irq_common_data.affinity); |
0d3f5425 TG |
337 | #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK |
338 | free_cpumask_var(desc->irq_common_data.effective_affinity); | |
339 | #endif | |
1f5a5b87 TG |
340 | } |
341 | #else | |
342 | static inline void free_masks(struct irq_desc *desc) { } | |
343 | #endif | |
344 | ||
c291ee62 TG |
345 | void irq_lock_sparse(void) |
346 | { | |
347 | mutex_lock(&sparse_irq_lock); | |
348 | } | |
349 | ||
350 | void irq_unlock_sparse(void) | |
351 | { | |
352 | mutex_unlock(&sparse_irq_lock); | |
353 | } | |
354 | ||
45ddcecb TG |
355 | static struct irq_desc *alloc_desc(int irq, int node, unsigned int flags, |
356 | const struct cpumask *affinity, | |
357 | struct module *owner) | |
1f5a5b87 TG |
358 | { |
359 | struct irq_desc *desc; | |
1f5a5b87 | 360 | |
4ab764c3 | 361 | desc = kzalloc_node(sizeof(*desc), GFP_KERNEL, node); |
1f5a5b87 TG |
362 | if (!desc) |
363 | return NULL; | |
364 | /* allocate based on nr_cpu_ids */ | |
6c9ae009 | 365 | desc->kstat_irqs = alloc_percpu(unsigned int); |
1f5a5b87 TG |
366 | if (!desc->kstat_irqs) |
367 | goto err_desc; | |
368 | ||
4ab764c3 | 369 | if (alloc_masks(desc, node)) |
1f5a5b87 TG |
370 | goto err_kstat; |
371 | ||
372 | raw_spin_lock_init(&desc->lock); | |
373 | lockdep_set_class(&desc->lock, &irq_desc_lock_class); | |
9114014c | 374 | mutex_init(&desc->request_mutex); |
425a5072 | 375 | init_rcu_head(&desc->rcu); |
1f5a5b87 | 376 | |
45ddcecb TG |
377 | desc_set_defaults(irq, desc, node, affinity, owner); |
378 | irqd_set(&desc->irq_data, flags); | |
ecb3f394 | 379 | kobject_init(&desc->kobj, &irq_kobj_type); |
1f5a5b87 TG |
380 | |
381 | return desc; | |
382 | ||
383 | err_kstat: | |
6c9ae009 | 384 | free_percpu(desc->kstat_irqs); |
1f5a5b87 TG |
385 | err_desc: |
386 | kfree(desc); | |
387 | return NULL; | |
388 | } | |
389 | ||
ecb3f394 | 390 | static void irq_kobj_release(struct kobject *kobj) |
425a5072 | 391 | { |
ecb3f394 | 392 | struct irq_desc *desc = container_of(kobj, struct irq_desc, kobj); |
425a5072 TG |
393 | |
394 | free_masks(desc); | |
395 | free_percpu(desc->kstat_irqs); | |
396 | kfree(desc); | |
397 | } | |
398 | ||
ecb3f394 CG |
399 | static void delayed_free_desc(struct rcu_head *rhp) |
400 | { | |
401 | struct irq_desc *desc = container_of(rhp, struct irq_desc, rcu); | |
402 | ||
403 | kobject_put(&desc->kobj); | |
404 | } | |
405 | ||
1f5a5b87 TG |
406 | static void free_desc(unsigned int irq) |
407 | { | |
408 | struct irq_desc *desc = irq_to_desc(irq); | |
1f5a5b87 | 409 | |
087cdfb6 | 410 | irq_remove_debugfs_entry(desc); |
13bfe99e TG |
411 | unregister_irq_proc(irq, desc); |
412 | ||
c291ee62 TG |
413 | /* |
414 | * sparse_irq_lock protects also show_interrupts() and | |
415 | * kstat_irq_usr(). Once we deleted the descriptor from the | |
416 | * sparse tree we can free it. Access in proc will fail to | |
417 | * lookup the descriptor. | |
ecb3f394 CG |
418 | * |
419 | * The sysfs entry must be serialized against a concurrent | |
420 | * irq_sysfs_init() as well. | |
c291ee62 | 421 | */ |
ecb3f394 | 422 | kobject_del(&desc->kobj); |
1f5a5b87 | 423 | delete_irq_desc(irq); |
1f5a5b87 | 424 | |
425a5072 TG |
425 | /* |
426 | * We free the descriptor, masks and stat fields via RCU. That | |
427 | * allows demultiplex interrupts to do rcu based management of | |
428 | * the child interrupts. | |
429 | */ | |
430 | call_rcu(&desc->rcu, delayed_free_desc); | |
1f5a5b87 TG |
431 | } |
432 | ||
b6873807 | 433 | static int alloc_descs(unsigned int start, unsigned int cnt, int node, |
06ee6d57 | 434 | const struct cpumask *affinity, struct module *owner) |
1f5a5b87 | 435 | { |
45ddcecb | 436 | const struct cpumask *mask = NULL; |
1f5a5b87 | 437 | struct irq_desc *desc; |
45ddcecb | 438 | unsigned int flags; |
e75eafb9 | 439 | int i; |
45ddcecb | 440 | |
e75eafb9 TG |
441 | /* Validate affinity mask(s) */ |
442 | if (affinity) { | |
443 | for (i = 0, mask = affinity; i < cnt; i++, mask++) { | |
444 | if (cpumask_empty(mask)) | |
445 | return -EINVAL; | |
446 | } | |
447 | } | |
45ddcecb | 448 | |
239306fe | 449 | flags = affinity ? IRQD_AFFINITY_MANAGED | IRQD_MANAGED_SHUTDOWN : 0; |
e75eafb9 | 450 | mask = NULL; |
1f5a5b87 TG |
451 | |
452 | for (i = 0; i < cnt; i++) { | |
45ddcecb | 453 | if (affinity) { |
e75eafb9 TG |
454 | node = cpu_to_node(cpumask_first(affinity)); |
455 | mask = affinity; | |
456 | affinity++; | |
45ddcecb TG |
457 | } |
458 | desc = alloc_desc(start + i, node, flags, mask, owner); | |
1f5a5b87 TG |
459 | if (!desc) |
460 | goto err; | |
1f5a5b87 | 461 | irq_insert_desc(start + i, desc); |
ecb3f394 | 462 | irq_sysfs_add(start + i, desc); |
e0b47794 | 463 | irq_add_debugfs_entry(start + i, desc); |
1f5a5b87 | 464 | } |
12ac1d0f | 465 | bitmap_set(allocated_irqs, start, cnt); |
1f5a5b87 TG |
466 | return start; |
467 | ||
468 | err: | |
469 | for (i--; i >= 0; i--) | |
470 | free_desc(start + i); | |
1f5a5b87 TG |
471 | return -ENOMEM; |
472 | } | |
473 | ||
ed4dea6e | 474 | static int irq_expand_nr_irqs(unsigned int nr) |
e7bcecb7 | 475 | { |
ed4dea6e | 476 | if (nr > IRQ_BITMAP_BITS) |
e7bcecb7 | 477 | return -ENOMEM; |
ed4dea6e | 478 | nr_irqs = nr; |
e7bcecb7 TG |
479 | return 0; |
480 | } | |
481 | ||
3795de23 TG |
482 | int __init early_irq_init(void) |
483 | { | |
b683de2b | 484 | int i, initcnt, node = first_online_node; |
3795de23 | 485 | struct irq_desc *desc; |
3795de23 TG |
486 | |
487 | init_irq_default_affinity(); | |
488 | ||
b683de2b TG |
489 | /* Let arch update nr_irqs and return the nr of preallocated irqs */ |
490 | initcnt = arch_probe_nr_irqs(); | |
5a29ef22 VL |
491 | printk(KERN_INFO "NR_IRQS: %d, nr_irqs: %d, preallocated irqs: %d\n", |
492 | NR_IRQS, nr_irqs, initcnt); | |
3795de23 | 493 | |
c1ee6264 TG |
494 | if (WARN_ON(nr_irqs > IRQ_BITMAP_BITS)) |
495 | nr_irqs = IRQ_BITMAP_BITS; | |
496 | ||
497 | if (WARN_ON(initcnt > IRQ_BITMAP_BITS)) | |
498 | initcnt = IRQ_BITMAP_BITS; | |
499 | ||
500 | if (initcnt > nr_irqs) | |
501 | nr_irqs = initcnt; | |
502 | ||
b683de2b | 503 | for (i = 0; i < initcnt; i++) { |
45ddcecb | 504 | desc = alloc_desc(i, node, 0, NULL, NULL); |
aa99ec0f TG |
505 | set_bit(i, allocated_irqs); |
506 | irq_insert_desc(i, desc); | |
3795de23 | 507 | } |
3795de23 TG |
508 | return arch_early_irq_init(); |
509 | } | |
510 | ||
3795de23 TG |
511 | #else /* !CONFIG_SPARSE_IRQ */ |
512 | ||
513 | struct irq_desc irq_desc[NR_IRQS] __cacheline_aligned_in_smp = { | |
514 | [0 ... NR_IRQS-1] = { | |
3795de23 TG |
515 | .handle_irq = handle_bad_irq, |
516 | .depth = 1, | |
517 | .lock = __RAW_SPIN_LOCK_UNLOCKED(irq_desc->lock), | |
518 | } | |
519 | }; | |
520 | ||
3795de23 TG |
521 | int __init early_irq_init(void) |
522 | { | |
aa99ec0f | 523 | int count, i, node = first_online_node; |
3795de23 | 524 | struct irq_desc *desc; |
3795de23 TG |
525 | |
526 | init_irq_default_affinity(); | |
527 | ||
5a29ef22 | 528 | printk(KERN_INFO "NR_IRQS: %d\n", NR_IRQS); |
3795de23 TG |
529 | |
530 | desc = irq_desc; | |
531 | count = ARRAY_SIZE(irq_desc); | |
532 | ||
533 | for (i = 0; i < count; i++) { | |
6c9ae009 | 534 | desc[i].kstat_irqs = alloc_percpu(unsigned int); |
4ab764c3 | 535 | alloc_masks(&desc[i], node); |
e7fbad30 | 536 | raw_spin_lock_init(&desc[i].lock); |
154cd387 | 537 | lockdep_set_class(&desc[i].lock, &irq_desc_lock_class); |
45ddcecb | 538 | desc_set_defaults(i, &desc[i], node, NULL, NULL); |
3795de23 TG |
539 | } |
540 | return arch_early_irq_init(); | |
541 | } | |
542 | ||
543 | struct irq_desc *irq_to_desc(unsigned int irq) | |
544 | { | |
545 | return (irq < NR_IRQS) ? irq_desc + irq : NULL; | |
546 | } | |
2c45aada | 547 | EXPORT_SYMBOL(irq_to_desc); |
3795de23 | 548 | |
1f5a5b87 TG |
549 | static void free_desc(unsigned int irq) |
550 | { | |
d8179bc0 TG |
551 | struct irq_desc *desc = irq_to_desc(irq); |
552 | unsigned long flags; | |
553 | ||
554 | raw_spin_lock_irqsave(&desc->lock, flags); | |
45ddcecb | 555 | desc_set_defaults(irq, desc, irq_desc_get_node(desc), NULL, NULL); |
d8179bc0 | 556 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1f5a5b87 TG |
557 | } |
558 | ||
b6873807 | 559 | static inline int alloc_descs(unsigned int start, unsigned int cnt, int node, |
06ee6d57 | 560 | const struct cpumask *affinity, |
b6873807 | 561 | struct module *owner) |
1f5a5b87 | 562 | { |
b6873807 SAS |
563 | u32 i; |
564 | ||
565 | for (i = 0; i < cnt; i++) { | |
566 | struct irq_desc *desc = irq_to_desc(start + i); | |
567 | ||
568 | desc->owner = owner; | |
569 | } | |
12ac1d0f | 570 | bitmap_set(allocated_irqs, start, cnt); |
1f5a5b87 TG |
571 | return start; |
572 | } | |
e7bcecb7 | 573 | |
ed4dea6e | 574 | static int irq_expand_nr_irqs(unsigned int nr) |
e7bcecb7 TG |
575 | { |
576 | return -ENOMEM; | |
577 | } | |
578 | ||
f63b6a05 TG |
579 | void irq_mark_irq(unsigned int irq) |
580 | { | |
581 | mutex_lock(&sparse_irq_lock); | |
582 | bitmap_set(allocated_irqs, irq, 1); | |
583 | mutex_unlock(&sparse_irq_lock); | |
584 | } | |
585 | ||
c940e01c TG |
586 | #ifdef CONFIG_GENERIC_IRQ_LEGACY |
587 | void irq_init_desc(unsigned int irq) | |
588 | { | |
d8179bc0 | 589 | free_desc(irq); |
c940e01c TG |
590 | } |
591 | #endif | |
592 | ||
3795de23 TG |
593 | #endif /* !CONFIG_SPARSE_IRQ */ |
594 | ||
fe12bc2c TG |
595 | /** |
596 | * generic_handle_irq - Invoke the handler for a particular irq | |
597 | * @irq: The irq number to handle | |
598 | * | |
599 | */ | |
600 | int generic_handle_irq(unsigned int irq) | |
601 | { | |
602 | struct irq_desc *desc = irq_to_desc(irq); | |
603 | ||
604 | if (!desc) | |
605 | return -EINVAL; | |
bd0b9ac4 | 606 | generic_handle_irq_desc(desc); |
fe12bc2c TG |
607 | return 0; |
608 | } | |
edf76f83 | 609 | EXPORT_SYMBOL_GPL(generic_handle_irq); |
fe12bc2c | 610 | |
76ba59f8 MZ |
611 | #ifdef CONFIG_HANDLE_DOMAIN_IRQ |
612 | /** | |
613 | * __handle_domain_irq - Invoke the handler for a HW irq belonging to a domain | |
614 | * @domain: The domain where to perform the lookup | |
615 | * @hwirq: The HW irq number to convert to a logical one | |
616 | * @lookup: Whether to perform the domain lookup or not | |
617 | * @regs: Register file coming from the low-level handling code | |
618 | * | |
619 | * Returns: 0 on success, or -EINVAL if conversion has failed | |
620 | */ | |
621 | int __handle_domain_irq(struct irq_domain *domain, unsigned int hwirq, | |
622 | bool lookup, struct pt_regs *regs) | |
623 | { | |
624 | struct pt_regs *old_regs = set_irq_regs(regs); | |
625 | unsigned int irq = hwirq; | |
626 | int ret = 0; | |
627 | ||
628 | irq_enter(); | |
629 | ||
630 | #ifdef CONFIG_IRQ_DOMAIN | |
631 | if (lookup) | |
632 | irq = irq_find_mapping(domain, hwirq); | |
633 | #endif | |
634 | ||
635 | /* | |
636 | * Some hardware gives randomly wrong interrupts. Rather | |
637 | * than crashing, do something sensible. | |
638 | */ | |
639 | if (unlikely(!irq || irq >= nr_irqs)) { | |
640 | ack_bad_irq(irq); | |
641 | ret = -EINVAL; | |
642 | } else { | |
643 | generic_handle_irq(irq); | |
644 | } | |
645 | ||
646 | irq_exit(); | |
647 | set_irq_regs(old_regs); | |
648 | return ret; | |
649 | } | |
650 | #endif | |
651 | ||
1f5a5b87 TG |
652 | /* Dynamic interrupt handling */ |
653 | ||
654 | /** | |
655 | * irq_free_descs - free irq descriptors | |
656 | * @from: Start of descriptor range | |
657 | * @cnt: Number of consecutive irqs to free | |
658 | */ | |
659 | void irq_free_descs(unsigned int from, unsigned int cnt) | |
660 | { | |
1f5a5b87 TG |
661 | int i; |
662 | ||
663 | if (from >= nr_irqs || (from + cnt) > nr_irqs) | |
664 | return; | |
665 | ||
12ac1d0f | 666 | mutex_lock(&sparse_irq_lock); |
1f5a5b87 TG |
667 | for (i = 0; i < cnt; i++) |
668 | free_desc(from + i); | |
669 | ||
1f5a5b87 | 670 | bitmap_clear(allocated_irqs, from, cnt); |
a05a900a | 671 | mutex_unlock(&sparse_irq_lock); |
1f5a5b87 | 672 | } |
edf76f83 | 673 | EXPORT_SYMBOL_GPL(irq_free_descs); |
1f5a5b87 TG |
674 | |
675 | /** | |
676 | * irq_alloc_descs - allocate and initialize a range of irq descriptors | |
677 | * @irq: Allocate for specific irq number if irq >= 0 | |
678 | * @from: Start the search from this irq number | |
679 | * @cnt: Number of consecutive irqs to allocate. | |
680 | * @node: Preferred node on which the irq descriptor should be allocated | |
d522a0d1 | 681 | * @owner: Owning module (can be NULL) |
e75eafb9 TG |
682 | * @affinity: Optional pointer to an affinity mask array of size @cnt which |
683 | * hints where the irq descriptors should be allocated and which | |
684 | * default affinities to use | |
1f5a5b87 TG |
685 | * |
686 | * Returns the first irq number or error code | |
687 | */ | |
688 | int __ref | |
b6873807 | 689 | __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, |
06ee6d57 | 690 | struct module *owner, const struct cpumask *affinity) |
1f5a5b87 | 691 | { |
1f5a5b87 TG |
692 | int start, ret; |
693 | ||
694 | if (!cnt) | |
695 | return -EINVAL; | |
696 | ||
c5182b88 MB |
697 | if (irq >= 0) { |
698 | if (from > irq) | |
699 | return -EINVAL; | |
700 | from = irq; | |
62a08ae2 TG |
701 | } else { |
702 | /* | |
703 | * For interrupts which are freely allocated the | |
704 | * architecture can force a lower bound to the @from | |
705 | * argument. x86 uses this to exclude the GSI space. | |
706 | */ | |
707 | from = arch_dynirq_lower_bound(from); | |
c5182b88 MB |
708 | } |
709 | ||
a05a900a | 710 | mutex_lock(&sparse_irq_lock); |
1f5a5b87 | 711 | |
ed4dea6e YL |
712 | start = bitmap_find_next_zero_area(allocated_irqs, IRQ_BITMAP_BITS, |
713 | from, cnt, 0); | |
1f5a5b87 TG |
714 | ret = -EEXIST; |
715 | if (irq >=0 && start != irq) | |
12ac1d0f | 716 | goto unlock; |
1f5a5b87 | 717 | |
ed4dea6e YL |
718 | if (start + cnt > nr_irqs) { |
719 | ret = irq_expand_nr_irqs(start + cnt); | |
e7bcecb7 | 720 | if (ret) |
12ac1d0f | 721 | goto unlock; |
e7bcecb7 | 722 | } |
12ac1d0f TG |
723 | ret = alloc_descs(start, cnt, node, affinity, owner); |
724 | unlock: | |
a05a900a | 725 | mutex_unlock(&sparse_irq_lock); |
1f5a5b87 TG |
726 | return ret; |
727 | } | |
b6873807 | 728 | EXPORT_SYMBOL_GPL(__irq_alloc_descs); |
1f5a5b87 | 729 | |
7b6ef126 TG |
730 | #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ |
731 | /** | |
732 | * irq_alloc_hwirqs - Allocate an irq descriptor and initialize the hardware | |
733 | * @cnt: number of interrupts to allocate | |
734 | * @node: node on which to allocate | |
735 | * | |
736 | * Returns an interrupt number > 0 or 0, if the allocation fails. | |
737 | */ | |
738 | unsigned int irq_alloc_hwirqs(int cnt, int node) | |
739 | { | |
06ee6d57 | 740 | int i, irq = __irq_alloc_descs(-1, 0, cnt, node, NULL, NULL); |
7b6ef126 TG |
741 | |
742 | if (irq < 0) | |
743 | return 0; | |
744 | ||
745 | for (i = irq; cnt > 0; i++, cnt--) { | |
746 | if (arch_setup_hwirq(i, node)) | |
747 | goto err; | |
748 | irq_clear_status_flags(i, _IRQ_NOREQUEST); | |
749 | } | |
750 | return irq; | |
751 | ||
752 | err: | |
753 | for (i--; i >= irq; i--) { | |
754 | irq_set_status_flags(i, _IRQ_NOREQUEST | _IRQ_NOPROBE); | |
755 | arch_teardown_hwirq(i); | |
756 | } | |
757 | irq_free_descs(irq, cnt); | |
758 | return 0; | |
759 | } | |
760 | EXPORT_SYMBOL_GPL(irq_alloc_hwirqs); | |
761 | ||
762 | /** | |
763 | * irq_free_hwirqs - Free irq descriptor and cleanup the hardware | |
764 | * @from: Free from irq number | |
765 | * @cnt: number of interrupts to free | |
766 | * | |
767 | */ | |
768 | void irq_free_hwirqs(unsigned int from, int cnt) | |
769 | { | |
8844aad8 | 770 | int i, j; |
7b6ef126 | 771 | |
8844aad8 | 772 | for (i = from, j = cnt; j > 0; i++, j--) { |
7b6ef126 TG |
773 | irq_set_status_flags(i, _IRQ_NOREQUEST | _IRQ_NOPROBE); |
774 | arch_teardown_hwirq(i); | |
775 | } | |
776 | irq_free_descs(from, cnt); | |
777 | } | |
778 | EXPORT_SYMBOL_GPL(irq_free_hwirqs); | |
779 | #endif | |
780 | ||
a98d24b7 TG |
781 | /** |
782 | * irq_get_next_irq - get next allocated irq number | |
783 | * @offset: where to start the search | |
784 | * | |
785 | * Returns next irq number after offset or nr_irqs if none is found. | |
786 | */ | |
787 | unsigned int irq_get_next_irq(unsigned int offset) | |
788 | { | |
789 | return find_next_bit(allocated_irqs, nr_irqs, offset); | |
790 | } | |
791 | ||
d5eb4ad2 | 792 | struct irq_desc * |
31d9d9b6 MZ |
793 | __irq_get_desc_lock(unsigned int irq, unsigned long *flags, bool bus, |
794 | unsigned int check) | |
d5eb4ad2 TG |
795 | { |
796 | struct irq_desc *desc = irq_to_desc(irq); | |
797 | ||
798 | if (desc) { | |
31d9d9b6 MZ |
799 | if (check & _IRQ_DESC_CHECK) { |
800 | if ((check & _IRQ_DESC_PERCPU) && | |
801 | !irq_settings_is_per_cpu_devid(desc)) | |
802 | return NULL; | |
803 | ||
804 | if (!(check & _IRQ_DESC_PERCPU) && | |
805 | irq_settings_is_per_cpu_devid(desc)) | |
806 | return NULL; | |
807 | } | |
808 | ||
d5eb4ad2 TG |
809 | if (bus) |
810 | chip_bus_lock(desc); | |
811 | raw_spin_lock_irqsave(&desc->lock, *flags); | |
812 | } | |
813 | return desc; | |
814 | } | |
815 | ||
816 | void __irq_put_desc_unlock(struct irq_desc *desc, unsigned long flags, bool bus) | |
817 | { | |
818 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
819 | if (bus) | |
820 | chip_bus_sync_unlock(desc); | |
821 | } | |
822 | ||
222df54f MZ |
823 | int irq_set_percpu_devid_partition(unsigned int irq, |
824 | const struct cpumask *affinity) | |
31d9d9b6 MZ |
825 | { |
826 | struct irq_desc *desc = irq_to_desc(irq); | |
827 | ||
828 | if (!desc) | |
829 | return -EINVAL; | |
830 | ||
831 | if (desc->percpu_enabled) | |
832 | return -EINVAL; | |
833 | ||
834 | desc->percpu_enabled = kzalloc(sizeof(*desc->percpu_enabled), GFP_KERNEL); | |
835 | ||
836 | if (!desc->percpu_enabled) | |
837 | return -ENOMEM; | |
838 | ||
222df54f MZ |
839 | if (affinity) |
840 | desc->percpu_affinity = affinity; | |
841 | else | |
842 | desc->percpu_affinity = cpu_possible_mask; | |
843 | ||
31d9d9b6 MZ |
844 | irq_set_percpu_devid_flags(irq); |
845 | return 0; | |
846 | } | |
847 | ||
222df54f MZ |
848 | int irq_set_percpu_devid(unsigned int irq) |
849 | { | |
850 | return irq_set_percpu_devid_partition(irq, NULL); | |
851 | } | |
852 | ||
853 | int irq_get_percpu_devid_partition(unsigned int irq, struct cpumask *affinity) | |
854 | { | |
855 | struct irq_desc *desc = irq_to_desc(irq); | |
856 | ||
857 | if (!desc || !desc->percpu_enabled) | |
858 | return -EINVAL; | |
859 | ||
860 | if (affinity) | |
861 | cpumask_copy(affinity, desc->percpu_affinity); | |
862 | ||
863 | return 0; | |
864 | } | |
5ffeb050 | 865 | EXPORT_SYMBOL_GPL(irq_get_percpu_devid_partition); |
222df54f | 866 | |
792d0018 TG |
867 | void kstat_incr_irq_this_cpu(unsigned int irq) |
868 | { | |
b51bf95c | 869 | kstat_incr_irqs_this_cpu(irq_to_desc(irq)); |
792d0018 TG |
870 | } |
871 | ||
c291ee62 TG |
872 | /** |
873 | * kstat_irqs_cpu - Get the statistics for an interrupt on a cpu | |
874 | * @irq: The interrupt number | |
875 | * @cpu: The cpu number | |
876 | * | |
877 | * Returns the sum of interrupt counts on @cpu since boot for | |
878 | * @irq. The caller must ensure that the interrupt is not removed | |
879 | * concurrently. | |
880 | */ | |
3795de23 TG |
881 | unsigned int kstat_irqs_cpu(unsigned int irq, int cpu) |
882 | { | |
883 | struct irq_desc *desc = irq_to_desc(irq); | |
6c9ae009 ED |
884 | |
885 | return desc && desc->kstat_irqs ? | |
886 | *per_cpu_ptr(desc->kstat_irqs, cpu) : 0; | |
3795de23 | 887 | } |
478735e3 | 888 | |
c291ee62 TG |
889 | /** |
890 | * kstat_irqs - Get the statistics for an interrupt | |
891 | * @irq: The interrupt number | |
892 | * | |
893 | * Returns the sum of interrupt counts on all cpus since boot for | |
894 | * @irq. The caller must ensure that the interrupt is not removed | |
895 | * concurrently. | |
896 | */ | |
478735e3 KH |
897 | unsigned int kstat_irqs(unsigned int irq) |
898 | { | |
899 | struct irq_desc *desc = irq_to_desc(irq); | |
900 | int cpu; | |
5e9662fa | 901 | unsigned int sum = 0; |
478735e3 | 902 | |
6c9ae009 | 903 | if (!desc || !desc->kstat_irqs) |
478735e3 KH |
904 | return 0; |
905 | for_each_possible_cpu(cpu) | |
6c9ae009 | 906 | sum += *per_cpu_ptr(desc->kstat_irqs, cpu); |
478735e3 KH |
907 | return sum; |
908 | } | |
c291ee62 TG |
909 | |
910 | /** | |
911 | * kstat_irqs_usr - Get the statistics for an interrupt | |
912 | * @irq: The interrupt number | |
913 | * | |
914 | * Returns the sum of interrupt counts on all cpus since boot for | |
915 | * @irq. Contrary to kstat_irqs() this can be called from any | |
916 | * preemptible context. It's protected against concurrent removal of | |
917 | * an interrupt descriptor when sparse irqs are enabled. | |
918 | */ | |
919 | unsigned int kstat_irqs_usr(unsigned int irq) | |
920 | { | |
7df0b278 | 921 | unsigned int sum; |
c291ee62 TG |
922 | |
923 | irq_lock_sparse(); | |
924 | sum = kstat_irqs(irq); | |
925 | irq_unlock_sparse(); | |
926 | return sum; | |
927 | } |