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1da177e4 LT |
1 | /* |
2 | * linux/kernel/irq/manage.c | |
3 | * | |
a34db9b2 IM |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
5 | * Copyright (C) 2005-2006 Thomas Gleixner | |
1da177e4 LT |
6 | * |
7 | * This file contains driver APIs to the irq subsystem. | |
8 | */ | |
9 | ||
97fd75b7 AM |
10 | #define pr_fmt(fmt) "genirq: " fmt |
11 | ||
1da177e4 | 12 | #include <linux/irq.h> |
3aa551c9 | 13 | #include <linux/kthread.h> |
1da177e4 LT |
14 | #include <linux/module.h> |
15 | #include <linux/random.h> | |
16 | #include <linux/interrupt.h> | |
1aeb272c | 17 | #include <linux/slab.h> |
3aa551c9 | 18 | #include <linux/sched.h> |
8bd75c77 | 19 | #include <linux/sched/rt.h> |
4d1d61a6 | 20 | #include <linux/task_work.h> |
1da177e4 LT |
21 | |
22 | #include "internals.h" | |
23 | ||
8d32a307 TG |
24 | #ifdef CONFIG_IRQ_FORCED_THREADING |
25 | __read_mostly bool force_irqthreads; | |
26 | ||
27 | static int __init setup_forced_irqthreads(char *arg) | |
28 | { | |
29 | force_irqthreads = true; | |
30 | return 0; | |
31 | } | |
32 | early_param("threadirqs", setup_forced_irqthreads); | |
33 | #endif | |
34 | ||
18258f72 | 35 | static void __synchronize_hardirq(struct irq_desc *desc) |
1da177e4 | 36 | { |
32f4125e | 37 | bool inprogress; |
1da177e4 | 38 | |
a98ce5c6 HX |
39 | do { |
40 | unsigned long flags; | |
41 | ||
42 | /* | |
43 | * Wait until we're out of the critical section. This might | |
44 | * give the wrong answer due to the lack of memory barriers. | |
45 | */ | |
32f4125e | 46 | while (irqd_irq_inprogress(&desc->irq_data)) |
a98ce5c6 HX |
47 | cpu_relax(); |
48 | ||
49 | /* Ok, that indicated we're done: double-check carefully. */ | |
239007b8 | 50 | raw_spin_lock_irqsave(&desc->lock, flags); |
32f4125e | 51 | inprogress = irqd_irq_inprogress(&desc->irq_data); |
239007b8 | 52 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
a98ce5c6 HX |
53 | |
54 | /* Oops, that failed? */ | |
32f4125e | 55 | } while (inprogress); |
18258f72 TG |
56 | } |
57 | ||
58 | /** | |
59 | * synchronize_hardirq - wait for pending hard IRQ handlers (on other CPUs) | |
60 | * @irq: interrupt number to wait for | |
61 | * | |
62 | * This function waits for any pending hard IRQ handlers for this | |
63 | * interrupt to complete before returning. If you use this | |
64 | * function while holding a resource the IRQ handler may need you | |
65 | * will deadlock. It does not take associated threaded handlers | |
66 | * into account. | |
67 | * | |
68 | * Do not use this for shutdown scenarios where you must be sure | |
69 | * that all parts (hardirq and threaded handler) have completed. | |
70 | * | |
71 | * This function may be called - with care - from IRQ context. | |
72 | */ | |
73 | void synchronize_hardirq(unsigned int irq) | |
74 | { | |
75 | struct irq_desc *desc = irq_to_desc(irq); | |
3aa551c9 | 76 | |
18258f72 TG |
77 | if (desc) |
78 | __synchronize_hardirq(desc); | |
79 | } | |
80 | EXPORT_SYMBOL(synchronize_hardirq); | |
81 | ||
82 | /** | |
83 | * synchronize_irq - wait for pending IRQ handlers (on other CPUs) | |
84 | * @irq: interrupt number to wait for | |
85 | * | |
86 | * This function waits for any pending IRQ handlers for this interrupt | |
87 | * to complete before returning. If you use this function while | |
88 | * holding a resource the IRQ handler may need you will deadlock. | |
89 | * | |
90 | * This function may be called - with care - from IRQ context. | |
91 | */ | |
92 | void synchronize_irq(unsigned int irq) | |
93 | { | |
94 | struct irq_desc *desc = irq_to_desc(irq); | |
95 | ||
96 | if (desc) { | |
97 | __synchronize_hardirq(desc); | |
98 | /* | |
99 | * We made sure that no hardirq handler is | |
100 | * running. Now verify that no threaded handlers are | |
101 | * active. | |
102 | */ | |
103 | wait_event(desc->wait_for_threads, | |
104 | !atomic_read(&desc->threads_active)); | |
105 | } | |
1da177e4 | 106 | } |
1da177e4 LT |
107 | EXPORT_SYMBOL(synchronize_irq); |
108 | ||
3aa551c9 TG |
109 | #ifdef CONFIG_SMP |
110 | cpumask_var_t irq_default_affinity; | |
111 | ||
771ee3b0 TG |
112 | /** |
113 | * irq_can_set_affinity - Check if the affinity of a given irq can be set | |
114 | * @irq: Interrupt to check | |
115 | * | |
116 | */ | |
117 | int irq_can_set_affinity(unsigned int irq) | |
118 | { | |
08678b08 | 119 | struct irq_desc *desc = irq_to_desc(irq); |
771ee3b0 | 120 | |
bce43032 TG |
121 | if (!desc || !irqd_can_balance(&desc->irq_data) || |
122 | !desc->irq_data.chip || !desc->irq_data.chip->irq_set_affinity) | |
771ee3b0 TG |
123 | return 0; |
124 | ||
125 | return 1; | |
126 | } | |
127 | ||
591d2fb0 TG |
128 | /** |
129 | * irq_set_thread_affinity - Notify irq threads to adjust affinity | |
130 | * @desc: irq descriptor which has affitnity changed | |
131 | * | |
132 | * We just set IRQTF_AFFINITY and delegate the affinity setting | |
133 | * to the interrupt thread itself. We can not call | |
134 | * set_cpus_allowed_ptr() here as we hold desc->lock and this | |
135 | * code can be called from hard interrupt context. | |
136 | */ | |
137 | void irq_set_thread_affinity(struct irq_desc *desc) | |
3aa551c9 TG |
138 | { |
139 | struct irqaction *action = desc->action; | |
140 | ||
141 | while (action) { | |
142 | if (action->thread) | |
591d2fb0 | 143 | set_bit(IRQTF_AFFINITY, &action->thread_flags); |
3aa551c9 TG |
144 | action = action->next; |
145 | } | |
146 | } | |
147 | ||
1fa46f1f | 148 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
0ef5ca1e | 149 | static inline bool irq_can_move_pcntxt(struct irq_data *data) |
1fa46f1f | 150 | { |
0ef5ca1e | 151 | return irqd_can_move_in_process_context(data); |
1fa46f1f | 152 | } |
0ef5ca1e | 153 | static inline bool irq_move_pending(struct irq_data *data) |
1fa46f1f | 154 | { |
0ef5ca1e | 155 | return irqd_is_setaffinity_pending(data); |
1fa46f1f TG |
156 | } |
157 | static inline void | |
158 | irq_copy_pending(struct irq_desc *desc, const struct cpumask *mask) | |
159 | { | |
160 | cpumask_copy(desc->pending_mask, mask); | |
161 | } | |
162 | static inline void | |
163 | irq_get_pending(struct cpumask *mask, struct irq_desc *desc) | |
164 | { | |
165 | cpumask_copy(mask, desc->pending_mask); | |
166 | } | |
167 | #else | |
0ef5ca1e | 168 | static inline bool irq_can_move_pcntxt(struct irq_data *data) { return true; } |
cd22c0e4 | 169 | static inline bool irq_move_pending(struct irq_data *data) { return false; } |
1fa46f1f TG |
170 | static inline void |
171 | irq_copy_pending(struct irq_desc *desc, const struct cpumask *mask) { } | |
172 | static inline void | |
173 | irq_get_pending(struct cpumask *mask, struct irq_desc *desc) { } | |
174 | #endif | |
175 | ||
818b0f3b JL |
176 | int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask, |
177 | bool force) | |
178 | { | |
179 | struct irq_desc *desc = irq_data_to_desc(data); | |
180 | struct irq_chip *chip = irq_data_get_irq_chip(data); | |
181 | int ret; | |
182 | ||
183 | ret = chip->irq_set_affinity(data, mask, false); | |
184 | switch (ret) { | |
185 | case IRQ_SET_MASK_OK: | |
186 | cpumask_copy(data->affinity, mask); | |
187 | case IRQ_SET_MASK_OK_NOCOPY: | |
188 | irq_set_thread_affinity(desc); | |
189 | ret = 0; | |
190 | } | |
191 | ||
192 | return ret; | |
193 | } | |
194 | ||
c2d0c555 | 195 | int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *mask) |
771ee3b0 | 196 | { |
c2d0c555 DD |
197 | struct irq_chip *chip = irq_data_get_irq_chip(data); |
198 | struct irq_desc *desc = irq_data_to_desc(data); | |
1fa46f1f | 199 | int ret = 0; |
771ee3b0 | 200 | |
c2d0c555 | 201 | if (!chip || !chip->irq_set_affinity) |
771ee3b0 TG |
202 | return -EINVAL; |
203 | ||
0ef5ca1e | 204 | if (irq_can_move_pcntxt(data)) { |
818b0f3b | 205 | ret = irq_do_set_affinity(data, mask, false); |
1fa46f1f | 206 | } else { |
c2d0c555 | 207 | irqd_set_move_pending(data); |
1fa46f1f | 208 | irq_copy_pending(desc, mask); |
57b150cc | 209 | } |
1fa46f1f | 210 | |
cd7eab44 BH |
211 | if (desc->affinity_notify) { |
212 | kref_get(&desc->affinity_notify->kref); | |
213 | schedule_work(&desc->affinity_notify->work); | |
214 | } | |
c2d0c555 DD |
215 | irqd_set(data, IRQD_AFFINITY_SET); |
216 | ||
217 | return ret; | |
218 | } | |
219 | ||
220 | /** | |
221 | * irq_set_affinity - Set the irq affinity of a given irq | |
222 | * @irq: Interrupt to set affinity | |
30398bf6 | 223 | * @mask: cpumask |
c2d0c555 DD |
224 | * |
225 | */ | |
226 | int irq_set_affinity(unsigned int irq, const struct cpumask *mask) | |
227 | { | |
228 | struct irq_desc *desc = irq_to_desc(irq); | |
229 | unsigned long flags; | |
230 | int ret; | |
231 | ||
232 | if (!desc) | |
233 | return -EINVAL; | |
234 | ||
235 | raw_spin_lock_irqsave(&desc->lock, flags); | |
236 | ret = __irq_set_affinity_locked(irq_desc_get_irq_data(desc), mask); | |
239007b8 | 237 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1fa46f1f | 238 | return ret; |
771ee3b0 TG |
239 | } |
240 | ||
e7a297b0 PWJ |
241 | int irq_set_affinity_hint(unsigned int irq, const struct cpumask *m) |
242 | { | |
e7a297b0 | 243 | unsigned long flags; |
31d9d9b6 | 244 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
e7a297b0 PWJ |
245 | |
246 | if (!desc) | |
247 | return -EINVAL; | |
e7a297b0 | 248 | desc->affinity_hint = m; |
02725e74 | 249 | irq_put_desc_unlock(desc, flags); |
e7a297b0 PWJ |
250 | return 0; |
251 | } | |
252 | EXPORT_SYMBOL_GPL(irq_set_affinity_hint); | |
253 | ||
cd7eab44 BH |
254 | static void irq_affinity_notify(struct work_struct *work) |
255 | { | |
256 | struct irq_affinity_notify *notify = | |
257 | container_of(work, struct irq_affinity_notify, work); | |
258 | struct irq_desc *desc = irq_to_desc(notify->irq); | |
259 | cpumask_var_t cpumask; | |
260 | unsigned long flags; | |
261 | ||
1fa46f1f | 262 | if (!desc || !alloc_cpumask_var(&cpumask, GFP_KERNEL)) |
cd7eab44 BH |
263 | goto out; |
264 | ||
265 | raw_spin_lock_irqsave(&desc->lock, flags); | |
0ef5ca1e | 266 | if (irq_move_pending(&desc->irq_data)) |
1fa46f1f | 267 | irq_get_pending(cpumask, desc); |
cd7eab44 | 268 | else |
1fb0ef31 | 269 | cpumask_copy(cpumask, desc->irq_data.affinity); |
cd7eab44 BH |
270 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
271 | ||
272 | notify->notify(notify, cpumask); | |
273 | ||
274 | free_cpumask_var(cpumask); | |
275 | out: | |
276 | kref_put(¬ify->kref, notify->release); | |
277 | } | |
278 | ||
279 | /** | |
280 | * irq_set_affinity_notifier - control notification of IRQ affinity changes | |
281 | * @irq: Interrupt for which to enable/disable notification | |
282 | * @notify: Context for notification, or %NULL to disable | |
283 | * notification. Function pointers must be initialised; | |
284 | * the other fields will be initialised by this function. | |
285 | * | |
286 | * Must be called in process context. Notification may only be enabled | |
287 | * after the IRQ is allocated and must be disabled before the IRQ is | |
288 | * freed using free_irq(). | |
289 | */ | |
290 | int | |
291 | irq_set_affinity_notifier(unsigned int irq, struct irq_affinity_notify *notify) | |
292 | { | |
293 | struct irq_desc *desc = irq_to_desc(irq); | |
294 | struct irq_affinity_notify *old_notify; | |
295 | unsigned long flags; | |
296 | ||
297 | /* The release function is promised process context */ | |
298 | might_sleep(); | |
299 | ||
300 | if (!desc) | |
301 | return -EINVAL; | |
302 | ||
303 | /* Complete initialisation of *notify */ | |
304 | if (notify) { | |
305 | notify->irq = irq; | |
306 | kref_init(¬ify->kref); | |
307 | INIT_WORK(¬ify->work, irq_affinity_notify); | |
308 | } | |
309 | ||
310 | raw_spin_lock_irqsave(&desc->lock, flags); | |
311 | old_notify = desc->affinity_notify; | |
312 | desc->affinity_notify = notify; | |
313 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
314 | ||
315 | if (old_notify) | |
316 | kref_put(&old_notify->kref, old_notify->release); | |
317 | ||
318 | return 0; | |
319 | } | |
320 | EXPORT_SYMBOL_GPL(irq_set_affinity_notifier); | |
321 | ||
18404756 MK |
322 | #ifndef CONFIG_AUTO_IRQ_AFFINITY |
323 | /* | |
324 | * Generic version of the affinity autoselector. | |
325 | */ | |
3b8249e7 TG |
326 | static int |
327 | setup_affinity(unsigned int irq, struct irq_desc *desc, struct cpumask *mask) | |
18404756 | 328 | { |
569bda8d | 329 | struct cpumask *set = irq_default_affinity; |
818b0f3b | 330 | int node = desc->irq_data.node; |
569bda8d | 331 | |
b008207c | 332 | /* Excludes PER_CPU and NO_BALANCE interrupts */ |
18404756 MK |
333 | if (!irq_can_set_affinity(irq)) |
334 | return 0; | |
335 | ||
f6d87f4b TG |
336 | /* |
337 | * Preserve an userspace affinity setup, but make sure that | |
338 | * one of the targets is online. | |
339 | */ | |
2bdd1055 | 340 | if (irqd_has_set(&desc->irq_data, IRQD_AFFINITY_SET)) { |
569bda8d TG |
341 | if (cpumask_intersects(desc->irq_data.affinity, |
342 | cpu_online_mask)) | |
343 | set = desc->irq_data.affinity; | |
0c6f8a8b | 344 | else |
2bdd1055 | 345 | irqd_clear(&desc->irq_data, IRQD_AFFINITY_SET); |
f6d87f4b | 346 | } |
18404756 | 347 | |
3b8249e7 | 348 | cpumask_and(mask, cpu_online_mask, set); |
241fc640 PB |
349 | if (node != NUMA_NO_NODE) { |
350 | const struct cpumask *nodemask = cpumask_of_node(node); | |
351 | ||
352 | /* make sure at least one of the cpus in nodemask is online */ | |
353 | if (cpumask_intersects(mask, nodemask)) | |
354 | cpumask_and(mask, mask, nodemask); | |
355 | } | |
818b0f3b | 356 | irq_do_set_affinity(&desc->irq_data, mask, false); |
18404756 MK |
357 | return 0; |
358 | } | |
f6d87f4b | 359 | #else |
3b8249e7 TG |
360 | static inline int |
361 | setup_affinity(unsigned int irq, struct irq_desc *d, struct cpumask *mask) | |
f6d87f4b TG |
362 | { |
363 | return irq_select_affinity(irq); | |
364 | } | |
18404756 MK |
365 | #endif |
366 | ||
f6d87f4b TG |
367 | /* |
368 | * Called when affinity is set via /proc/irq | |
369 | */ | |
3b8249e7 | 370 | int irq_select_affinity_usr(unsigned int irq, struct cpumask *mask) |
f6d87f4b TG |
371 | { |
372 | struct irq_desc *desc = irq_to_desc(irq); | |
373 | unsigned long flags; | |
374 | int ret; | |
375 | ||
239007b8 | 376 | raw_spin_lock_irqsave(&desc->lock, flags); |
3b8249e7 | 377 | ret = setup_affinity(irq, desc, mask); |
239007b8 | 378 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
f6d87f4b TG |
379 | return ret; |
380 | } | |
381 | ||
382 | #else | |
3b8249e7 TG |
383 | static inline int |
384 | setup_affinity(unsigned int irq, struct irq_desc *desc, struct cpumask *mask) | |
f6d87f4b TG |
385 | { |
386 | return 0; | |
387 | } | |
1da177e4 LT |
388 | #endif |
389 | ||
0a0c5168 RW |
390 | void __disable_irq(struct irq_desc *desc, unsigned int irq, bool suspend) |
391 | { | |
392 | if (suspend) { | |
685fd0b4 | 393 | if (!desc->action || (desc->action->flags & IRQF_NO_SUSPEND)) |
0a0c5168 | 394 | return; |
c531e836 | 395 | desc->istate |= IRQS_SUSPENDED; |
0a0c5168 RW |
396 | } |
397 | ||
3aae994f | 398 | if (!desc->depth++) |
87923470 | 399 | irq_disable(desc); |
0a0c5168 RW |
400 | } |
401 | ||
02725e74 TG |
402 | static int __disable_irq_nosync(unsigned int irq) |
403 | { | |
404 | unsigned long flags; | |
31d9d9b6 | 405 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
02725e74 TG |
406 | |
407 | if (!desc) | |
408 | return -EINVAL; | |
409 | __disable_irq(desc, irq, false); | |
410 | irq_put_desc_busunlock(desc, flags); | |
411 | return 0; | |
412 | } | |
413 | ||
1da177e4 LT |
414 | /** |
415 | * disable_irq_nosync - disable an irq without waiting | |
416 | * @irq: Interrupt to disable | |
417 | * | |
418 | * Disable the selected interrupt line. Disables and Enables are | |
419 | * nested. | |
420 | * Unlike disable_irq(), this function does not ensure existing | |
421 | * instances of the IRQ handler have completed before returning. | |
422 | * | |
423 | * This function may be called from IRQ context. | |
424 | */ | |
425 | void disable_irq_nosync(unsigned int irq) | |
426 | { | |
02725e74 | 427 | __disable_irq_nosync(irq); |
1da177e4 | 428 | } |
1da177e4 LT |
429 | EXPORT_SYMBOL(disable_irq_nosync); |
430 | ||
431 | /** | |
432 | * disable_irq - disable an irq and wait for completion | |
433 | * @irq: Interrupt to disable | |
434 | * | |
435 | * Disable the selected interrupt line. Enables and Disables are | |
436 | * nested. | |
437 | * This function waits for any pending IRQ handlers for this interrupt | |
438 | * to complete before returning. If you use this function while | |
439 | * holding a resource the IRQ handler may need you will deadlock. | |
440 | * | |
441 | * This function may be called - with care - from IRQ context. | |
442 | */ | |
443 | void disable_irq(unsigned int irq) | |
444 | { | |
02725e74 | 445 | if (!__disable_irq_nosync(irq)) |
1da177e4 LT |
446 | synchronize_irq(irq); |
447 | } | |
1da177e4 LT |
448 | EXPORT_SYMBOL(disable_irq); |
449 | ||
0a0c5168 | 450 | void __enable_irq(struct irq_desc *desc, unsigned int irq, bool resume) |
1adb0850 | 451 | { |
dc5f219e | 452 | if (resume) { |
c531e836 | 453 | if (!(desc->istate & IRQS_SUSPENDED)) { |
dc5f219e TG |
454 | if (!desc->action) |
455 | return; | |
456 | if (!(desc->action->flags & IRQF_FORCE_RESUME)) | |
457 | return; | |
458 | /* Pretend that it got disabled ! */ | |
459 | desc->depth++; | |
460 | } | |
c531e836 | 461 | desc->istate &= ~IRQS_SUSPENDED; |
dc5f219e | 462 | } |
0a0c5168 | 463 | |
1adb0850 TG |
464 | switch (desc->depth) { |
465 | case 0: | |
0a0c5168 | 466 | err_out: |
b8c512f6 | 467 | WARN(1, KERN_WARNING "Unbalanced enable for IRQ %d\n", irq); |
1adb0850 TG |
468 | break; |
469 | case 1: { | |
c531e836 | 470 | if (desc->istate & IRQS_SUSPENDED) |
0a0c5168 | 471 | goto err_out; |
1adb0850 | 472 | /* Prevent probing on this irq: */ |
1ccb4e61 | 473 | irq_settings_set_noprobe(desc); |
3aae994f | 474 | irq_enable(desc); |
1adb0850 TG |
475 | check_irq_resend(desc, irq); |
476 | /* fall-through */ | |
477 | } | |
478 | default: | |
479 | desc->depth--; | |
480 | } | |
481 | } | |
482 | ||
1da177e4 LT |
483 | /** |
484 | * enable_irq - enable handling of an irq | |
485 | * @irq: Interrupt to enable | |
486 | * | |
487 | * Undoes the effect of one call to disable_irq(). If this | |
488 | * matches the last disable, processing of interrupts on this | |
489 | * IRQ line is re-enabled. | |
490 | * | |
70aedd24 | 491 | * This function may be called from IRQ context only when |
6b8ff312 | 492 | * desc->irq_data.chip->bus_lock and desc->chip->bus_sync_unlock are NULL ! |
1da177e4 LT |
493 | */ |
494 | void enable_irq(unsigned int irq) | |
495 | { | |
1da177e4 | 496 | unsigned long flags; |
31d9d9b6 | 497 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
1da177e4 | 498 | |
7d94f7ca | 499 | if (!desc) |
c2b5a251 | 500 | return; |
50f7c032 TG |
501 | if (WARN(!desc->irq_data.chip, |
502 | KERN_ERR "enable_irq before setup/request_irq: irq %u\n", irq)) | |
02725e74 | 503 | goto out; |
2656c366 | 504 | |
0a0c5168 | 505 | __enable_irq(desc, irq, false); |
02725e74 TG |
506 | out: |
507 | irq_put_desc_busunlock(desc, flags); | |
1da177e4 | 508 | } |
1da177e4 LT |
509 | EXPORT_SYMBOL(enable_irq); |
510 | ||
0c5d1eb7 | 511 | static int set_irq_wake_real(unsigned int irq, unsigned int on) |
2db87321 | 512 | { |
08678b08 | 513 | struct irq_desc *desc = irq_to_desc(irq); |
2db87321 UKK |
514 | int ret = -ENXIO; |
515 | ||
60f96b41 SS |
516 | if (irq_desc_get_chip(desc)->flags & IRQCHIP_SKIP_SET_WAKE) |
517 | return 0; | |
518 | ||
2f7e99bb TG |
519 | if (desc->irq_data.chip->irq_set_wake) |
520 | ret = desc->irq_data.chip->irq_set_wake(&desc->irq_data, on); | |
2db87321 UKK |
521 | |
522 | return ret; | |
523 | } | |
524 | ||
ba9a2331 | 525 | /** |
a0cd9ca2 | 526 | * irq_set_irq_wake - control irq power management wakeup |
ba9a2331 TG |
527 | * @irq: interrupt to control |
528 | * @on: enable/disable power management wakeup | |
529 | * | |
15a647eb DB |
530 | * Enable/disable power management wakeup mode, which is |
531 | * disabled by default. Enables and disables must match, | |
532 | * just as they match for non-wakeup mode support. | |
533 | * | |
534 | * Wakeup mode lets this IRQ wake the system from sleep | |
535 | * states like "suspend to RAM". | |
ba9a2331 | 536 | */ |
a0cd9ca2 | 537 | int irq_set_irq_wake(unsigned int irq, unsigned int on) |
ba9a2331 | 538 | { |
ba9a2331 | 539 | unsigned long flags; |
31d9d9b6 | 540 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
2db87321 | 541 | int ret = 0; |
ba9a2331 | 542 | |
13863a66 JJ |
543 | if (!desc) |
544 | return -EINVAL; | |
545 | ||
15a647eb DB |
546 | /* wakeup-capable irqs can be shared between drivers that |
547 | * don't need to have the same sleep mode behaviors. | |
548 | */ | |
15a647eb | 549 | if (on) { |
2db87321 UKK |
550 | if (desc->wake_depth++ == 0) { |
551 | ret = set_irq_wake_real(irq, on); | |
552 | if (ret) | |
553 | desc->wake_depth = 0; | |
554 | else | |
7f94226f | 555 | irqd_set(&desc->irq_data, IRQD_WAKEUP_STATE); |
2db87321 | 556 | } |
15a647eb DB |
557 | } else { |
558 | if (desc->wake_depth == 0) { | |
7a2c4770 | 559 | WARN(1, "Unbalanced IRQ %d wake disable\n", irq); |
2db87321 UKK |
560 | } else if (--desc->wake_depth == 0) { |
561 | ret = set_irq_wake_real(irq, on); | |
562 | if (ret) | |
563 | desc->wake_depth = 1; | |
564 | else | |
7f94226f | 565 | irqd_clear(&desc->irq_data, IRQD_WAKEUP_STATE); |
2db87321 | 566 | } |
15a647eb | 567 | } |
02725e74 | 568 | irq_put_desc_busunlock(desc, flags); |
ba9a2331 TG |
569 | return ret; |
570 | } | |
a0cd9ca2 | 571 | EXPORT_SYMBOL(irq_set_irq_wake); |
ba9a2331 | 572 | |
1da177e4 LT |
573 | /* |
574 | * Internal function that tells the architecture code whether a | |
575 | * particular irq has been exclusively allocated or is available | |
576 | * for driver use. | |
577 | */ | |
578 | int can_request_irq(unsigned int irq, unsigned long irqflags) | |
579 | { | |
cc8c3b78 | 580 | unsigned long flags; |
31d9d9b6 | 581 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
02725e74 | 582 | int canrequest = 0; |
1da177e4 | 583 | |
7d94f7ca YL |
584 | if (!desc) |
585 | return 0; | |
586 | ||
02725e74 | 587 | if (irq_settings_can_request(desc)) { |
2779db8d BH |
588 | if (!desc->action || |
589 | irqflags & desc->action->flags & IRQF_SHARED) | |
590 | canrequest = 1; | |
02725e74 TG |
591 | } |
592 | irq_put_desc_unlock(desc, flags); | |
593 | return canrequest; | |
1da177e4 LT |
594 | } |
595 | ||
0c5d1eb7 | 596 | int __irq_set_trigger(struct irq_desc *desc, unsigned int irq, |
b2ba2c30 | 597 | unsigned long flags) |
82736f4d | 598 | { |
6b8ff312 | 599 | struct irq_chip *chip = desc->irq_data.chip; |
d4d5e089 | 600 | int ret, unmask = 0; |
82736f4d | 601 | |
b2ba2c30 | 602 | if (!chip || !chip->irq_set_type) { |
82736f4d UKK |
603 | /* |
604 | * IRQF_TRIGGER_* but the PIC does not support multiple | |
605 | * flow-types? | |
606 | */ | |
97fd75b7 | 607 | pr_debug("No set_type function for IRQ %d (%s)\n", irq, |
f5d89470 | 608 | chip ? (chip->name ? : "unknown") : "unknown"); |
82736f4d UKK |
609 | return 0; |
610 | } | |
611 | ||
876dbd4c | 612 | flags &= IRQ_TYPE_SENSE_MASK; |
d4d5e089 TG |
613 | |
614 | if (chip->flags & IRQCHIP_SET_TYPE_MASKED) { | |
32f4125e | 615 | if (!irqd_irq_masked(&desc->irq_data)) |
d4d5e089 | 616 | mask_irq(desc); |
32f4125e | 617 | if (!irqd_irq_disabled(&desc->irq_data)) |
d4d5e089 TG |
618 | unmask = 1; |
619 | } | |
620 | ||
f2b662da | 621 | /* caller masked out all except trigger mode flags */ |
b2ba2c30 | 622 | ret = chip->irq_set_type(&desc->irq_data, flags); |
82736f4d | 623 | |
876dbd4c TG |
624 | switch (ret) { |
625 | case IRQ_SET_MASK_OK: | |
626 | irqd_clear(&desc->irq_data, IRQD_TRIGGER_MASK); | |
627 | irqd_set(&desc->irq_data, flags); | |
628 | ||
629 | case IRQ_SET_MASK_OK_NOCOPY: | |
630 | flags = irqd_get_trigger_type(&desc->irq_data); | |
631 | irq_settings_set_trigger_mask(desc, flags); | |
632 | irqd_clear(&desc->irq_data, IRQD_LEVEL); | |
633 | irq_settings_clr_level(desc); | |
634 | if (flags & IRQ_TYPE_LEVEL_MASK) { | |
635 | irq_settings_set_level(desc); | |
636 | irqd_set(&desc->irq_data, IRQD_LEVEL); | |
637 | } | |
46732475 | 638 | |
d4d5e089 | 639 | ret = 0; |
8fff39e0 | 640 | break; |
876dbd4c | 641 | default: |
97fd75b7 | 642 | pr_err("Setting trigger mode %lu for irq %u failed (%pF)\n", |
876dbd4c | 643 | flags, irq, chip->irq_set_type); |
0c5d1eb7 | 644 | } |
d4d5e089 TG |
645 | if (unmask) |
646 | unmask_irq(desc); | |
82736f4d UKK |
647 | return ret; |
648 | } | |
649 | ||
293a7a0a TG |
650 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
651 | int irq_set_parent(int irq, int parent_irq) | |
652 | { | |
653 | unsigned long flags; | |
654 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | |
655 | ||
656 | if (!desc) | |
657 | return -EINVAL; | |
658 | ||
659 | desc->parent_irq = parent_irq; | |
660 | ||
661 | irq_put_desc_unlock(desc, flags); | |
662 | return 0; | |
663 | } | |
664 | #endif | |
665 | ||
b25c340c TG |
666 | /* |
667 | * Default primary interrupt handler for threaded interrupts. Is | |
668 | * assigned as primary handler when request_threaded_irq is called | |
669 | * with handler == NULL. Useful for oneshot interrupts. | |
670 | */ | |
671 | static irqreturn_t irq_default_primary_handler(int irq, void *dev_id) | |
672 | { | |
673 | return IRQ_WAKE_THREAD; | |
674 | } | |
675 | ||
399b5da2 TG |
676 | /* |
677 | * Primary handler for nested threaded interrupts. Should never be | |
678 | * called. | |
679 | */ | |
680 | static irqreturn_t irq_nested_primary_handler(int irq, void *dev_id) | |
681 | { | |
682 | WARN(1, "Primary handler called for nested irq %d\n", irq); | |
683 | return IRQ_NONE; | |
684 | } | |
685 | ||
3aa551c9 TG |
686 | static int irq_wait_for_interrupt(struct irqaction *action) |
687 | { | |
550acb19 IY |
688 | set_current_state(TASK_INTERRUPTIBLE); |
689 | ||
3aa551c9 | 690 | while (!kthread_should_stop()) { |
f48fe81e TG |
691 | |
692 | if (test_and_clear_bit(IRQTF_RUNTHREAD, | |
693 | &action->thread_flags)) { | |
3aa551c9 TG |
694 | __set_current_state(TASK_RUNNING); |
695 | return 0; | |
f48fe81e TG |
696 | } |
697 | schedule(); | |
550acb19 | 698 | set_current_state(TASK_INTERRUPTIBLE); |
3aa551c9 | 699 | } |
550acb19 | 700 | __set_current_state(TASK_RUNNING); |
3aa551c9 TG |
701 | return -1; |
702 | } | |
703 | ||
b25c340c TG |
704 | /* |
705 | * Oneshot interrupts keep the irq line masked until the threaded | |
706 | * handler finished. unmask if the interrupt has not been disabled and | |
707 | * is marked MASKED. | |
708 | */ | |
b5faba21 | 709 | static void irq_finalize_oneshot(struct irq_desc *desc, |
f3f79e38 | 710 | struct irqaction *action) |
b25c340c | 711 | { |
b5faba21 TG |
712 | if (!(desc->istate & IRQS_ONESHOT)) |
713 | return; | |
0b1adaa0 | 714 | again: |
3876ec9e | 715 | chip_bus_lock(desc); |
239007b8 | 716 | raw_spin_lock_irq(&desc->lock); |
0b1adaa0 TG |
717 | |
718 | /* | |
719 | * Implausible though it may be we need to protect us against | |
720 | * the following scenario: | |
721 | * | |
722 | * The thread is faster done than the hard interrupt handler | |
723 | * on the other CPU. If we unmask the irq line then the | |
724 | * interrupt can come in again and masks the line, leaves due | |
009b4c3b | 725 | * to IRQS_INPROGRESS and the irq line is masked forever. |
b5faba21 TG |
726 | * |
727 | * This also serializes the state of shared oneshot handlers | |
728 | * versus "desc->threads_onehsot |= action->thread_mask;" in | |
729 | * irq_wake_thread(). See the comment there which explains the | |
730 | * serialization. | |
0b1adaa0 | 731 | */ |
32f4125e | 732 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) { |
0b1adaa0 | 733 | raw_spin_unlock_irq(&desc->lock); |
3876ec9e | 734 | chip_bus_sync_unlock(desc); |
0b1adaa0 TG |
735 | cpu_relax(); |
736 | goto again; | |
737 | } | |
738 | ||
b5faba21 TG |
739 | /* |
740 | * Now check again, whether the thread should run. Otherwise | |
741 | * we would clear the threads_oneshot bit of this thread which | |
742 | * was just set. | |
743 | */ | |
f3f79e38 | 744 | if (test_bit(IRQTF_RUNTHREAD, &action->thread_flags)) |
b5faba21 TG |
745 | goto out_unlock; |
746 | ||
747 | desc->threads_oneshot &= ~action->thread_mask; | |
748 | ||
32f4125e TG |
749 | if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && |
750 | irqd_irq_masked(&desc->irq_data)) | |
328a4978 | 751 | unmask_threaded_irq(desc); |
32f4125e | 752 | |
b5faba21 | 753 | out_unlock: |
239007b8 | 754 | raw_spin_unlock_irq(&desc->lock); |
3876ec9e | 755 | chip_bus_sync_unlock(desc); |
b25c340c TG |
756 | } |
757 | ||
61f38261 | 758 | #ifdef CONFIG_SMP |
591d2fb0 | 759 | /* |
b04c644e | 760 | * Check whether we need to change the affinity of the interrupt thread. |
591d2fb0 TG |
761 | */ |
762 | static void | |
763 | irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) | |
764 | { | |
765 | cpumask_var_t mask; | |
04aa530e | 766 | bool valid = true; |
591d2fb0 TG |
767 | |
768 | if (!test_and_clear_bit(IRQTF_AFFINITY, &action->thread_flags)) | |
769 | return; | |
770 | ||
771 | /* | |
772 | * In case we are out of memory we set IRQTF_AFFINITY again and | |
773 | * try again next time | |
774 | */ | |
775 | if (!alloc_cpumask_var(&mask, GFP_KERNEL)) { | |
776 | set_bit(IRQTF_AFFINITY, &action->thread_flags); | |
777 | return; | |
778 | } | |
779 | ||
239007b8 | 780 | raw_spin_lock_irq(&desc->lock); |
04aa530e TG |
781 | /* |
782 | * This code is triggered unconditionally. Check the affinity | |
783 | * mask pointer. For CPU_MASK_OFFSTACK=n this is optimized out. | |
784 | */ | |
785 | if (desc->irq_data.affinity) | |
786 | cpumask_copy(mask, desc->irq_data.affinity); | |
787 | else | |
788 | valid = false; | |
239007b8 | 789 | raw_spin_unlock_irq(&desc->lock); |
591d2fb0 | 790 | |
04aa530e TG |
791 | if (valid) |
792 | set_cpus_allowed_ptr(current, mask); | |
591d2fb0 TG |
793 | free_cpumask_var(mask); |
794 | } | |
61f38261 BP |
795 | #else |
796 | static inline void | |
797 | irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) { } | |
798 | #endif | |
591d2fb0 | 799 | |
8d32a307 TG |
800 | /* |
801 | * Interrupts which are not explicitely requested as threaded | |
802 | * interrupts rely on the implicit bh/preempt disable of the hard irq | |
803 | * context. So we need to disable bh here to avoid deadlocks and other | |
804 | * side effects. | |
805 | */ | |
3a43e05f | 806 | static irqreturn_t |
8d32a307 TG |
807 | irq_forced_thread_fn(struct irq_desc *desc, struct irqaction *action) |
808 | { | |
3a43e05f SAS |
809 | irqreturn_t ret; |
810 | ||
8d32a307 | 811 | local_bh_disable(); |
3a43e05f | 812 | ret = action->thread_fn(action->irq, action->dev_id); |
f3f79e38 | 813 | irq_finalize_oneshot(desc, action); |
8d32a307 | 814 | local_bh_enable(); |
3a43e05f | 815 | return ret; |
8d32a307 TG |
816 | } |
817 | ||
818 | /* | |
f788e7bf | 819 | * Interrupts explicitly requested as threaded interrupts want to be |
8d32a307 TG |
820 | * preemtible - many of them need to sleep and wait for slow busses to |
821 | * complete. | |
822 | */ | |
3a43e05f SAS |
823 | static irqreturn_t irq_thread_fn(struct irq_desc *desc, |
824 | struct irqaction *action) | |
8d32a307 | 825 | { |
3a43e05f SAS |
826 | irqreturn_t ret; |
827 | ||
828 | ret = action->thread_fn(action->irq, action->dev_id); | |
f3f79e38 | 829 | irq_finalize_oneshot(desc, action); |
3a43e05f | 830 | return ret; |
8d32a307 TG |
831 | } |
832 | ||
7140ea19 IY |
833 | static void wake_threads_waitq(struct irq_desc *desc) |
834 | { | |
c685689f | 835 | if (atomic_dec_and_test(&desc->threads_active)) |
7140ea19 IY |
836 | wake_up(&desc->wait_for_threads); |
837 | } | |
838 | ||
67d12145 | 839 | static void irq_thread_dtor(struct callback_head *unused) |
4d1d61a6 ON |
840 | { |
841 | struct task_struct *tsk = current; | |
842 | struct irq_desc *desc; | |
843 | struct irqaction *action; | |
844 | ||
845 | if (WARN_ON_ONCE(!(current->flags & PF_EXITING))) | |
846 | return; | |
847 | ||
848 | action = kthread_data(tsk); | |
849 | ||
fb21affa | 850 | pr_err("exiting task \"%s\" (%d) is an active IRQ thread (irq %d)\n", |
19af395d | 851 | tsk->comm, tsk->pid, action->irq); |
4d1d61a6 ON |
852 | |
853 | ||
854 | desc = irq_to_desc(action->irq); | |
855 | /* | |
856 | * If IRQTF_RUNTHREAD is set, we need to decrement | |
857 | * desc->threads_active and wake possible waiters. | |
858 | */ | |
859 | if (test_and_clear_bit(IRQTF_RUNTHREAD, &action->thread_flags)) | |
860 | wake_threads_waitq(desc); | |
861 | ||
862 | /* Prevent a stale desc->threads_oneshot */ | |
863 | irq_finalize_oneshot(desc, action); | |
864 | } | |
865 | ||
3aa551c9 TG |
866 | /* |
867 | * Interrupt handler thread | |
868 | */ | |
869 | static int irq_thread(void *data) | |
870 | { | |
67d12145 | 871 | struct callback_head on_exit_work; |
3aa551c9 TG |
872 | struct irqaction *action = data; |
873 | struct irq_desc *desc = irq_to_desc(action->irq); | |
3a43e05f SAS |
874 | irqreturn_t (*handler_fn)(struct irq_desc *desc, |
875 | struct irqaction *action); | |
3aa551c9 | 876 | |
540b60e2 | 877 | if (force_irqthreads && test_bit(IRQTF_FORCED_THREAD, |
8d32a307 TG |
878 | &action->thread_flags)) |
879 | handler_fn = irq_forced_thread_fn; | |
880 | else | |
881 | handler_fn = irq_thread_fn; | |
882 | ||
41f9d29f | 883 | init_task_work(&on_exit_work, irq_thread_dtor); |
4d1d61a6 | 884 | task_work_add(current, &on_exit_work, false); |
3aa551c9 | 885 | |
f3de44ed SM |
886 | irq_thread_check_affinity(desc, action); |
887 | ||
3aa551c9 | 888 | while (!irq_wait_for_interrupt(action)) { |
7140ea19 | 889 | irqreturn_t action_ret; |
3aa551c9 | 890 | |
591d2fb0 TG |
891 | irq_thread_check_affinity(desc, action); |
892 | ||
7140ea19 IY |
893 | action_ret = handler_fn(desc, action); |
894 | if (!noirqdebug) | |
895 | note_interrupt(action->irq, desc, action_ret); | |
3aa551c9 | 896 | |
7140ea19 | 897 | wake_threads_waitq(desc); |
3aa551c9 TG |
898 | } |
899 | ||
7140ea19 IY |
900 | /* |
901 | * This is the regular exit path. __free_irq() is stopping the | |
902 | * thread via kthread_stop() after calling | |
903 | * synchronize_irq(). So neither IRQTF_RUNTHREAD nor the | |
e04268b0 TG |
904 | * oneshot mask bit can be set. We cannot verify that as we |
905 | * cannot touch the oneshot mask at this point anymore as | |
906 | * __setup_irq() might have given out currents thread_mask | |
907 | * again. | |
3aa551c9 | 908 | */ |
4d1d61a6 | 909 | task_work_cancel(current, irq_thread_dtor); |
3aa551c9 TG |
910 | return 0; |
911 | } | |
912 | ||
a92444c6 TG |
913 | /** |
914 | * irq_wake_thread - wake the irq thread for the action identified by dev_id | |
915 | * @irq: Interrupt line | |
916 | * @dev_id: Device identity for which the thread should be woken | |
917 | * | |
918 | */ | |
919 | void irq_wake_thread(unsigned int irq, void *dev_id) | |
920 | { | |
921 | struct irq_desc *desc = irq_to_desc(irq); | |
922 | struct irqaction *action; | |
923 | unsigned long flags; | |
924 | ||
925 | if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
926 | return; | |
927 | ||
928 | raw_spin_lock_irqsave(&desc->lock, flags); | |
929 | for (action = desc->action; action; action = action->next) { | |
930 | if (action->dev_id == dev_id) { | |
931 | if (action->thread) | |
932 | __irq_wake_thread(desc, action); | |
933 | break; | |
934 | } | |
935 | } | |
936 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
937 | } | |
938 | EXPORT_SYMBOL_GPL(irq_wake_thread); | |
939 | ||
8d32a307 TG |
940 | static void irq_setup_forced_threading(struct irqaction *new) |
941 | { | |
942 | if (!force_irqthreads) | |
943 | return; | |
944 | if (new->flags & (IRQF_NO_THREAD | IRQF_PERCPU | IRQF_ONESHOT)) | |
945 | return; | |
946 | ||
947 | new->flags |= IRQF_ONESHOT; | |
948 | ||
949 | if (!new->thread_fn) { | |
950 | set_bit(IRQTF_FORCED_THREAD, &new->thread_flags); | |
951 | new->thread_fn = new->handler; | |
952 | new->handler = irq_default_primary_handler; | |
953 | } | |
954 | } | |
955 | ||
c1bacbae TG |
956 | static int irq_request_resources(struct irq_desc *desc) |
957 | { | |
958 | struct irq_data *d = &desc->irq_data; | |
959 | struct irq_chip *c = d->chip; | |
960 | ||
961 | return c->irq_request_resources ? c->irq_request_resources(d) : 0; | |
962 | } | |
963 | ||
964 | static void irq_release_resources(struct irq_desc *desc) | |
965 | { | |
966 | struct irq_data *d = &desc->irq_data; | |
967 | struct irq_chip *c = d->chip; | |
968 | ||
969 | if (c->irq_release_resources) | |
970 | c->irq_release_resources(d); | |
971 | } | |
972 | ||
1da177e4 LT |
973 | /* |
974 | * Internal function to register an irqaction - typically used to | |
975 | * allocate special interrupts that are part of the architecture. | |
976 | */ | |
d3c60047 | 977 | static int |
327ec569 | 978 | __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) |
1da177e4 | 979 | { |
f17c7545 | 980 | struct irqaction *old, **old_ptr; |
b5faba21 | 981 | unsigned long flags, thread_mask = 0; |
3b8249e7 TG |
982 | int ret, nested, shared = 0; |
983 | cpumask_var_t mask; | |
1da177e4 | 984 | |
7d94f7ca | 985 | if (!desc) |
c2b5a251 MW |
986 | return -EINVAL; |
987 | ||
6b8ff312 | 988 | if (desc->irq_data.chip == &no_irq_chip) |
1da177e4 | 989 | return -ENOSYS; |
b6873807 SAS |
990 | if (!try_module_get(desc->owner)) |
991 | return -ENODEV; | |
1da177e4 | 992 | |
3aa551c9 | 993 | /* |
399b5da2 TG |
994 | * Check whether the interrupt nests into another interrupt |
995 | * thread. | |
996 | */ | |
1ccb4e61 | 997 | nested = irq_settings_is_nested_thread(desc); |
399b5da2 | 998 | if (nested) { |
b6873807 SAS |
999 | if (!new->thread_fn) { |
1000 | ret = -EINVAL; | |
1001 | goto out_mput; | |
1002 | } | |
399b5da2 TG |
1003 | /* |
1004 | * Replace the primary handler which was provided from | |
1005 | * the driver for non nested interrupt handling by the | |
1006 | * dummy function which warns when called. | |
1007 | */ | |
1008 | new->handler = irq_nested_primary_handler; | |
8d32a307 | 1009 | } else { |
7f1b1244 PM |
1010 | if (irq_settings_can_thread(desc)) |
1011 | irq_setup_forced_threading(new); | |
399b5da2 TG |
1012 | } |
1013 | ||
3aa551c9 | 1014 | /* |
399b5da2 TG |
1015 | * Create a handler thread when a thread function is supplied |
1016 | * and the interrupt does not nest into another interrupt | |
1017 | * thread. | |
3aa551c9 | 1018 | */ |
399b5da2 | 1019 | if (new->thread_fn && !nested) { |
3aa551c9 | 1020 | struct task_struct *t; |
ee238713 IS |
1021 | static const struct sched_param param = { |
1022 | .sched_priority = MAX_USER_RT_PRIO/2, | |
1023 | }; | |
3aa551c9 TG |
1024 | |
1025 | t = kthread_create(irq_thread, new, "irq/%d-%s", irq, | |
1026 | new->name); | |
b6873807 SAS |
1027 | if (IS_ERR(t)) { |
1028 | ret = PTR_ERR(t); | |
1029 | goto out_mput; | |
1030 | } | |
ee238713 | 1031 | |
bbfe65c2 | 1032 | sched_setscheduler_nocheck(t, SCHED_FIFO, ¶m); |
ee238713 | 1033 | |
3aa551c9 TG |
1034 | /* |
1035 | * We keep the reference to the task struct even if | |
1036 | * the thread dies to avoid that the interrupt code | |
1037 | * references an already freed task_struct. | |
1038 | */ | |
1039 | get_task_struct(t); | |
1040 | new->thread = t; | |
04aa530e TG |
1041 | /* |
1042 | * Tell the thread to set its affinity. This is | |
1043 | * important for shared interrupt handlers as we do | |
1044 | * not invoke setup_affinity() for the secondary | |
1045 | * handlers as everything is already set up. Even for | |
1046 | * interrupts marked with IRQF_NO_BALANCE this is | |
1047 | * correct as we want the thread to move to the cpu(s) | |
1048 | * on which the requesting code placed the interrupt. | |
1049 | */ | |
1050 | set_bit(IRQTF_AFFINITY, &new->thread_flags); | |
3aa551c9 TG |
1051 | } |
1052 | ||
3b8249e7 TG |
1053 | if (!alloc_cpumask_var(&mask, GFP_KERNEL)) { |
1054 | ret = -ENOMEM; | |
1055 | goto out_thread; | |
1056 | } | |
1057 | ||
dc9b229a TG |
1058 | /* |
1059 | * Drivers are often written to work w/o knowledge about the | |
1060 | * underlying irq chip implementation, so a request for a | |
1061 | * threaded irq without a primary hard irq context handler | |
1062 | * requires the ONESHOT flag to be set. Some irq chips like | |
1063 | * MSI based interrupts are per se one shot safe. Check the | |
1064 | * chip flags, so we can avoid the unmask dance at the end of | |
1065 | * the threaded handler for those. | |
1066 | */ | |
1067 | if (desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE) | |
1068 | new->flags &= ~IRQF_ONESHOT; | |
1069 | ||
1da177e4 LT |
1070 | /* |
1071 | * The following block of code has to be executed atomically | |
1072 | */ | |
239007b8 | 1073 | raw_spin_lock_irqsave(&desc->lock, flags); |
f17c7545 IM |
1074 | old_ptr = &desc->action; |
1075 | old = *old_ptr; | |
06fcb0c6 | 1076 | if (old) { |
e76de9f8 TG |
1077 | /* |
1078 | * Can't share interrupts unless both agree to and are | |
1079 | * the same type (level, edge, polarity). So both flag | |
3cca53b0 | 1080 | * fields must have IRQF_SHARED set and the bits which |
9d591edd TG |
1081 | * set the trigger type must match. Also all must |
1082 | * agree on ONESHOT. | |
e76de9f8 | 1083 | */ |
3cca53b0 | 1084 | if (!((old->flags & new->flags) & IRQF_SHARED) || |
9d591edd | 1085 | ((old->flags ^ new->flags) & IRQF_TRIGGER_MASK) || |
f5d89470 | 1086 | ((old->flags ^ new->flags) & IRQF_ONESHOT)) |
f5163427 DS |
1087 | goto mismatch; |
1088 | ||
f5163427 | 1089 | /* All handlers must agree on per-cpuness */ |
3cca53b0 TG |
1090 | if ((old->flags & IRQF_PERCPU) != |
1091 | (new->flags & IRQF_PERCPU)) | |
f5163427 | 1092 | goto mismatch; |
1da177e4 LT |
1093 | |
1094 | /* add new interrupt at end of irq queue */ | |
1095 | do { | |
52abb700 TG |
1096 | /* |
1097 | * Or all existing action->thread_mask bits, | |
1098 | * so we can find the next zero bit for this | |
1099 | * new action. | |
1100 | */ | |
b5faba21 | 1101 | thread_mask |= old->thread_mask; |
f17c7545 IM |
1102 | old_ptr = &old->next; |
1103 | old = *old_ptr; | |
1da177e4 LT |
1104 | } while (old); |
1105 | shared = 1; | |
1106 | } | |
1107 | ||
b5faba21 | 1108 | /* |
52abb700 TG |
1109 | * Setup the thread mask for this irqaction for ONESHOT. For |
1110 | * !ONESHOT irqs the thread mask is 0 so we can avoid a | |
1111 | * conditional in irq_wake_thread(). | |
b5faba21 | 1112 | */ |
52abb700 TG |
1113 | if (new->flags & IRQF_ONESHOT) { |
1114 | /* | |
1115 | * Unlikely to have 32 resp 64 irqs sharing one line, | |
1116 | * but who knows. | |
1117 | */ | |
1118 | if (thread_mask == ~0UL) { | |
1119 | ret = -EBUSY; | |
1120 | goto out_mask; | |
1121 | } | |
1122 | /* | |
1123 | * The thread_mask for the action is or'ed to | |
1124 | * desc->thread_active to indicate that the | |
1125 | * IRQF_ONESHOT thread handler has been woken, but not | |
1126 | * yet finished. The bit is cleared when a thread | |
1127 | * completes. When all threads of a shared interrupt | |
1128 | * line have completed desc->threads_active becomes | |
1129 | * zero and the interrupt line is unmasked. See | |
1130 | * handle.c:irq_wake_thread() for further information. | |
1131 | * | |
1132 | * If no thread is woken by primary (hard irq context) | |
1133 | * interrupt handlers, then desc->threads_active is | |
1134 | * also checked for zero to unmask the irq line in the | |
1135 | * affected hard irq flow handlers | |
1136 | * (handle_[fasteoi|level]_irq). | |
1137 | * | |
1138 | * The new action gets the first zero bit of | |
1139 | * thread_mask assigned. See the loop above which or's | |
1140 | * all existing action->thread_mask bits. | |
1141 | */ | |
1142 | new->thread_mask = 1 << ffz(thread_mask); | |
1c6c6952 | 1143 | |
dc9b229a TG |
1144 | } else if (new->handler == irq_default_primary_handler && |
1145 | !(desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE)) { | |
1c6c6952 TG |
1146 | /* |
1147 | * The interrupt was requested with handler = NULL, so | |
1148 | * we use the default primary handler for it. But it | |
1149 | * does not have the oneshot flag set. In combination | |
1150 | * with level interrupts this is deadly, because the | |
1151 | * default primary handler just wakes the thread, then | |
1152 | * the irq lines is reenabled, but the device still | |
1153 | * has the level irq asserted. Rinse and repeat.... | |
1154 | * | |
1155 | * While this works for edge type interrupts, we play | |
1156 | * it safe and reject unconditionally because we can't | |
1157 | * say for sure which type this interrupt really | |
1158 | * has. The type flags are unreliable as the | |
1159 | * underlying chip implementation can override them. | |
1160 | */ | |
97fd75b7 | 1161 | pr_err("Threaded irq requested with handler=NULL and !ONESHOT for irq %d\n", |
1c6c6952 TG |
1162 | irq); |
1163 | ret = -EINVAL; | |
1164 | goto out_mask; | |
b5faba21 | 1165 | } |
b5faba21 | 1166 | |
1da177e4 | 1167 | if (!shared) { |
c1bacbae TG |
1168 | ret = irq_request_resources(desc); |
1169 | if (ret) { | |
1170 | pr_err("Failed to request resources for %s (irq %d) on irqchip %s\n", | |
1171 | new->name, irq, desc->irq_data.chip->name); | |
1172 | goto out_mask; | |
1173 | } | |
1174 | ||
3aa551c9 TG |
1175 | init_waitqueue_head(&desc->wait_for_threads); |
1176 | ||
e76de9f8 | 1177 | /* Setup the type (level, edge polarity) if configured: */ |
3cca53b0 | 1178 | if (new->flags & IRQF_TRIGGER_MASK) { |
f2b662da DB |
1179 | ret = __irq_set_trigger(desc, irq, |
1180 | new->flags & IRQF_TRIGGER_MASK); | |
82736f4d | 1181 | |
3aa551c9 | 1182 | if (ret) |
3b8249e7 | 1183 | goto out_mask; |
091738a2 | 1184 | } |
6a6de9ef | 1185 | |
009b4c3b | 1186 | desc->istate &= ~(IRQS_AUTODETECT | IRQS_SPURIOUS_DISABLED | \ |
32f4125e TG |
1187 | IRQS_ONESHOT | IRQS_WAITING); |
1188 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); | |
94d39e1f | 1189 | |
a005677b TG |
1190 | if (new->flags & IRQF_PERCPU) { |
1191 | irqd_set(&desc->irq_data, IRQD_PER_CPU); | |
1192 | irq_settings_set_per_cpu(desc); | |
1193 | } | |
6a58fb3b | 1194 | |
b25c340c | 1195 | if (new->flags & IRQF_ONESHOT) |
3d67baec | 1196 | desc->istate |= IRQS_ONESHOT; |
b25c340c | 1197 | |
1ccb4e61 | 1198 | if (irq_settings_can_autoenable(desc)) |
b4bc724e | 1199 | irq_startup(desc, true); |
46999238 | 1200 | else |
e76de9f8 TG |
1201 | /* Undo nested disables: */ |
1202 | desc->depth = 1; | |
18404756 | 1203 | |
612e3684 | 1204 | /* Exclude IRQ from balancing if requested */ |
a005677b TG |
1205 | if (new->flags & IRQF_NOBALANCING) { |
1206 | irq_settings_set_no_balancing(desc); | |
1207 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | |
1208 | } | |
612e3684 | 1209 | |
18404756 | 1210 | /* Set default affinity mask once everything is setup */ |
3b8249e7 | 1211 | setup_affinity(irq, desc, mask); |
0c5d1eb7 | 1212 | |
876dbd4c TG |
1213 | } else if (new->flags & IRQF_TRIGGER_MASK) { |
1214 | unsigned int nmsk = new->flags & IRQF_TRIGGER_MASK; | |
1215 | unsigned int omsk = irq_settings_get_trigger_mask(desc); | |
1216 | ||
1217 | if (nmsk != omsk) | |
1218 | /* hope the handler works with current trigger mode */ | |
97fd75b7 | 1219 | pr_warning("irq %d uses trigger mode %u; requested %u\n", |
876dbd4c | 1220 | irq, nmsk, omsk); |
1da177e4 | 1221 | } |
82736f4d | 1222 | |
69ab8494 | 1223 | new->irq = irq; |
f17c7545 | 1224 | *old_ptr = new; |
82736f4d | 1225 | |
8528b0f1 LT |
1226 | /* Reset broken irq detection when installing new handler */ |
1227 | desc->irq_count = 0; | |
1228 | desc->irqs_unhandled = 0; | |
1adb0850 TG |
1229 | |
1230 | /* | |
1231 | * Check whether we disabled the irq via the spurious handler | |
1232 | * before. Reenable it and give it another chance. | |
1233 | */ | |
7acdd53e TG |
1234 | if (shared && (desc->istate & IRQS_SPURIOUS_DISABLED)) { |
1235 | desc->istate &= ~IRQS_SPURIOUS_DISABLED; | |
0a0c5168 | 1236 | __enable_irq(desc, irq, false); |
1adb0850 TG |
1237 | } |
1238 | ||
239007b8 | 1239 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 | 1240 | |
69ab8494 TG |
1241 | /* |
1242 | * Strictly no need to wake it up, but hung_task complains | |
1243 | * when no hard interrupt wakes the thread up. | |
1244 | */ | |
1245 | if (new->thread) | |
1246 | wake_up_process(new->thread); | |
1247 | ||
2c6927a3 | 1248 | register_irq_proc(irq, desc); |
1da177e4 LT |
1249 | new->dir = NULL; |
1250 | register_handler_proc(irq, new); | |
4f5058c3 | 1251 | free_cpumask_var(mask); |
1da177e4 LT |
1252 | |
1253 | return 0; | |
f5163427 DS |
1254 | |
1255 | mismatch: | |
3cca53b0 | 1256 | if (!(new->flags & IRQF_PROBE_SHARED)) { |
97fd75b7 | 1257 | pr_err("Flags mismatch irq %d. %08x (%s) vs. %08x (%s)\n", |
f5d89470 TG |
1258 | irq, new->flags, new->name, old->flags, old->name); |
1259 | #ifdef CONFIG_DEBUG_SHIRQ | |
13e87ec6 | 1260 | dump_stack(); |
3f050447 | 1261 | #endif |
f5d89470 | 1262 | } |
3aa551c9 TG |
1263 | ret = -EBUSY; |
1264 | ||
3b8249e7 | 1265 | out_mask: |
1c389795 | 1266 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3b8249e7 TG |
1267 | free_cpumask_var(mask); |
1268 | ||
3aa551c9 | 1269 | out_thread: |
3aa551c9 TG |
1270 | if (new->thread) { |
1271 | struct task_struct *t = new->thread; | |
1272 | ||
1273 | new->thread = NULL; | |
05d74efa | 1274 | kthread_stop(t); |
3aa551c9 TG |
1275 | put_task_struct(t); |
1276 | } | |
b6873807 SAS |
1277 | out_mput: |
1278 | module_put(desc->owner); | |
3aa551c9 | 1279 | return ret; |
1da177e4 LT |
1280 | } |
1281 | ||
d3c60047 TG |
1282 | /** |
1283 | * setup_irq - setup an interrupt | |
1284 | * @irq: Interrupt line to setup | |
1285 | * @act: irqaction for the interrupt | |
1286 | * | |
1287 | * Used to statically setup interrupts in the early boot process. | |
1288 | */ | |
1289 | int setup_irq(unsigned int irq, struct irqaction *act) | |
1290 | { | |
986c011d | 1291 | int retval; |
d3c60047 TG |
1292 | struct irq_desc *desc = irq_to_desc(irq); |
1293 | ||
31d9d9b6 MZ |
1294 | if (WARN_ON(irq_settings_is_per_cpu_devid(desc))) |
1295 | return -EINVAL; | |
986c011d DD |
1296 | chip_bus_lock(desc); |
1297 | retval = __setup_irq(irq, desc, act); | |
1298 | chip_bus_sync_unlock(desc); | |
1299 | ||
1300 | return retval; | |
d3c60047 | 1301 | } |
eb53b4e8 | 1302 | EXPORT_SYMBOL_GPL(setup_irq); |
d3c60047 | 1303 | |
31d9d9b6 | 1304 | /* |
cbf94f06 MD |
1305 | * Internal function to unregister an irqaction - used to free |
1306 | * regular and special interrupts that are part of the architecture. | |
1da177e4 | 1307 | */ |
cbf94f06 | 1308 | static struct irqaction *__free_irq(unsigned int irq, void *dev_id) |
1da177e4 | 1309 | { |
d3c60047 | 1310 | struct irq_desc *desc = irq_to_desc(irq); |
f17c7545 | 1311 | struct irqaction *action, **action_ptr; |
1da177e4 LT |
1312 | unsigned long flags; |
1313 | ||
ae88a23b | 1314 | WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq); |
7d94f7ca | 1315 | |
7d94f7ca | 1316 | if (!desc) |
f21cfb25 | 1317 | return NULL; |
1da177e4 | 1318 | |
239007b8 | 1319 | raw_spin_lock_irqsave(&desc->lock, flags); |
ae88a23b IM |
1320 | |
1321 | /* | |
1322 | * There can be multiple actions per IRQ descriptor, find the right | |
1323 | * one based on the dev_id: | |
1324 | */ | |
f17c7545 | 1325 | action_ptr = &desc->action; |
1da177e4 | 1326 | for (;;) { |
f17c7545 | 1327 | action = *action_ptr; |
1da177e4 | 1328 | |
ae88a23b IM |
1329 | if (!action) { |
1330 | WARN(1, "Trying to free already-free IRQ %d\n", irq); | |
239007b8 | 1331 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 | 1332 | |
f21cfb25 | 1333 | return NULL; |
ae88a23b | 1334 | } |
1da177e4 | 1335 | |
8316e381 IM |
1336 | if (action->dev_id == dev_id) |
1337 | break; | |
f17c7545 | 1338 | action_ptr = &action->next; |
ae88a23b | 1339 | } |
dbce706e | 1340 | |
ae88a23b | 1341 | /* Found it - now remove it from the list of entries: */ |
f17c7545 | 1342 | *action_ptr = action->next; |
ae88a23b | 1343 | |
ae88a23b | 1344 | /* If this was the last handler, shut down the IRQ line: */ |
c1bacbae | 1345 | if (!desc->action) { |
46999238 | 1346 | irq_shutdown(desc); |
c1bacbae TG |
1347 | irq_release_resources(desc); |
1348 | } | |
3aa551c9 | 1349 | |
e7a297b0 PWJ |
1350 | #ifdef CONFIG_SMP |
1351 | /* make sure affinity_hint is cleaned up */ | |
1352 | if (WARN_ON_ONCE(desc->affinity_hint)) | |
1353 | desc->affinity_hint = NULL; | |
1354 | #endif | |
1355 | ||
239007b8 | 1356 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
ae88a23b IM |
1357 | |
1358 | unregister_handler_proc(irq, action); | |
1359 | ||
1360 | /* Make sure it's not being used on another CPU: */ | |
1361 | synchronize_irq(irq); | |
1da177e4 | 1362 | |
70edcd77 | 1363 | #ifdef CONFIG_DEBUG_SHIRQ |
ae88a23b IM |
1364 | /* |
1365 | * It's a shared IRQ -- the driver ought to be prepared for an IRQ | |
1366 | * event to happen even now it's being freed, so let's make sure that | |
1367 | * is so by doing an extra call to the handler .... | |
1368 | * | |
1369 | * ( We do this after actually deregistering it, to make sure that a | |
1370 | * 'real' IRQ doesn't run in * parallel with our fake. ) | |
1371 | */ | |
1372 | if (action->flags & IRQF_SHARED) { | |
1373 | local_irq_save(flags); | |
1374 | action->handler(irq, dev_id); | |
1375 | local_irq_restore(flags); | |
1da177e4 | 1376 | } |
ae88a23b | 1377 | #endif |
2d860ad7 LT |
1378 | |
1379 | if (action->thread) { | |
05d74efa | 1380 | kthread_stop(action->thread); |
2d860ad7 LT |
1381 | put_task_struct(action->thread); |
1382 | } | |
1383 | ||
b6873807 | 1384 | module_put(desc->owner); |
f21cfb25 MD |
1385 | return action; |
1386 | } | |
1387 | ||
cbf94f06 MD |
1388 | /** |
1389 | * remove_irq - free an interrupt | |
1390 | * @irq: Interrupt line to free | |
1391 | * @act: irqaction for the interrupt | |
1392 | * | |
1393 | * Used to remove interrupts statically setup by the early boot process. | |
1394 | */ | |
1395 | void remove_irq(unsigned int irq, struct irqaction *act) | |
1396 | { | |
31d9d9b6 MZ |
1397 | struct irq_desc *desc = irq_to_desc(irq); |
1398 | ||
1399 | if (desc && !WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
1400 | __free_irq(irq, act->dev_id); | |
cbf94f06 | 1401 | } |
eb53b4e8 | 1402 | EXPORT_SYMBOL_GPL(remove_irq); |
cbf94f06 | 1403 | |
f21cfb25 MD |
1404 | /** |
1405 | * free_irq - free an interrupt allocated with request_irq | |
1406 | * @irq: Interrupt line to free | |
1407 | * @dev_id: Device identity to free | |
1408 | * | |
1409 | * Remove an interrupt handler. The handler is removed and if the | |
1410 | * interrupt line is no longer in use by any driver it is disabled. | |
1411 | * On a shared IRQ the caller must ensure the interrupt is disabled | |
1412 | * on the card it drives before calling this function. The function | |
1413 | * does not return until any executing interrupts for this IRQ | |
1414 | * have completed. | |
1415 | * | |
1416 | * This function must not be called from interrupt context. | |
1417 | */ | |
1418 | void free_irq(unsigned int irq, void *dev_id) | |
1419 | { | |
70aedd24 TG |
1420 | struct irq_desc *desc = irq_to_desc(irq); |
1421 | ||
31d9d9b6 | 1422 | if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) |
70aedd24 TG |
1423 | return; |
1424 | ||
cd7eab44 BH |
1425 | #ifdef CONFIG_SMP |
1426 | if (WARN_ON(desc->affinity_notify)) | |
1427 | desc->affinity_notify = NULL; | |
1428 | #endif | |
1429 | ||
3876ec9e | 1430 | chip_bus_lock(desc); |
cbf94f06 | 1431 | kfree(__free_irq(irq, dev_id)); |
3876ec9e | 1432 | chip_bus_sync_unlock(desc); |
1da177e4 | 1433 | } |
1da177e4 LT |
1434 | EXPORT_SYMBOL(free_irq); |
1435 | ||
1436 | /** | |
3aa551c9 | 1437 | * request_threaded_irq - allocate an interrupt line |
1da177e4 | 1438 | * @irq: Interrupt line to allocate |
3aa551c9 TG |
1439 | * @handler: Function to be called when the IRQ occurs. |
1440 | * Primary handler for threaded interrupts | |
b25c340c TG |
1441 | * If NULL and thread_fn != NULL the default |
1442 | * primary handler is installed | |
f48fe81e TG |
1443 | * @thread_fn: Function called from the irq handler thread |
1444 | * If NULL, no irq thread is created | |
1da177e4 LT |
1445 | * @irqflags: Interrupt type flags |
1446 | * @devname: An ascii name for the claiming device | |
1447 | * @dev_id: A cookie passed back to the handler function | |
1448 | * | |
1449 | * This call allocates interrupt resources and enables the | |
1450 | * interrupt line and IRQ handling. From the point this | |
1451 | * call is made your handler function may be invoked. Since | |
1452 | * your handler function must clear any interrupt the board | |
1453 | * raises, you must take care both to initialise your hardware | |
1454 | * and to set up the interrupt handler in the right order. | |
1455 | * | |
3aa551c9 | 1456 | * If you want to set up a threaded irq handler for your device |
6d21af4f | 1457 | * then you need to supply @handler and @thread_fn. @handler is |
3aa551c9 TG |
1458 | * still called in hard interrupt context and has to check |
1459 | * whether the interrupt originates from the device. If yes it | |
1460 | * needs to disable the interrupt on the device and return | |
39a2eddb | 1461 | * IRQ_WAKE_THREAD which will wake up the handler thread and run |
3aa551c9 TG |
1462 | * @thread_fn. This split handler design is necessary to support |
1463 | * shared interrupts. | |
1464 | * | |
1da177e4 LT |
1465 | * Dev_id must be globally unique. Normally the address of the |
1466 | * device data structure is used as the cookie. Since the handler | |
1467 | * receives this value it makes sense to use it. | |
1468 | * | |
1469 | * If your interrupt is shared you must pass a non NULL dev_id | |
1470 | * as this is required when freeing the interrupt. | |
1471 | * | |
1472 | * Flags: | |
1473 | * | |
3cca53b0 | 1474 | * IRQF_SHARED Interrupt is shared |
0c5d1eb7 | 1475 | * IRQF_TRIGGER_* Specify active edge(s) or level |
1da177e4 LT |
1476 | * |
1477 | */ | |
3aa551c9 TG |
1478 | int request_threaded_irq(unsigned int irq, irq_handler_t handler, |
1479 | irq_handler_t thread_fn, unsigned long irqflags, | |
1480 | const char *devname, void *dev_id) | |
1da177e4 | 1481 | { |
06fcb0c6 | 1482 | struct irqaction *action; |
08678b08 | 1483 | struct irq_desc *desc; |
d3c60047 | 1484 | int retval; |
1da177e4 LT |
1485 | |
1486 | /* | |
1487 | * Sanity-check: shared interrupts must pass in a real dev-ID, | |
1488 | * otherwise we'll have trouble later trying to figure out | |
1489 | * which interrupt is which (messes up the interrupt freeing | |
1490 | * logic etc). | |
1491 | */ | |
3cca53b0 | 1492 | if ((irqflags & IRQF_SHARED) && !dev_id) |
1da177e4 | 1493 | return -EINVAL; |
7d94f7ca | 1494 | |
cb5bc832 | 1495 | desc = irq_to_desc(irq); |
7d94f7ca | 1496 | if (!desc) |
1da177e4 | 1497 | return -EINVAL; |
7d94f7ca | 1498 | |
31d9d9b6 MZ |
1499 | if (!irq_settings_can_request(desc) || |
1500 | WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
6550c775 | 1501 | return -EINVAL; |
b25c340c TG |
1502 | |
1503 | if (!handler) { | |
1504 | if (!thread_fn) | |
1505 | return -EINVAL; | |
1506 | handler = irq_default_primary_handler; | |
1507 | } | |
1da177e4 | 1508 | |
45535732 | 1509 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); |
1da177e4 LT |
1510 | if (!action) |
1511 | return -ENOMEM; | |
1512 | ||
1513 | action->handler = handler; | |
3aa551c9 | 1514 | action->thread_fn = thread_fn; |
1da177e4 | 1515 | action->flags = irqflags; |
1da177e4 | 1516 | action->name = devname; |
1da177e4 LT |
1517 | action->dev_id = dev_id; |
1518 | ||
3876ec9e | 1519 | chip_bus_lock(desc); |
d3c60047 | 1520 | retval = __setup_irq(irq, desc, action); |
3876ec9e | 1521 | chip_bus_sync_unlock(desc); |
70aedd24 | 1522 | |
377bf1e4 AV |
1523 | if (retval) |
1524 | kfree(action); | |
1525 | ||
6d83f94d | 1526 | #ifdef CONFIG_DEBUG_SHIRQ_FIXME |
6ce51c43 | 1527 | if (!retval && (irqflags & IRQF_SHARED)) { |
a304e1b8 DW |
1528 | /* |
1529 | * It's a shared IRQ -- the driver ought to be prepared for it | |
1530 | * to happen immediately, so let's make sure.... | |
377bf1e4 AV |
1531 | * We disable the irq to make sure that a 'real' IRQ doesn't |
1532 | * run in parallel with our fake. | |
a304e1b8 | 1533 | */ |
59845b1f | 1534 | unsigned long flags; |
a304e1b8 | 1535 | |
377bf1e4 | 1536 | disable_irq(irq); |
59845b1f | 1537 | local_irq_save(flags); |
377bf1e4 | 1538 | |
59845b1f | 1539 | handler(irq, dev_id); |
377bf1e4 | 1540 | |
59845b1f | 1541 | local_irq_restore(flags); |
377bf1e4 | 1542 | enable_irq(irq); |
a304e1b8 DW |
1543 | } |
1544 | #endif | |
1da177e4 LT |
1545 | return retval; |
1546 | } | |
3aa551c9 | 1547 | EXPORT_SYMBOL(request_threaded_irq); |
ae731f8d MZ |
1548 | |
1549 | /** | |
1550 | * request_any_context_irq - allocate an interrupt line | |
1551 | * @irq: Interrupt line to allocate | |
1552 | * @handler: Function to be called when the IRQ occurs. | |
1553 | * Threaded handler for threaded interrupts. | |
1554 | * @flags: Interrupt type flags | |
1555 | * @name: An ascii name for the claiming device | |
1556 | * @dev_id: A cookie passed back to the handler function | |
1557 | * | |
1558 | * This call allocates interrupt resources and enables the | |
1559 | * interrupt line and IRQ handling. It selects either a | |
1560 | * hardirq or threaded handling method depending on the | |
1561 | * context. | |
1562 | * | |
1563 | * On failure, it returns a negative value. On success, | |
1564 | * it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED. | |
1565 | */ | |
1566 | int request_any_context_irq(unsigned int irq, irq_handler_t handler, | |
1567 | unsigned long flags, const char *name, void *dev_id) | |
1568 | { | |
1569 | struct irq_desc *desc = irq_to_desc(irq); | |
1570 | int ret; | |
1571 | ||
1572 | if (!desc) | |
1573 | return -EINVAL; | |
1574 | ||
1ccb4e61 | 1575 | if (irq_settings_is_nested_thread(desc)) { |
ae731f8d MZ |
1576 | ret = request_threaded_irq(irq, NULL, handler, |
1577 | flags, name, dev_id); | |
1578 | return !ret ? IRQC_IS_NESTED : ret; | |
1579 | } | |
1580 | ||
1581 | ret = request_irq(irq, handler, flags, name, dev_id); | |
1582 | return !ret ? IRQC_IS_HARDIRQ : ret; | |
1583 | } | |
1584 | EXPORT_SYMBOL_GPL(request_any_context_irq); | |
31d9d9b6 | 1585 | |
1e7c5fd2 | 1586 | void enable_percpu_irq(unsigned int irq, unsigned int type) |
31d9d9b6 MZ |
1587 | { |
1588 | unsigned int cpu = smp_processor_id(); | |
1589 | unsigned long flags; | |
1590 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
1591 | ||
1592 | if (!desc) | |
1593 | return; | |
1594 | ||
1e7c5fd2 MZ |
1595 | type &= IRQ_TYPE_SENSE_MASK; |
1596 | if (type != IRQ_TYPE_NONE) { | |
1597 | int ret; | |
1598 | ||
1599 | ret = __irq_set_trigger(desc, irq, type); | |
1600 | ||
1601 | if (ret) { | |
32cffdde | 1602 | WARN(1, "failed to set type for IRQ%d\n", irq); |
1e7c5fd2 MZ |
1603 | goto out; |
1604 | } | |
1605 | } | |
1606 | ||
31d9d9b6 | 1607 | irq_percpu_enable(desc, cpu); |
1e7c5fd2 | 1608 | out: |
31d9d9b6 MZ |
1609 | irq_put_desc_unlock(desc, flags); |
1610 | } | |
36a5df85 | 1611 | EXPORT_SYMBOL_GPL(enable_percpu_irq); |
31d9d9b6 MZ |
1612 | |
1613 | void disable_percpu_irq(unsigned int irq) | |
1614 | { | |
1615 | unsigned int cpu = smp_processor_id(); | |
1616 | unsigned long flags; | |
1617 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
1618 | ||
1619 | if (!desc) | |
1620 | return; | |
1621 | ||
1622 | irq_percpu_disable(desc, cpu); | |
1623 | irq_put_desc_unlock(desc, flags); | |
1624 | } | |
36a5df85 | 1625 | EXPORT_SYMBOL_GPL(disable_percpu_irq); |
31d9d9b6 MZ |
1626 | |
1627 | /* | |
1628 | * Internal function to unregister a percpu irqaction. | |
1629 | */ | |
1630 | static struct irqaction *__free_percpu_irq(unsigned int irq, void __percpu *dev_id) | |
1631 | { | |
1632 | struct irq_desc *desc = irq_to_desc(irq); | |
1633 | struct irqaction *action; | |
1634 | unsigned long flags; | |
1635 | ||
1636 | WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq); | |
1637 | ||
1638 | if (!desc) | |
1639 | return NULL; | |
1640 | ||
1641 | raw_spin_lock_irqsave(&desc->lock, flags); | |
1642 | ||
1643 | action = desc->action; | |
1644 | if (!action || action->percpu_dev_id != dev_id) { | |
1645 | WARN(1, "Trying to free already-free IRQ %d\n", irq); | |
1646 | goto bad; | |
1647 | } | |
1648 | ||
1649 | if (!cpumask_empty(desc->percpu_enabled)) { | |
1650 | WARN(1, "percpu IRQ %d still enabled on CPU%d!\n", | |
1651 | irq, cpumask_first(desc->percpu_enabled)); | |
1652 | goto bad; | |
1653 | } | |
1654 | ||
1655 | /* Found it - now remove it from the list of entries: */ | |
1656 | desc->action = NULL; | |
1657 | ||
1658 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1659 | ||
1660 | unregister_handler_proc(irq, action); | |
1661 | ||
1662 | module_put(desc->owner); | |
1663 | return action; | |
1664 | ||
1665 | bad: | |
1666 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1667 | return NULL; | |
1668 | } | |
1669 | ||
1670 | /** | |
1671 | * remove_percpu_irq - free a per-cpu interrupt | |
1672 | * @irq: Interrupt line to free | |
1673 | * @act: irqaction for the interrupt | |
1674 | * | |
1675 | * Used to remove interrupts statically setup by the early boot process. | |
1676 | */ | |
1677 | void remove_percpu_irq(unsigned int irq, struct irqaction *act) | |
1678 | { | |
1679 | struct irq_desc *desc = irq_to_desc(irq); | |
1680 | ||
1681 | if (desc && irq_settings_is_per_cpu_devid(desc)) | |
1682 | __free_percpu_irq(irq, act->percpu_dev_id); | |
1683 | } | |
1684 | ||
1685 | /** | |
1686 | * free_percpu_irq - free an interrupt allocated with request_percpu_irq | |
1687 | * @irq: Interrupt line to free | |
1688 | * @dev_id: Device identity to free | |
1689 | * | |
1690 | * Remove a percpu interrupt handler. The handler is removed, but | |
1691 | * the interrupt line is not disabled. This must be done on each | |
1692 | * CPU before calling this function. The function does not return | |
1693 | * until any executing interrupts for this IRQ have completed. | |
1694 | * | |
1695 | * This function must not be called from interrupt context. | |
1696 | */ | |
1697 | void free_percpu_irq(unsigned int irq, void __percpu *dev_id) | |
1698 | { | |
1699 | struct irq_desc *desc = irq_to_desc(irq); | |
1700 | ||
1701 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
1702 | return; | |
1703 | ||
1704 | chip_bus_lock(desc); | |
1705 | kfree(__free_percpu_irq(irq, dev_id)); | |
1706 | chip_bus_sync_unlock(desc); | |
1707 | } | |
1708 | ||
1709 | /** | |
1710 | * setup_percpu_irq - setup a per-cpu interrupt | |
1711 | * @irq: Interrupt line to setup | |
1712 | * @act: irqaction for the interrupt | |
1713 | * | |
1714 | * Used to statically setup per-cpu interrupts in the early boot process. | |
1715 | */ | |
1716 | int setup_percpu_irq(unsigned int irq, struct irqaction *act) | |
1717 | { | |
1718 | struct irq_desc *desc = irq_to_desc(irq); | |
1719 | int retval; | |
1720 | ||
1721 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
1722 | return -EINVAL; | |
1723 | chip_bus_lock(desc); | |
1724 | retval = __setup_irq(irq, desc, act); | |
1725 | chip_bus_sync_unlock(desc); | |
1726 | ||
1727 | return retval; | |
1728 | } | |
1729 | ||
1730 | /** | |
1731 | * request_percpu_irq - allocate a percpu interrupt line | |
1732 | * @irq: Interrupt line to allocate | |
1733 | * @handler: Function to be called when the IRQ occurs. | |
1734 | * @devname: An ascii name for the claiming device | |
1735 | * @dev_id: A percpu cookie passed back to the handler function | |
1736 | * | |
1737 | * This call allocates interrupt resources, but doesn't | |
1738 | * automatically enable the interrupt. It has to be done on each | |
1739 | * CPU using enable_percpu_irq(). | |
1740 | * | |
1741 | * Dev_id must be globally unique. It is a per-cpu variable, and | |
1742 | * the handler gets called with the interrupted CPU's instance of | |
1743 | * that variable. | |
1744 | */ | |
1745 | int request_percpu_irq(unsigned int irq, irq_handler_t handler, | |
1746 | const char *devname, void __percpu *dev_id) | |
1747 | { | |
1748 | struct irqaction *action; | |
1749 | struct irq_desc *desc; | |
1750 | int retval; | |
1751 | ||
1752 | if (!dev_id) | |
1753 | return -EINVAL; | |
1754 | ||
1755 | desc = irq_to_desc(irq); | |
1756 | if (!desc || !irq_settings_can_request(desc) || | |
1757 | !irq_settings_is_per_cpu_devid(desc)) | |
1758 | return -EINVAL; | |
1759 | ||
1760 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); | |
1761 | if (!action) | |
1762 | return -ENOMEM; | |
1763 | ||
1764 | action->handler = handler; | |
2ed0e645 | 1765 | action->flags = IRQF_PERCPU | IRQF_NO_SUSPEND; |
31d9d9b6 MZ |
1766 | action->name = devname; |
1767 | action->percpu_dev_id = dev_id; | |
1768 | ||
1769 | chip_bus_lock(desc); | |
1770 | retval = __setup_irq(irq, desc, action); | |
1771 | chip_bus_sync_unlock(desc); | |
1772 | ||
1773 | if (retval) | |
1774 | kfree(action); | |
1775 | ||
1776 | return retval; | |
1777 | } |