]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/kernel/irq/manage.c | |
3 | * | |
a34db9b2 IM |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
5 | * Copyright (C) 2005-2006 Thomas Gleixner | |
1da177e4 LT |
6 | * |
7 | * This file contains driver APIs to the irq subsystem. | |
8 | */ | |
9 | ||
97fd75b7 AM |
10 | #define pr_fmt(fmt) "genirq: " fmt |
11 | ||
1da177e4 | 12 | #include <linux/irq.h> |
3aa551c9 | 13 | #include <linux/kthread.h> |
1da177e4 LT |
14 | #include <linux/module.h> |
15 | #include <linux/random.h> | |
16 | #include <linux/interrupt.h> | |
1aeb272c | 17 | #include <linux/slab.h> |
3aa551c9 | 18 | #include <linux/sched.h> |
8bd75c77 | 19 | #include <linux/sched/rt.h> |
4d1d61a6 | 20 | #include <linux/task_work.h> |
1da177e4 LT |
21 | |
22 | #include "internals.h" | |
23 | ||
8d32a307 TG |
24 | #ifdef CONFIG_IRQ_FORCED_THREADING |
25 | __read_mostly bool force_irqthreads; | |
26 | ||
27 | static int __init setup_forced_irqthreads(char *arg) | |
28 | { | |
29 | force_irqthreads = true; | |
30 | return 0; | |
31 | } | |
32 | early_param("threadirqs", setup_forced_irqthreads); | |
33 | #endif | |
34 | ||
18258f72 | 35 | static void __synchronize_hardirq(struct irq_desc *desc) |
1da177e4 | 36 | { |
32f4125e | 37 | bool inprogress; |
1da177e4 | 38 | |
a98ce5c6 HX |
39 | do { |
40 | unsigned long flags; | |
41 | ||
42 | /* | |
43 | * Wait until we're out of the critical section. This might | |
44 | * give the wrong answer due to the lack of memory barriers. | |
45 | */ | |
32f4125e | 46 | while (irqd_irq_inprogress(&desc->irq_data)) |
a98ce5c6 HX |
47 | cpu_relax(); |
48 | ||
49 | /* Ok, that indicated we're done: double-check carefully. */ | |
239007b8 | 50 | raw_spin_lock_irqsave(&desc->lock, flags); |
32f4125e | 51 | inprogress = irqd_irq_inprogress(&desc->irq_data); |
239007b8 | 52 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
a98ce5c6 HX |
53 | |
54 | /* Oops, that failed? */ | |
32f4125e | 55 | } while (inprogress); |
18258f72 TG |
56 | } |
57 | ||
58 | /** | |
59 | * synchronize_hardirq - wait for pending hard IRQ handlers (on other CPUs) | |
60 | * @irq: interrupt number to wait for | |
61 | * | |
62 | * This function waits for any pending hard IRQ handlers for this | |
63 | * interrupt to complete before returning. If you use this | |
64 | * function while holding a resource the IRQ handler may need you | |
65 | * will deadlock. It does not take associated threaded handlers | |
66 | * into account. | |
67 | * | |
68 | * Do not use this for shutdown scenarios where you must be sure | |
69 | * that all parts (hardirq and threaded handler) have completed. | |
70 | * | |
71 | * This function may be called - with care - from IRQ context. | |
72 | */ | |
73 | void synchronize_hardirq(unsigned int irq) | |
74 | { | |
75 | struct irq_desc *desc = irq_to_desc(irq); | |
3aa551c9 | 76 | |
18258f72 TG |
77 | if (desc) |
78 | __synchronize_hardirq(desc); | |
79 | } | |
80 | EXPORT_SYMBOL(synchronize_hardirq); | |
81 | ||
82 | /** | |
83 | * synchronize_irq - wait for pending IRQ handlers (on other CPUs) | |
84 | * @irq: interrupt number to wait for | |
85 | * | |
86 | * This function waits for any pending IRQ handlers for this interrupt | |
87 | * to complete before returning. If you use this function while | |
88 | * holding a resource the IRQ handler may need you will deadlock. | |
89 | * | |
90 | * This function may be called - with care - from IRQ context. | |
91 | */ | |
92 | void synchronize_irq(unsigned int irq) | |
93 | { | |
94 | struct irq_desc *desc = irq_to_desc(irq); | |
95 | ||
96 | if (desc) { | |
97 | __synchronize_hardirq(desc); | |
98 | /* | |
99 | * We made sure that no hardirq handler is | |
100 | * running. Now verify that no threaded handlers are | |
101 | * active. | |
102 | */ | |
103 | wait_event(desc->wait_for_threads, | |
104 | !atomic_read(&desc->threads_active)); | |
105 | } | |
1da177e4 | 106 | } |
1da177e4 LT |
107 | EXPORT_SYMBOL(synchronize_irq); |
108 | ||
3aa551c9 TG |
109 | #ifdef CONFIG_SMP |
110 | cpumask_var_t irq_default_affinity; | |
111 | ||
771ee3b0 TG |
112 | /** |
113 | * irq_can_set_affinity - Check if the affinity of a given irq can be set | |
114 | * @irq: Interrupt to check | |
115 | * | |
116 | */ | |
117 | int irq_can_set_affinity(unsigned int irq) | |
118 | { | |
08678b08 | 119 | struct irq_desc *desc = irq_to_desc(irq); |
771ee3b0 | 120 | |
bce43032 TG |
121 | if (!desc || !irqd_can_balance(&desc->irq_data) || |
122 | !desc->irq_data.chip || !desc->irq_data.chip->irq_set_affinity) | |
771ee3b0 TG |
123 | return 0; |
124 | ||
125 | return 1; | |
126 | } | |
127 | ||
591d2fb0 TG |
128 | /** |
129 | * irq_set_thread_affinity - Notify irq threads to adjust affinity | |
130 | * @desc: irq descriptor which has affitnity changed | |
131 | * | |
132 | * We just set IRQTF_AFFINITY and delegate the affinity setting | |
133 | * to the interrupt thread itself. We can not call | |
134 | * set_cpus_allowed_ptr() here as we hold desc->lock and this | |
135 | * code can be called from hard interrupt context. | |
136 | */ | |
137 | void irq_set_thread_affinity(struct irq_desc *desc) | |
3aa551c9 TG |
138 | { |
139 | struct irqaction *action = desc->action; | |
140 | ||
141 | while (action) { | |
142 | if (action->thread) | |
591d2fb0 | 143 | set_bit(IRQTF_AFFINITY, &action->thread_flags); |
3aa551c9 TG |
144 | action = action->next; |
145 | } | |
146 | } | |
147 | ||
1fa46f1f | 148 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
0ef5ca1e | 149 | static inline bool irq_can_move_pcntxt(struct irq_data *data) |
1fa46f1f | 150 | { |
0ef5ca1e | 151 | return irqd_can_move_in_process_context(data); |
1fa46f1f | 152 | } |
0ef5ca1e | 153 | static inline bool irq_move_pending(struct irq_data *data) |
1fa46f1f | 154 | { |
0ef5ca1e | 155 | return irqd_is_setaffinity_pending(data); |
1fa46f1f TG |
156 | } |
157 | static inline void | |
158 | irq_copy_pending(struct irq_desc *desc, const struct cpumask *mask) | |
159 | { | |
160 | cpumask_copy(desc->pending_mask, mask); | |
161 | } | |
162 | static inline void | |
163 | irq_get_pending(struct cpumask *mask, struct irq_desc *desc) | |
164 | { | |
165 | cpumask_copy(mask, desc->pending_mask); | |
166 | } | |
167 | #else | |
0ef5ca1e | 168 | static inline bool irq_can_move_pcntxt(struct irq_data *data) { return true; } |
cd22c0e4 | 169 | static inline bool irq_move_pending(struct irq_data *data) { return false; } |
1fa46f1f TG |
170 | static inline void |
171 | irq_copy_pending(struct irq_desc *desc, const struct cpumask *mask) { } | |
172 | static inline void | |
173 | irq_get_pending(struct cpumask *mask, struct irq_desc *desc) { } | |
174 | #endif | |
175 | ||
818b0f3b JL |
176 | int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask, |
177 | bool force) | |
178 | { | |
179 | struct irq_desc *desc = irq_data_to_desc(data); | |
180 | struct irq_chip *chip = irq_data_get_irq_chip(data); | |
181 | int ret; | |
182 | ||
01f8fa4f | 183 | ret = chip->irq_set_affinity(data, mask, force); |
818b0f3b JL |
184 | switch (ret) { |
185 | case IRQ_SET_MASK_OK: | |
186 | cpumask_copy(data->affinity, mask); | |
187 | case IRQ_SET_MASK_OK_NOCOPY: | |
188 | irq_set_thread_affinity(desc); | |
189 | ret = 0; | |
190 | } | |
191 | ||
192 | return ret; | |
193 | } | |
194 | ||
01f8fa4f TG |
195 | int irq_set_affinity_locked(struct irq_data *data, const struct cpumask *mask, |
196 | bool force) | |
771ee3b0 | 197 | { |
c2d0c555 DD |
198 | struct irq_chip *chip = irq_data_get_irq_chip(data); |
199 | struct irq_desc *desc = irq_data_to_desc(data); | |
1fa46f1f | 200 | int ret = 0; |
771ee3b0 | 201 | |
c2d0c555 | 202 | if (!chip || !chip->irq_set_affinity) |
771ee3b0 TG |
203 | return -EINVAL; |
204 | ||
0ef5ca1e | 205 | if (irq_can_move_pcntxt(data)) { |
01f8fa4f | 206 | ret = irq_do_set_affinity(data, mask, force); |
1fa46f1f | 207 | } else { |
c2d0c555 | 208 | irqd_set_move_pending(data); |
1fa46f1f | 209 | irq_copy_pending(desc, mask); |
57b150cc | 210 | } |
1fa46f1f | 211 | |
cd7eab44 BH |
212 | if (desc->affinity_notify) { |
213 | kref_get(&desc->affinity_notify->kref); | |
214 | schedule_work(&desc->affinity_notify->work); | |
215 | } | |
c2d0c555 DD |
216 | irqd_set(data, IRQD_AFFINITY_SET); |
217 | ||
218 | return ret; | |
219 | } | |
220 | ||
01f8fa4f | 221 | int __irq_set_affinity(unsigned int irq, const struct cpumask *mask, bool force) |
c2d0c555 DD |
222 | { |
223 | struct irq_desc *desc = irq_to_desc(irq); | |
224 | unsigned long flags; | |
225 | int ret; | |
226 | ||
227 | if (!desc) | |
228 | return -EINVAL; | |
229 | ||
230 | raw_spin_lock_irqsave(&desc->lock, flags); | |
01f8fa4f | 231 | ret = irq_set_affinity_locked(irq_desc_get_irq_data(desc), mask, force); |
239007b8 | 232 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1fa46f1f | 233 | return ret; |
771ee3b0 TG |
234 | } |
235 | ||
e7a297b0 PWJ |
236 | int irq_set_affinity_hint(unsigned int irq, const struct cpumask *m) |
237 | { | |
e7a297b0 | 238 | unsigned long flags; |
31d9d9b6 | 239 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
e7a297b0 PWJ |
240 | |
241 | if (!desc) | |
242 | return -EINVAL; | |
e7a297b0 | 243 | desc->affinity_hint = m; |
02725e74 | 244 | irq_put_desc_unlock(desc, flags); |
e7a297b0 PWJ |
245 | return 0; |
246 | } | |
247 | EXPORT_SYMBOL_GPL(irq_set_affinity_hint); | |
248 | ||
cd7eab44 BH |
249 | static void irq_affinity_notify(struct work_struct *work) |
250 | { | |
251 | struct irq_affinity_notify *notify = | |
252 | container_of(work, struct irq_affinity_notify, work); | |
253 | struct irq_desc *desc = irq_to_desc(notify->irq); | |
254 | cpumask_var_t cpumask; | |
255 | unsigned long flags; | |
256 | ||
1fa46f1f | 257 | if (!desc || !alloc_cpumask_var(&cpumask, GFP_KERNEL)) |
cd7eab44 BH |
258 | goto out; |
259 | ||
260 | raw_spin_lock_irqsave(&desc->lock, flags); | |
0ef5ca1e | 261 | if (irq_move_pending(&desc->irq_data)) |
1fa46f1f | 262 | irq_get_pending(cpumask, desc); |
cd7eab44 | 263 | else |
1fb0ef31 | 264 | cpumask_copy(cpumask, desc->irq_data.affinity); |
cd7eab44 BH |
265 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
266 | ||
267 | notify->notify(notify, cpumask); | |
268 | ||
269 | free_cpumask_var(cpumask); | |
270 | out: | |
271 | kref_put(¬ify->kref, notify->release); | |
272 | } | |
273 | ||
274 | /** | |
275 | * irq_set_affinity_notifier - control notification of IRQ affinity changes | |
276 | * @irq: Interrupt for which to enable/disable notification | |
277 | * @notify: Context for notification, or %NULL to disable | |
278 | * notification. Function pointers must be initialised; | |
279 | * the other fields will be initialised by this function. | |
280 | * | |
281 | * Must be called in process context. Notification may only be enabled | |
282 | * after the IRQ is allocated and must be disabled before the IRQ is | |
283 | * freed using free_irq(). | |
284 | */ | |
285 | int | |
286 | irq_set_affinity_notifier(unsigned int irq, struct irq_affinity_notify *notify) | |
287 | { | |
288 | struct irq_desc *desc = irq_to_desc(irq); | |
289 | struct irq_affinity_notify *old_notify; | |
290 | unsigned long flags; | |
291 | ||
292 | /* The release function is promised process context */ | |
293 | might_sleep(); | |
294 | ||
295 | if (!desc) | |
296 | return -EINVAL; | |
297 | ||
298 | /* Complete initialisation of *notify */ | |
299 | if (notify) { | |
300 | notify->irq = irq; | |
301 | kref_init(¬ify->kref); | |
302 | INIT_WORK(¬ify->work, irq_affinity_notify); | |
303 | } | |
304 | ||
305 | raw_spin_lock_irqsave(&desc->lock, flags); | |
306 | old_notify = desc->affinity_notify; | |
307 | desc->affinity_notify = notify; | |
308 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
309 | ||
310 | if (old_notify) | |
311 | kref_put(&old_notify->kref, old_notify->release); | |
312 | ||
313 | return 0; | |
314 | } | |
315 | EXPORT_SYMBOL_GPL(irq_set_affinity_notifier); | |
316 | ||
18404756 MK |
317 | #ifndef CONFIG_AUTO_IRQ_AFFINITY |
318 | /* | |
319 | * Generic version of the affinity autoselector. | |
320 | */ | |
3b8249e7 TG |
321 | static int |
322 | setup_affinity(unsigned int irq, struct irq_desc *desc, struct cpumask *mask) | |
18404756 | 323 | { |
569bda8d | 324 | struct cpumask *set = irq_default_affinity; |
818b0f3b | 325 | int node = desc->irq_data.node; |
569bda8d | 326 | |
b008207c | 327 | /* Excludes PER_CPU and NO_BALANCE interrupts */ |
18404756 MK |
328 | if (!irq_can_set_affinity(irq)) |
329 | return 0; | |
330 | ||
f6d87f4b TG |
331 | /* |
332 | * Preserve an userspace affinity setup, but make sure that | |
333 | * one of the targets is online. | |
334 | */ | |
2bdd1055 | 335 | if (irqd_has_set(&desc->irq_data, IRQD_AFFINITY_SET)) { |
569bda8d TG |
336 | if (cpumask_intersects(desc->irq_data.affinity, |
337 | cpu_online_mask)) | |
338 | set = desc->irq_data.affinity; | |
0c6f8a8b | 339 | else |
2bdd1055 | 340 | irqd_clear(&desc->irq_data, IRQD_AFFINITY_SET); |
f6d87f4b | 341 | } |
18404756 | 342 | |
3b8249e7 | 343 | cpumask_and(mask, cpu_online_mask, set); |
241fc640 PB |
344 | if (node != NUMA_NO_NODE) { |
345 | const struct cpumask *nodemask = cpumask_of_node(node); | |
346 | ||
347 | /* make sure at least one of the cpus in nodemask is online */ | |
348 | if (cpumask_intersects(mask, nodemask)) | |
349 | cpumask_and(mask, mask, nodemask); | |
350 | } | |
818b0f3b | 351 | irq_do_set_affinity(&desc->irq_data, mask, false); |
18404756 MK |
352 | return 0; |
353 | } | |
f6d87f4b | 354 | #else |
3b8249e7 TG |
355 | static inline int |
356 | setup_affinity(unsigned int irq, struct irq_desc *d, struct cpumask *mask) | |
f6d87f4b TG |
357 | { |
358 | return irq_select_affinity(irq); | |
359 | } | |
18404756 MK |
360 | #endif |
361 | ||
f6d87f4b TG |
362 | /* |
363 | * Called when affinity is set via /proc/irq | |
364 | */ | |
3b8249e7 | 365 | int irq_select_affinity_usr(unsigned int irq, struct cpumask *mask) |
f6d87f4b TG |
366 | { |
367 | struct irq_desc *desc = irq_to_desc(irq); | |
368 | unsigned long flags; | |
369 | int ret; | |
370 | ||
239007b8 | 371 | raw_spin_lock_irqsave(&desc->lock, flags); |
3b8249e7 | 372 | ret = setup_affinity(irq, desc, mask); |
239007b8 | 373 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
f6d87f4b TG |
374 | return ret; |
375 | } | |
376 | ||
377 | #else | |
3b8249e7 TG |
378 | static inline int |
379 | setup_affinity(unsigned int irq, struct irq_desc *desc, struct cpumask *mask) | |
f6d87f4b TG |
380 | { |
381 | return 0; | |
382 | } | |
1da177e4 LT |
383 | #endif |
384 | ||
8df2e02c | 385 | void __disable_irq(struct irq_desc *desc, unsigned int irq) |
0a0c5168 | 386 | { |
3aae994f | 387 | if (!desc->depth++) |
87923470 | 388 | irq_disable(desc); |
0a0c5168 RW |
389 | } |
390 | ||
02725e74 TG |
391 | static int __disable_irq_nosync(unsigned int irq) |
392 | { | |
393 | unsigned long flags; | |
31d9d9b6 | 394 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
02725e74 TG |
395 | |
396 | if (!desc) | |
397 | return -EINVAL; | |
8df2e02c | 398 | __disable_irq(desc, irq); |
02725e74 TG |
399 | irq_put_desc_busunlock(desc, flags); |
400 | return 0; | |
401 | } | |
402 | ||
1da177e4 LT |
403 | /** |
404 | * disable_irq_nosync - disable an irq without waiting | |
405 | * @irq: Interrupt to disable | |
406 | * | |
407 | * Disable the selected interrupt line. Disables and Enables are | |
408 | * nested. | |
409 | * Unlike disable_irq(), this function does not ensure existing | |
410 | * instances of the IRQ handler have completed before returning. | |
411 | * | |
412 | * This function may be called from IRQ context. | |
413 | */ | |
414 | void disable_irq_nosync(unsigned int irq) | |
415 | { | |
02725e74 | 416 | __disable_irq_nosync(irq); |
1da177e4 | 417 | } |
1da177e4 LT |
418 | EXPORT_SYMBOL(disable_irq_nosync); |
419 | ||
420 | /** | |
421 | * disable_irq - disable an irq and wait for completion | |
422 | * @irq: Interrupt to disable | |
423 | * | |
424 | * Disable the selected interrupt line. Enables and Disables are | |
425 | * nested. | |
426 | * This function waits for any pending IRQ handlers for this interrupt | |
427 | * to complete before returning. If you use this function while | |
428 | * holding a resource the IRQ handler may need you will deadlock. | |
429 | * | |
430 | * This function may be called - with care - from IRQ context. | |
431 | */ | |
432 | void disable_irq(unsigned int irq) | |
433 | { | |
02725e74 | 434 | if (!__disable_irq_nosync(irq)) |
1da177e4 LT |
435 | synchronize_irq(irq); |
436 | } | |
1da177e4 LT |
437 | EXPORT_SYMBOL(disable_irq); |
438 | ||
8df2e02c | 439 | void __enable_irq(struct irq_desc *desc, unsigned int irq) |
1adb0850 TG |
440 | { |
441 | switch (desc->depth) { | |
442 | case 0: | |
0a0c5168 | 443 | err_out: |
b8c512f6 | 444 | WARN(1, KERN_WARNING "Unbalanced enable for IRQ %d\n", irq); |
1adb0850 TG |
445 | break; |
446 | case 1: { | |
c531e836 | 447 | if (desc->istate & IRQS_SUSPENDED) |
0a0c5168 | 448 | goto err_out; |
1adb0850 | 449 | /* Prevent probing on this irq: */ |
1ccb4e61 | 450 | irq_settings_set_noprobe(desc); |
3aae994f | 451 | irq_enable(desc); |
1adb0850 TG |
452 | check_irq_resend(desc, irq); |
453 | /* fall-through */ | |
454 | } | |
455 | default: | |
456 | desc->depth--; | |
457 | } | |
458 | } | |
459 | ||
1da177e4 LT |
460 | /** |
461 | * enable_irq - enable handling of an irq | |
462 | * @irq: Interrupt to enable | |
463 | * | |
464 | * Undoes the effect of one call to disable_irq(). If this | |
465 | * matches the last disable, processing of interrupts on this | |
466 | * IRQ line is re-enabled. | |
467 | * | |
70aedd24 | 468 | * This function may be called from IRQ context only when |
6b8ff312 | 469 | * desc->irq_data.chip->bus_lock and desc->chip->bus_sync_unlock are NULL ! |
1da177e4 LT |
470 | */ |
471 | void enable_irq(unsigned int irq) | |
472 | { | |
1da177e4 | 473 | unsigned long flags; |
31d9d9b6 | 474 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
1da177e4 | 475 | |
7d94f7ca | 476 | if (!desc) |
c2b5a251 | 477 | return; |
50f7c032 TG |
478 | if (WARN(!desc->irq_data.chip, |
479 | KERN_ERR "enable_irq before setup/request_irq: irq %u\n", irq)) | |
02725e74 | 480 | goto out; |
2656c366 | 481 | |
8df2e02c | 482 | __enable_irq(desc, irq); |
02725e74 TG |
483 | out: |
484 | irq_put_desc_busunlock(desc, flags); | |
1da177e4 | 485 | } |
1da177e4 LT |
486 | EXPORT_SYMBOL(enable_irq); |
487 | ||
0c5d1eb7 | 488 | static int set_irq_wake_real(unsigned int irq, unsigned int on) |
2db87321 | 489 | { |
08678b08 | 490 | struct irq_desc *desc = irq_to_desc(irq); |
2db87321 UKK |
491 | int ret = -ENXIO; |
492 | ||
60f96b41 SS |
493 | if (irq_desc_get_chip(desc)->flags & IRQCHIP_SKIP_SET_WAKE) |
494 | return 0; | |
495 | ||
2f7e99bb TG |
496 | if (desc->irq_data.chip->irq_set_wake) |
497 | ret = desc->irq_data.chip->irq_set_wake(&desc->irq_data, on); | |
2db87321 UKK |
498 | |
499 | return ret; | |
500 | } | |
501 | ||
ba9a2331 | 502 | /** |
a0cd9ca2 | 503 | * irq_set_irq_wake - control irq power management wakeup |
ba9a2331 TG |
504 | * @irq: interrupt to control |
505 | * @on: enable/disable power management wakeup | |
506 | * | |
15a647eb DB |
507 | * Enable/disable power management wakeup mode, which is |
508 | * disabled by default. Enables and disables must match, | |
509 | * just as they match for non-wakeup mode support. | |
510 | * | |
511 | * Wakeup mode lets this IRQ wake the system from sleep | |
512 | * states like "suspend to RAM". | |
ba9a2331 | 513 | */ |
a0cd9ca2 | 514 | int irq_set_irq_wake(unsigned int irq, unsigned int on) |
ba9a2331 | 515 | { |
ba9a2331 | 516 | unsigned long flags; |
31d9d9b6 | 517 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
2db87321 | 518 | int ret = 0; |
ba9a2331 | 519 | |
13863a66 JJ |
520 | if (!desc) |
521 | return -EINVAL; | |
522 | ||
15a647eb DB |
523 | /* wakeup-capable irqs can be shared between drivers that |
524 | * don't need to have the same sleep mode behaviors. | |
525 | */ | |
15a647eb | 526 | if (on) { |
2db87321 UKK |
527 | if (desc->wake_depth++ == 0) { |
528 | ret = set_irq_wake_real(irq, on); | |
529 | if (ret) | |
530 | desc->wake_depth = 0; | |
531 | else | |
7f94226f | 532 | irqd_set(&desc->irq_data, IRQD_WAKEUP_STATE); |
2db87321 | 533 | } |
15a647eb DB |
534 | } else { |
535 | if (desc->wake_depth == 0) { | |
7a2c4770 | 536 | WARN(1, "Unbalanced IRQ %d wake disable\n", irq); |
2db87321 UKK |
537 | } else if (--desc->wake_depth == 0) { |
538 | ret = set_irq_wake_real(irq, on); | |
539 | if (ret) | |
540 | desc->wake_depth = 1; | |
541 | else | |
7f94226f | 542 | irqd_clear(&desc->irq_data, IRQD_WAKEUP_STATE); |
2db87321 | 543 | } |
15a647eb | 544 | } |
02725e74 | 545 | irq_put_desc_busunlock(desc, flags); |
ba9a2331 TG |
546 | return ret; |
547 | } | |
a0cd9ca2 | 548 | EXPORT_SYMBOL(irq_set_irq_wake); |
ba9a2331 | 549 | |
1da177e4 LT |
550 | /* |
551 | * Internal function that tells the architecture code whether a | |
552 | * particular irq has been exclusively allocated or is available | |
553 | * for driver use. | |
554 | */ | |
555 | int can_request_irq(unsigned int irq, unsigned long irqflags) | |
556 | { | |
cc8c3b78 | 557 | unsigned long flags; |
31d9d9b6 | 558 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
02725e74 | 559 | int canrequest = 0; |
1da177e4 | 560 | |
7d94f7ca YL |
561 | if (!desc) |
562 | return 0; | |
563 | ||
02725e74 | 564 | if (irq_settings_can_request(desc)) { |
2779db8d BH |
565 | if (!desc->action || |
566 | irqflags & desc->action->flags & IRQF_SHARED) | |
567 | canrequest = 1; | |
02725e74 TG |
568 | } |
569 | irq_put_desc_unlock(desc, flags); | |
570 | return canrequest; | |
1da177e4 LT |
571 | } |
572 | ||
0c5d1eb7 | 573 | int __irq_set_trigger(struct irq_desc *desc, unsigned int irq, |
b2ba2c30 | 574 | unsigned long flags) |
82736f4d | 575 | { |
6b8ff312 | 576 | struct irq_chip *chip = desc->irq_data.chip; |
d4d5e089 | 577 | int ret, unmask = 0; |
82736f4d | 578 | |
b2ba2c30 | 579 | if (!chip || !chip->irq_set_type) { |
82736f4d UKK |
580 | /* |
581 | * IRQF_TRIGGER_* but the PIC does not support multiple | |
582 | * flow-types? | |
583 | */ | |
97fd75b7 | 584 | pr_debug("No set_type function for IRQ %d (%s)\n", irq, |
f5d89470 | 585 | chip ? (chip->name ? : "unknown") : "unknown"); |
82736f4d UKK |
586 | return 0; |
587 | } | |
588 | ||
876dbd4c | 589 | flags &= IRQ_TYPE_SENSE_MASK; |
d4d5e089 TG |
590 | |
591 | if (chip->flags & IRQCHIP_SET_TYPE_MASKED) { | |
32f4125e | 592 | if (!irqd_irq_masked(&desc->irq_data)) |
d4d5e089 | 593 | mask_irq(desc); |
32f4125e | 594 | if (!irqd_irq_disabled(&desc->irq_data)) |
d4d5e089 TG |
595 | unmask = 1; |
596 | } | |
597 | ||
f2b662da | 598 | /* caller masked out all except trigger mode flags */ |
b2ba2c30 | 599 | ret = chip->irq_set_type(&desc->irq_data, flags); |
82736f4d | 600 | |
876dbd4c TG |
601 | switch (ret) { |
602 | case IRQ_SET_MASK_OK: | |
603 | irqd_clear(&desc->irq_data, IRQD_TRIGGER_MASK); | |
604 | irqd_set(&desc->irq_data, flags); | |
605 | ||
606 | case IRQ_SET_MASK_OK_NOCOPY: | |
607 | flags = irqd_get_trigger_type(&desc->irq_data); | |
608 | irq_settings_set_trigger_mask(desc, flags); | |
609 | irqd_clear(&desc->irq_data, IRQD_LEVEL); | |
610 | irq_settings_clr_level(desc); | |
611 | if (flags & IRQ_TYPE_LEVEL_MASK) { | |
612 | irq_settings_set_level(desc); | |
613 | irqd_set(&desc->irq_data, IRQD_LEVEL); | |
614 | } | |
46732475 | 615 | |
d4d5e089 | 616 | ret = 0; |
8fff39e0 | 617 | break; |
876dbd4c | 618 | default: |
97fd75b7 | 619 | pr_err("Setting trigger mode %lu for irq %u failed (%pF)\n", |
876dbd4c | 620 | flags, irq, chip->irq_set_type); |
0c5d1eb7 | 621 | } |
d4d5e089 TG |
622 | if (unmask) |
623 | unmask_irq(desc); | |
82736f4d UKK |
624 | return ret; |
625 | } | |
626 | ||
293a7a0a TG |
627 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
628 | int irq_set_parent(int irq, int parent_irq) | |
629 | { | |
630 | unsigned long flags; | |
631 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | |
632 | ||
633 | if (!desc) | |
634 | return -EINVAL; | |
635 | ||
636 | desc->parent_irq = parent_irq; | |
637 | ||
638 | irq_put_desc_unlock(desc, flags); | |
639 | return 0; | |
640 | } | |
641 | #endif | |
642 | ||
b25c340c TG |
643 | /* |
644 | * Default primary interrupt handler for threaded interrupts. Is | |
645 | * assigned as primary handler when request_threaded_irq is called | |
646 | * with handler == NULL. Useful for oneshot interrupts. | |
647 | */ | |
648 | static irqreturn_t irq_default_primary_handler(int irq, void *dev_id) | |
649 | { | |
650 | return IRQ_WAKE_THREAD; | |
651 | } | |
652 | ||
399b5da2 TG |
653 | /* |
654 | * Primary handler for nested threaded interrupts. Should never be | |
655 | * called. | |
656 | */ | |
657 | static irqreturn_t irq_nested_primary_handler(int irq, void *dev_id) | |
658 | { | |
659 | WARN(1, "Primary handler called for nested irq %d\n", irq); | |
660 | return IRQ_NONE; | |
661 | } | |
662 | ||
3aa551c9 TG |
663 | static int irq_wait_for_interrupt(struct irqaction *action) |
664 | { | |
550acb19 IY |
665 | set_current_state(TASK_INTERRUPTIBLE); |
666 | ||
3aa551c9 | 667 | while (!kthread_should_stop()) { |
f48fe81e TG |
668 | |
669 | if (test_and_clear_bit(IRQTF_RUNTHREAD, | |
670 | &action->thread_flags)) { | |
3aa551c9 TG |
671 | __set_current_state(TASK_RUNNING); |
672 | return 0; | |
f48fe81e TG |
673 | } |
674 | schedule(); | |
550acb19 | 675 | set_current_state(TASK_INTERRUPTIBLE); |
3aa551c9 | 676 | } |
550acb19 | 677 | __set_current_state(TASK_RUNNING); |
3aa551c9 TG |
678 | return -1; |
679 | } | |
680 | ||
b25c340c TG |
681 | /* |
682 | * Oneshot interrupts keep the irq line masked until the threaded | |
683 | * handler finished. unmask if the interrupt has not been disabled and | |
684 | * is marked MASKED. | |
685 | */ | |
b5faba21 | 686 | static void irq_finalize_oneshot(struct irq_desc *desc, |
f3f79e38 | 687 | struct irqaction *action) |
b25c340c | 688 | { |
b5faba21 TG |
689 | if (!(desc->istate & IRQS_ONESHOT)) |
690 | return; | |
0b1adaa0 | 691 | again: |
3876ec9e | 692 | chip_bus_lock(desc); |
239007b8 | 693 | raw_spin_lock_irq(&desc->lock); |
0b1adaa0 TG |
694 | |
695 | /* | |
696 | * Implausible though it may be we need to protect us against | |
697 | * the following scenario: | |
698 | * | |
699 | * The thread is faster done than the hard interrupt handler | |
700 | * on the other CPU. If we unmask the irq line then the | |
701 | * interrupt can come in again and masks the line, leaves due | |
009b4c3b | 702 | * to IRQS_INPROGRESS and the irq line is masked forever. |
b5faba21 TG |
703 | * |
704 | * This also serializes the state of shared oneshot handlers | |
705 | * versus "desc->threads_onehsot |= action->thread_mask;" in | |
706 | * irq_wake_thread(). See the comment there which explains the | |
707 | * serialization. | |
0b1adaa0 | 708 | */ |
32f4125e | 709 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) { |
0b1adaa0 | 710 | raw_spin_unlock_irq(&desc->lock); |
3876ec9e | 711 | chip_bus_sync_unlock(desc); |
0b1adaa0 TG |
712 | cpu_relax(); |
713 | goto again; | |
714 | } | |
715 | ||
b5faba21 TG |
716 | /* |
717 | * Now check again, whether the thread should run. Otherwise | |
718 | * we would clear the threads_oneshot bit of this thread which | |
719 | * was just set. | |
720 | */ | |
f3f79e38 | 721 | if (test_bit(IRQTF_RUNTHREAD, &action->thread_flags)) |
b5faba21 TG |
722 | goto out_unlock; |
723 | ||
724 | desc->threads_oneshot &= ~action->thread_mask; | |
725 | ||
32f4125e TG |
726 | if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && |
727 | irqd_irq_masked(&desc->irq_data)) | |
328a4978 | 728 | unmask_threaded_irq(desc); |
32f4125e | 729 | |
b5faba21 | 730 | out_unlock: |
239007b8 | 731 | raw_spin_unlock_irq(&desc->lock); |
3876ec9e | 732 | chip_bus_sync_unlock(desc); |
b25c340c TG |
733 | } |
734 | ||
61f38261 | 735 | #ifdef CONFIG_SMP |
591d2fb0 | 736 | /* |
b04c644e | 737 | * Check whether we need to change the affinity of the interrupt thread. |
591d2fb0 TG |
738 | */ |
739 | static void | |
740 | irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) | |
741 | { | |
742 | cpumask_var_t mask; | |
04aa530e | 743 | bool valid = true; |
591d2fb0 TG |
744 | |
745 | if (!test_and_clear_bit(IRQTF_AFFINITY, &action->thread_flags)) | |
746 | return; | |
747 | ||
748 | /* | |
749 | * In case we are out of memory we set IRQTF_AFFINITY again and | |
750 | * try again next time | |
751 | */ | |
752 | if (!alloc_cpumask_var(&mask, GFP_KERNEL)) { | |
753 | set_bit(IRQTF_AFFINITY, &action->thread_flags); | |
754 | return; | |
755 | } | |
756 | ||
239007b8 | 757 | raw_spin_lock_irq(&desc->lock); |
04aa530e TG |
758 | /* |
759 | * This code is triggered unconditionally. Check the affinity | |
760 | * mask pointer. For CPU_MASK_OFFSTACK=n this is optimized out. | |
761 | */ | |
762 | if (desc->irq_data.affinity) | |
763 | cpumask_copy(mask, desc->irq_data.affinity); | |
764 | else | |
765 | valid = false; | |
239007b8 | 766 | raw_spin_unlock_irq(&desc->lock); |
591d2fb0 | 767 | |
04aa530e TG |
768 | if (valid) |
769 | set_cpus_allowed_ptr(current, mask); | |
591d2fb0 TG |
770 | free_cpumask_var(mask); |
771 | } | |
61f38261 BP |
772 | #else |
773 | static inline void | |
774 | irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) { } | |
775 | #endif | |
591d2fb0 | 776 | |
8d32a307 TG |
777 | /* |
778 | * Interrupts which are not explicitely requested as threaded | |
779 | * interrupts rely on the implicit bh/preempt disable of the hard irq | |
780 | * context. So we need to disable bh here to avoid deadlocks and other | |
781 | * side effects. | |
782 | */ | |
3a43e05f | 783 | static irqreturn_t |
8d32a307 TG |
784 | irq_forced_thread_fn(struct irq_desc *desc, struct irqaction *action) |
785 | { | |
3a43e05f SAS |
786 | irqreturn_t ret; |
787 | ||
8d32a307 | 788 | local_bh_disable(); |
3a43e05f | 789 | ret = action->thread_fn(action->irq, action->dev_id); |
f3f79e38 | 790 | irq_finalize_oneshot(desc, action); |
8d32a307 | 791 | local_bh_enable(); |
3a43e05f | 792 | return ret; |
8d32a307 TG |
793 | } |
794 | ||
795 | /* | |
f788e7bf | 796 | * Interrupts explicitly requested as threaded interrupts want to be |
8d32a307 TG |
797 | * preemtible - many of them need to sleep and wait for slow busses to |
798 | * complete. | |
799 | */ | |
3a43e05f SAS |
800 | static irqreturn_t irq_thread_fn(struct irq_desc *desc, |
801 | struct irqaction *action) | |
8d32a307 | 802 | { |
3a43e05f SAS |
803 | irqreturn_t ret; |
804 | ||
805 | ret = action->thread_fn(action->irq, action->dev_id); | |
f3f79e38 | 806 | irq_finalize_oneshot(desc, action); |
3a43e05f | 807 | return ret; |
8d32a307 TG |
808 | } |
809 | ||
7140ea19 IY |
810 | static void wake_threads_waitq(struct irq_desc *desc) |
811 | { | |
c685689f | 812 | if (atomic_dec_and_test(&desc->threads_active)) |
7140ea19 IY |
813 | wake_up(&desc->wait_for_threads); |
814 | } | |
815 | ||
67d12145 | 816 | static void irq_thread_dtor(struct callback_head *unused) |
4d1d61a6 ON |
817 | { |
818 | struct task_struct *tsk = current; | |
819 | struct irq_desc *desc; | |
820 | struct irqaction *action; | |
821 | ||
822 | if (WARN_ON_ONCE(!(current->flags & PF_EXITING))) | |
823 | return; | |
824 | ||
825 | action = kthread_data(tsk); | |
826 | ||
fb21affa | 827 | pr_err("exiting task \"%s\" (%d) is an active IRQ thread (irq %d)\n", |
19af395d | 828 | tsk->comm, tsk->pid, action->irq); |
4d1d61a6 ON |
829 | |
830 | ||
831 | desc = irq_to_desc(action->irq); | |
832 | /* | |
833 | * If IRQTF_RUNTHREAD is set, we need to decrement | |
834 | * desc->threads_active and wake possible waiters. | |
835 | */ | |
836 | if (test_and_clear_bit(IRQTF_RUNTHREAD, &action->thread_flags)) | |
837 | wake_threads_waitq(desc); | |
838 | ||
839 | /* Prevent a stale desc->threads_oneshot */ | |
840 | irq_finalize_oneshot(desc, action); | |
841 | } | |
842 | ||
3aa551c9 TG |
843 | /* |
844 | * Interrupt handler thread | |
845 | */ | |
846 | static int irq_thread(void *data) | |
847 | { | |
67d12145 | 848 | struct callback_head on_exit_work; |
3aa551c9 TG |
849 | struct irqaction *action = data; |
850 | struct irq_desc *desc = irq_to_desc(action->irq); | |
3a43e05f SAS |
851 | irqreturn_t (*handler_fn)(struct irq_desc *desc, |
852 | struct irqaction *action); | |
3aa551c9 | 853 | |
540b60e2 | 854 | if (force_irqthreads && test_bit(IRQTF_FORCED_THREAD, |
8d32a307 TG |
855 | &action->thread_flags)) |
856 | handler_fn = irq_forced_thread_fn; | |
857 | else | |
858 | handler_fn = irq_thread_fn; | |
859 | ||
41f9d29f | 860 | init_task_work(&on_exit_work, irq_thread_dtor); |
4d1d61a6 | 861 | task_work_add(current, &on_exit_work, false); |
3aa551c9 | 862 | |
f3de44ed SM |
863 | irq_thread_check_affinity(desc, action); |
864 | ||
3aa551c9 | 865 | while (!irq_wait_for_interrupt(action)) { |
7140ea19 | 866 | irqreturn_t action_ret; |
3aa551c9 | 867 | |
591d2fb0 TG |
868 | irq_thread_check_affinity(desc, action); |
869 | ||
7140ea19 | 870 | action_ret = handler_fn(desc, action); |
1e77d0a1 TG |
871 | if (action_ret == IRQ_HANDLED) |
872 | atomic_inc(&desc->threads_handled); | |
3aa551c9 | 873 | |
7140ea19 | 874 | wake_threads_waitq(desc); |
3aa551c9 TG |
875 | } |
876 | ||
7140ea19 IY |
877 | /* |
878 | * This is the regular exit path. __free_irq() is stopping the | |
879 | * thread via kthread_stop() after calling | |
880 | * synchronize_irq(). So neither IRQTF_RUNTHREAD nor the | |
e04268b0 TG |
881 | * oneshot mask bit can be set. We cannot verify that as we |
882 | * cannot touch the oneshot mask at this point anymore as | |
883 | * __setup_irq() might have given out currents thread_mask | |
884 | * again. | |
3aa551c9 | 885 | */ |
4d1d61a6 | 886 | task_work_cancel(current, irq_thread_dtor); |
3aa551c9 TG |
887 | return 0; |
888 | } | |
889 | ||
a92444c6 TG |
890 | /** |
891 | * irq_wake_thread - wake the irq thread for the action identified by dev_id | |
892 | * @irq: Interrupt line | |
893 | * @dev_id: Device identity for which the thread should be woken | |
894 | * | |
895 | */ | |
896 | void irq_wake_thread(unsigned int irq, void *dev_id) | |
897 | { | |
898 | struct irq_desc *desc = irq_to_desc(irq); | |
899 | struct irqaction *action; | |
900 | unsigned long flags; | |
901 | ||
902 | if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
903 | return; | |
904 | ||
905 | raw_spin_lock_irqsave(&desc->lock, flags); | |
906 | for (action = desc->action; action; action = action->next) { | |
907 | if (action->dev_id == dev_id) { | |
908 | if (action->thread) | |
909 | __irq_wake_thread(desc, action); | |
910 | break; | |
911 | } | |
912 | } | |
913 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
914 | } | |
915 | EXPORT_SYMBOL_GPL(irq_wake_thread); | |
916 | ||
8d32a307 TG |
917 | static void irq_setup_forced_threading(struct irqaction *new) |
918 | { | |
919 | if (!force_irqthreads) | |
920 | return; | |
921 | if (new->flags & (IRQF_NO_THREAD | IRQF_PERCPU | IRQF_ONESHOT)) | |
922 | return; | |
923 | ||
924 | new->flags |= IRQF_ONESHOT; | |
925 | ||
926 | if (!new->thread_fn) { | |
927 | set_bit(IRQTF_FORCED_THREAD, &new->thread_flags); | |
928 | new->thread_fn = new->handler; | |
929 | new->handler = irq_default_primary_handler; | |
930 | } | |
931 | } | |
932 | ||
c1bacbae TG |
933 | static int irq_request_resources(struct irq_desc *desc) |
934 | { | |
935 | struct irq_data *d = &desc->irq_data; | |
936 | struct irq_chip *c = d->chip; | |
937 | ||
938 | return c->irq_request_resources ? c->irq_request_resources(d) : 0; | |
939 | } | |
940 | ||
941 | static void irq_release_resources(struct irq_desc *desc) | |
942 | { | |
943 | struct irq_data *d = &desc->irq_data; | |
944 | struct irq_chip *c = d->chip; | |
945 | ||
946 | if (c->irq_release_resources) | |
947 | c->irq_release_resources(d); | |
948 | } | |
949 | ||
1da177e4 LT |
950 | /* |
951 | * Internal function to register an irqaction - typically used to | |
952 | * allocate special interrupts that are part of the architecture. | |
953 | */ | |
d3c60047 | 954 | static int |
327ec569 | 955 | __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) |
1da177e4 | 956 | { |
f17c7545 | 957 | struct irqaction *old, **old_ptr; |
b5faba21 | 958 | unsigned long flags, thread_mask = 0; |
3b8249e7 TG |
959 | int ret, nested, shared = 0; |
960 | cpumask_var_t mask; | |
1da177e4 | 961 | |
7d94f7ca | 962 | if (!desc) |
c2b5a251 MW |
963 | return -EINVAL; |
964 | ||
6b8ff312 | 965 | if (desc->irq_data.chip == &no_irq_chip) |
1da177e4 | 966 | return -ENOSYS; |
b6873807 SAS |
967 | if (!try_module_get(desc->owner)) |
968 | return -ENODEV; | |
1da177e4 | 969 | |
3aa551c9 | 970 | /* |
399b5da2 TG |
971 | * Check whether the interrupt nests into another interrupt |
972 | * thread. | |
973 | */ | |
1ccb4e61 | 974 | nested = irq_settings_is_nested_thread(desc); |
399b5da2 | 975 | if (nested) { |
b6873807 SAS |
976 | if (!new->thread_fn) { |
977 | ret = -EINVAL; | |
978 | goto out_mput; | |
979 | } | |
399b5da2 TG |
980 | /* |
981 | * Replace the primary handler which was provided from | |
982 | * the driver for non nested interrupt handling by the | |
983 | * dummy function which warns when called. | |
984 | */ | |
985 | new->handler = irq_nested_primary_handler; | |
8d32a307 | 986 | } else { |
7f1b1244 PM |
987 | if (irq_settings_can_thread(desc)) |
988 | irq_setup_forced_threading(new); | |
399b5da2 TG |
989 | } |
990 | ||
3aa551c9 | 991 | /* |
399b5da2 TG |
992 | * Create a handler thread when a thread function is supplied |
993 | * and the interrupt does not nest into another interrupt | |
994 | * thread. | |
3aa551c9 | 995 | */ |
399b5da2 | 996 | if (new->thread_fn && !nested) { |
3aa551c9 | 997 | struct task_struct *t; |
ee238713 IS |
998 | static const struct sched_param param = { |
999 | .sched_priority = MAX_USER_RT_PRIO/2, | |
1000 | }; | |
3aa551c9 TG |
1001 | |
1002 | t = kthread_create(irq_thread, new, "irq/%d-%s", irq, | |
1003 | new->name); | |
b6873807 SAS |
1004 | if (IS_ERR(t)) { |
1005 | ret = PTR_ERR(t); | |
1006 | goto out_mput; | |
1007 | } | |
ee238713 | 1008 | |
bbfe65c2 | 1009 | sched_setscheduler_nocheck(t, SCHED_FIFO, ¶m); |
ee238713 | 1010 | |
3aa551c9 TG |
1011 | /* |
1012 | * We keep the reference to the task struct even if | |
1013 | * the thread dies to avoid that the interrupt code | |
1014 | * references an already freed task_struct. | |
1015 | */ | |
1016 | get_task_struct(t); | |
1017 | new->thread = t; | |
04aa530e TG |
1018 | /* |
1019 | * Tell the thread to set its affinity. This is | |
1020 | * important for shared interrupt handlers as we do | |
1021 | * not invoke setup_affinity() for the secondary | |
1022 | * handlers as everything is already set up. Even for | |
1023 | * interrupts marked with IRQF_NO_BALANCE this is | |
1024 | * correct as we want the thread to move to the cpu(s) | |
1025 | * on which the requesting code placed the interrupt. | |
1026 | */ | |
1027 | set_bit(IRQTF_AFFINITY, &new->thread_flags); | |
3aa551c9 TG |
1028 | } |
1029 | ||
3b8249e7 TG |
1030 | if (!alloc_cpumask_var(&mask, GFP_KERNEL)) { |
1031 | ret = -ENOMEM; | |
1032 | goto out_thread; | |
1033 | } | |
1034 | ||
dc9b229a TG |
1035 | /* |
1036 | * Drivers are often written to work w/o knowledge about the | |
1037 | * underlying irq chip implementation, so a request for a | |
1038 | * threaded irq without a primary hard irq context handler | |
1039 | * requires the ONESHOT flag to be set. Some irq chips like | |
1040 | * MSI based interrupts are per se one shot safe. Check the | |
1041 | * chip flags, so we can avoid the unmask dance at the end of | |
1042 | * the threaded handler for those. | |
1043 | */ | |
1044 | if (desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE) | |
1045 | new->flags &= ~IRQF_ONESHOT; | |
1046 | ||
1da177e4 LT |
1047 | /* |
1048 | * The following block of code has to be executed atomically | |
1049 | */ | |
239007b8 | 1050 | raw_spin_lock_irqsave(&desc->lock, flags); |
f17c7545 IM |
1051 | old_ptr = &desc->action; |
1052 | old = *old_ptr; | |
06fcb0c6 | 1053 | if (old) { |
e76de9f8 TG |
1054 | /* |
1055 | * Can't share interrupts unless both agree to and are | |
1056 | * the same type (level, edge, polarity). So both flag | |
3cca53b0 | 1057 | * fields must have IRQF_SHARED set and the bits which |
9d591edd TG |
1058 | * set the trigger type must match. Also all must |
1059 | * agree on ONESHOT. | |
e76de9f8 | 1060 | */ |
3cca53b0 | 1061 | if (!((old->flags & new->flags) & IRQF_SHARED) || |
9d591edd | 1062 | ((old->flags ^ new->flags) & IRQF_TRIGGER_MASK) || |
f5d89470 | 1063 | ((old->flags ^ new->flags) & IRQF_ONESHOT)) |
f5163427 DS |
1064 | goto mismatch; |
1065 | ||
f5163427 | 1066 | /* All handlers must agree on per-cpuness */ |
3cca53b0 TG |
1067 | if ((old->flags & IRQF_PERCPU) != |
1068 | (new->flags & IRQF_PERCPU)) | |
f5163427 | 1069 | goto mismatch; |
1da177e4 LT |
1070 | |
1071 | /* add new interrupt at end of irq queue */ | |
1072 | do { | |
52abb700 TG |
1073 | /* |
1074 | * Or all existing action->thread_mask bits, | |
1075 | * so we can find the next zero bit for this | |
1076 | * new action. | |
1077 | */ | |
b5faba21 | 1078 | thread_mask |= old->thread_mask; |
f17c7545 IM |
1079 | old_ptr = &old->next; |
1080 | old = *old_ptr; | |
1da177e4 LT |
1081 | } while (old); |
1082 | shared = 1; | |
1083 | } | |
1084 | ||
b5faba21 | 1085 | /* |
52abb700 TG |
1086 | * Setup the thread mask for this irqaction for ONESHOT. For |
1087 | * !ONESHOT irqs the thread mask is 0 so we can avoid a | |
1088 | * conditional in irq_wake_thread(). | |
b5faba21 | 1089 | */ |
52abb700 TG |
1090 | if (new->flags & IRQF_ONESHOT) { |
1091 | /* | |
1092 | * Unlikely to have 32 resp 64 irqs sharing one line, | |
1093 | * but who knows. | |
1094 | */ | |
1095 | if (thread_mask == ~0UL) { | |
1096 | ret = -EBUSY; | |
1097 | goto out_mask; | |
1098 | } | |
1099 | /* | |
1100 | * The thread_mask for the action is or'ed to | |
1101 | * desc->thread_active to indicate that the | |
1102 | * IRQF_ONESHOT thread handler has been woken, but not | |
1103 | * yet finished. The bit is cleared when a thread | |
1104 | * completes. When all threads of a shared interrupt | |
1105 | * line have completed desc->threads_active becomes | |
1106 | * zero and the interrupt line is unmasked. See | |
1107 | * handle.c:irq_wake_thread() for further information. | |
1108 | * | |
1109 | * If no thread is woken by primary (hard irq context) | |
1110 | * interrupt handlers, then desc->threads_active is | |
1111 | * also checked for zero to unmask the irq line in the | |
1112 | * affected hard irq flow handlers | |
1113 | * (handle_[fasteoi|level]_irq). | |
1114 | * | |
1115 | * The new action gets the first zero bit of | |
1116 | * thread_mask assigned. See the loop above which or's | |
1117 | * all existing action->thread_mask bits. | |
1118 | */ | |
1119 | new->thread_mask = 1 << ffz(thread_mask); | |
1c6c6952 | 1120 | |
dc9b229a TG |
1121 | } else if (new->handler == irq_default_primary_handler && |
1122 | !(desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE)) { | |
1c6c6952 TG |
1123 | /* |
1124 | * The interrupt was requested with handler = NULL, so | |
1125 | * we use the default primary handler for it. But it | |
1126 | * does not have the oneshot flag set. In combination | |
1127 | * with level interrupts this is deadly, because the | |
1128 | * default primary handler just wakes the thread, then | |
1129 | * the irq lines is reenabled, but the device still | |
1130 | * has the level irq asserted. Rinse and repeat.... | |
1131 | * | |
1132 | * While this works for edge type interrupts, we play | |
1133 | * it safe and reject unconditionally because we can't | |
1134 | * say for sure which type this interrupt really | |
1135 | * has. The type flags are unreliable as the | |
1136 | * underlying chip implementation can override them. | |
1137 | */ | |
97fd75b7 | 1138 | pr_err("Threaded irq requested with handler=NULL and !ONESHOT for irq %d\n", |
1c6c6952 TG |
1139 | irq); |
1140 | ret = -EINVAL; | |
1141 | goto out_mask; | |
b5faba21 | 1142 | } |
b5faba21 | 1143 | |
1da177e4 | 1144 | if (!shared) { |
c1bacbae TG |
1145 | ret = irq_request_resources(desc); |
1146 | if (ret) { | |
1147 | pr_err("Failed to request resources for %s (irq %d) on irqchip %s\n", | |
1148 | new->name, irq, desc->irq_data.chip->name); | |
1149 | goto out_mask; | |
1150 | } | |
1151 | ||
3aa551c9 TG |
1152 | init_waitqueue_head(&desc->wait_for_threads); |
1153 | ||
e76de9f8 | 1154 | /* Setup the type (level, edge polarity) if configured: */ |
3cca53b0 | 1155 | if (new->flags & IRQF_TRIGGER_MASK) { |
f2b662da DB |
1156 | ret = __irq_set_trigger(desc, irq, |
1157 | new->flags & IRQF_TRIGGER_MASK); | |
82736f4d | 1158 | |
3aa551c9 | 1159 | if (ret) |
3b8249e7 | 1160 | goto out_mask; |
091738a2 | 1161 | } |
6a6de9ef | 1162 | |
009b4c3b | 1163 | desc->istate &= ~(IRQS_AUTODETECT | IRQS_SPURIOUS_DISABLED | \ |
32f4125e TG |
1164 | IRQS_ONESHOT | IRQS_WAITING); |
1165 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); | |
94d39e1f | 1166 | |
a005677b TG |
1167 | if (new->flags & IRQF_PERCPU) { |
1168 | irqd_set(&desc->irq_data, IRQD_PER_CPU); | |
1169 | irq_settings_set_per_cpu(desc); | |
1170 | } | |
6a58fb3b | 1171 | |
b25c340c | 1172 | if (new->flags & IRQF_ONESHOT) |
3d67baec | 1173 | desc->istate |= IRQS_ONESHOT; |
b25c340c | 1174 | |
1ccb4e61 | 1175 | if (irq_settings_can_autoenable(desc)) |
b4bc724e | 1176 | irq_startup(desc, true); |
46999238 | 1177 | else |
e76de9f8 TG |
1178 | /* Undo nested disables: */ |
1179 | desc->depth = 1; | |
18404756 | 1180 | |
612e3684 | 1181 | /* Exclude IRQ from balancing if requested */ |
a005677b TG |
1182 | if (new->flags & IRQF_NOBALANCING) { |
1183 | irq_settings_set_no_balancing(desc); | |
1184 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | |
1185 | } | |
612e3684 | 1186 | |
18404756 | 1187 | /* Set default affinity mask once everything is setup */ |
3b8249e7 | 1188 | setup_affinity(irq, desc, mask); |
0c5d1eb7 | 1189 | |
876dbd4c TG |
1190 | } else if (new->flags & IRQF_TRIGGER_MASK) { |
1191 | unsigned int nmsk = new->flags & IRQF_TRIGGER_MASK; | |
1192 | unsigned int omsk = irq_settings_get_trigger_mask(desc); | |
1193 | ||
1194 | if (nmsk != omsk) | |
1195 | /* hope the handler works with current trigger mode */ | |
97fd75b7 | 1196 | pr_warning("irq %d uses trigger mode %u; requested %u\n", |
876dbd4c | 1197 | irq, nmsk, omsk); |
1da177e4 | 1198 | } |
82736f4d | 1199 | |
69ab8494 | 1200 | new->irq = irq; |
f17c7545 | 1201 | *old_ptr = new; |
82736f4d | 1202 | |
8528b0f1 LT |
1203 | /* Reset broken irq detection when installing new handler */ |
1204 | desc->irq_count = 0; | |
1205 | desc->irqs_unhandled = 0; | |
1adb0850 TG |
1206 | |
1207 | /* | |
1208 | * Check whether we disabled the irq via the spurious handler | |
1209 | * before. Reenable it and give it another chance. | |
1210 | */ | |
7acdd53e TG |
1211 | if (shared && (desc->istate & IRQS_SPURIOUS_DISABLED)) { |
1212 | desc->istate &= ~IRQS_SPURIOUS_DISABLED; | |
8df2e02c | 1213 | __enable_irq(desc, irq); |
1adb0850 TG |
1214 | } |
1215 | ||
239007b8 | 1216 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 | 1217 | |
69ab8494 TG |
1218 | /* |
1219 | * Strictly no need to wake it up, but hung_task complains | |
1220 | * when no hard interrupt wakes the thread up. | |
1221 | */ | |
1222 | if (new->thread) | |
1223 | wake_up_process(new->thread); | |
1224 | ||
2c6927a3 | 1225 | register_irq_proc(irq, desc); |
1da177e4 LT |
1226 | new->dir = NULL; |
1227 | register_handler_proc(irq, new); | |
4f5058c3 | 1228 | free_cpumask_var(mask); |
1da177e4 LT |
1229 | |
1230 | return 0; | |
f5163427 DS |
1231 | |
1232 | mismatch: | |
3cca53b0 | 1233 | if (!(new->flags & IRQF_PROBE_SHARED)) { |
97fd75b7 | 1234 | pr_err("Flags mismatch irq %d. %08x (%s) vs. %08x (%s)\n", |
f5d89470 TG |
1235 | irq, new->flags, new->name, old->flags, old->name); |
1236 | #ifdef CONFIG_DEBUG_SHIRQ | |
13e87ec6 | 1237 | dump_stack(); |
3f050447 | 1238 | #endif |
f5d89470 | 1239 | } |
3aa551c9 TG |
1240 | ret = -EBUSY; |
1241 | ||
3b8249e7 | 1242 | out_mask: |
1c389795 | 1243 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3b8249e7 TG |
1244 | free_cpumask_var(mask); |
1245 | ||
3aa551c9 | 1246 | out_thread: |
3aa551c9 TG |
1247 | if (new->thread) { |
1248 | struct task_struct *t = new->thread; | |
1249 | ||
1250 | new->thread = NULL; | |
05d74efa | 1251 | kthread_stop(t); |
3aa551c9 TG |
1252 | put_task_struct(t); |
1253 | } | |
b6873807 SAS |
1254 | out_mput: |
1255 | module_put(desc->owner); | |
3aa551c9 | 1256 | return ret; |
1da177e4 LT |
1257 | } |
1258 | ||
d3c60047 TG |
1259 | /** |
1260 | * setup_irq - setup an interrupt | |
1261 | * @irq: Interrupt line to setup | |
1262 | * @act: irqaction for the interrupt | |
1263 | * | |
1264 | * Used to statically setup interrupts in the early boot process. | |
1265 | */ | |
1266 | int setup_irq(unsigned int irq, struct irqaction *act) | |
1267 | { | |
986c011d | 1268 | int retval; |
d3c60047 TG |
1269 | struct irq_desc *desc = irq_to_desc(irq); |
1270 | ||
31d9d9b6 MZ |
1271 | if (WARN_ON(irq_settings_is_per_cpu_devid(desc))) |
1272 | return -EINVAL; | |
986c011d DD |
1273 | chip_bus_lock(desc); |
1274 | retval = __setup_irq(irq, desc, act); | |
1275 | chip_bus_sync_unlock(desc); | |
1276 | ||
1277 | return retval; | |
d3c60047 | 1278 | } |
eb53b4e8 | 1279 | EXPORT_SYMBOL_GPL(setup_irq); |
d3c60047 | 1280 | |
31d9d9b6 | 1281 | /* |
cbf94f06 MD |
1282 | * Internal function to unregister an irqaction - used to free |
1283 | * regular and special interrupts that are part of the architecture. | |
1da177e4 | 1284 | */ |
cbf94f06 | 1285 | static struct irqaction *__free_irq(unsigned int irq, void *dev_id) |
1da177e4 | 1286 | { |
d3c60047 | 1287 | struct irq_desc *desc = irq_to_desc(irq); |
f17c7545 | 1288 | struct irqaction *action, **action_ptr; |
1da177e4 LT |
1289 | unsigned long flags; |
1290 | ||
ae88a23b | 1291 | WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq); |
7d94f7ca | 1292 | |
7d94f7ca | 1293 | if (!desc) |
f21cfb25 | 1294 | return NULL; |
1da177e4 | 1295 | |
239007b8 | 1296 | raw_spin_lock_irqsave(&desc->lock, flags); |
ae88a23b IM |
1297 | |
1298 | /* | |
1299 | * There can be multiple actions per IRQ descriptor, find the right | |
1300 | * one based on the dev_id: | |
1301 | */ | |
f17c7545 | 1302 | action_ptr = &desc->action; |
1da177e4 | 1303 | for (;;) { |
f17c7545 | 1304 | action = *action_ptr; |
1da177e4 | 1305 | |
ae88a23b IM |
1306 | if (!action) { |
1307 | WARN(1, "Trying to free already-free IRQ %d\n", irq); | |
239007b8 | 1308 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 | 1309 | |
f21cfb25 | 1310 | return NULL; |
ae88a23b | 1311 | } |
1da177e4 | 1312 | |
8316e381 IM |
1313 | if (action->dev_id == dev_id) |
1314 | break; | |
f17c7545 | 1315 | action_ptr = &action->next; |
ae88a23b | 1316 | } |
dbce706e | 1317 | |
ae88a23b | 1318 | /* Found it - now remove it from the list of entries: */ |
f17c7545 | 1319 | *action_ptr = action->next; |
ae88a23b | 1320 | |
ae88a23b | 1321 | /* If this was the last handler, shut down the IRQ line: */ |
c1bacbae | 1322 | if (!desc->action) { |
46999238 | 1323 | irq_shutdown(desc); |
c1bacbae TG |
1324 | irq_release_resources(desc); |
1325 | } | |
3aa551c9 | 1326 | |
e7a297b0 PWJ |
1327 | #ifdef CONFIG_SMP |
1328 | /* make sure affinity_hint is cleaned up */ | |
1329 | if (WARN_ON_ONCE(desc->affinity_hint)) | |
1330 | desc->affinity_hint = NULL; | |
1331 | #endif | |
1332 | ||
239007b8 | 1333 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
ae88a23b IM |
1334 | |
1335 | unregister_handler_proc(irq, action); | |
1336 | ||
1337 | /* Make sure it's not being used on another CPU: */ | |
1338 | synchronize_irq(irq); | |
1da177e4 | 1339 | |
70edcd77 | 1340 | #ifdef CONFIG_DEBUG_SHIRQ |
ae88a23b IM |
1341 | /* |
1342 | * It's a shared IRQ -- the driver ought to be prepared for an IRQ | |
1343 | * event to happen even now it's being freed, so let's make sure that | |
1344 | * is so by doing an extra call to the handler .... | |
1345 | * | |
1346 | * ( We do this after actually deregistering it, to make sure that a | |
1347 | * 'real' IRQ doesn't run in * parallel with our fake. ) | |
1348 | */ | |
1349 | if (action->flags & IRQF_SHARED) { | |
1350 | local_irq_save(flags); | |
1351 | action->handler(irq, dev_id); | |
1352 | local_irq_restore(flags); | |
1da177e4 | 1353 | } |
ae88a23b | 1354 | #endif |
2d860ad7 LT |
1355 | |
1356 | if (action->thread) { | |
05d74efa | 1357 | kthread_stop(action->thread); |
2d860ad7 LT |
1358 | put_task_struct(action->thread); |
1359 | } | |
1360 | ||
b6873807 | 1361 | module_put(desc->owner); |
f21cfb25 MD |
1362 | return action; |
1363 | } | |
1364 | ||
cbf94f06 MD |
1365 | /** |
1366 | * remove_irq - free an interrupt | |
1367 | * @irq: Interrupt line to free | |
1368 | * @act: irqaction for the interrupt | |
1369 | * | |
1370 | * Used to remove interrupts statically setup by the early boot process. | |
1371 | */ | |
1372 | void remove_irq(unsigned int irq, struct irqaction *act) | |
1373 | { | |
31d9d9b6 MZ |
1374 | struct irq_desc *desc = irq_to_desc(irq); |
1375 | ||
1376 | if (desc && !WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
1377 | __free_irq(irq, act->dev_id); | |
cbf94f06 | 1378 | } |
eb53b4e8 | 1379 | EXPORT_SYMBOL_GPL(remove_irq); |
cbf94f06 | 1380 | |
f21cfb25 MD |
1381 | /** |
1382 | * free_irq - free an interrupt allocated with request_irq | |
1383 | * @irq: Interrupt line to free | |
1384 | * @dev_id: Device identity to free | |
1385 | * | |
1386 | * Remove an interrupt handler. The handler is removed and if the | |
1387 | * interrupt line is no longer in use by any driver it is disabled. | |
1388 | * On a shared IRQ the caller must ensure the interrupt is disabled | |
1389 | * on the card it drives before calling this function. The function | |
1390 | * does not return until any executing interrupts for this IRQ | |
1391 | * have completed. | |
1392 | * | |
1393 | * This function must not be called from interrupt context. | |
1394 | */ | |
1395 | void free_irq(unsigned int irq, void *dev_id) | |
1396 | { | |
70aedd24 TG |
1397 | struct irq_desc *desc = irq_to_desc(irq); |
1398 | ||
31d9d9b6 | 1399 | if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) |
70aedd24 TG |
1400 | return; |
1401 | ||
cd7eab44 BH |
1402 | #ifdef CONFIG_SMP |
1403 | if (WARN_ON(desc->affinity_notify)) | |
1404 | desc->affinity_notify = NULL; | |
1405 | #endif | |
1406 | ||
3876ec9e | 1407 | chip_bus_lock(desc); |
cbf94f06 | 1408 | kfree(__free_irq(irq, dev_id)); |
3876ec9e | 1409 | chip_bus_sync_unlock(desc); |
1da177e4 | 1410 | } |
1da177e4 LT |
1411 | EXPORT_SYMBOL(free_irq); |
1412 | ||
1413 | /** | |
3aa551c9 | 1414 | * request_threaded_irq - allocate an interrupt line |
1da177e4 | 1415 | * @irq: Interrupt line to allocate |
3aa551c9 TG |
1416 | * @handler: Function to be called when the IRQ occurs. |
1417 | * Primary handler for threaded interrupts | |
b25c340c TG |
1418 | * If NULL and thread_fn != NULL the default |
1419 | * primary handler is installed | |
f48fe81e TG |
1420 | * @thread_fn: Function called from the irq handler thread |
1421 | * If NULL, no irq thread is created | |
1da177e4 LT |
1422 | * @irqflags: Interrupt type flags |
1423 | * @devname: An ascii name for the claiming device | |
1424 | * @dev_id: A cookie passed back to the handler function | |
1425 | * | |
1426 | * This call allocates interrupt resources and enables the | |
1427 | * interrupt line and IRQ handling. From the point this | |
1428 | * call is made your handler function may be invoked. Since | |
1429 | * your handler function must clear any interrupt the board | |
1430 | * raises, you must take care both to initialise your hardware | |
1431 | * and to set up the interrupt handler in the right order. | |
1432 | * | |
3aa551c9 | 1433 | * If you want to set up a threaded irq handler for your device |
6d21af4f | 1434 | * then you need to supply @handler and @thread_fn. @handler is |
3aa551c9 TG |
1435 | * still called in hard interrupt context and has to check |
1436 | * whether the interrupt originates from the device. If yes it | |
1437 | * needs to disable the interrupt on the device and return | |
39a2eddb | 1438 | * IRQ_WAKE_THREAD which will wake up the handler thread and run |
3aa551c9 TG |
1439 | * @thread_fn. This split handler design is necessary to support |
1440 | * shared interrupts. | |
1441 | * | |
1da177e4 LT |
1442 | * Dev_id must be globally unique. Normally the address of the |
1443 | * device data structure is used as the cookie. Since the handler | |
1444 | * receives this value it makes sense to use it. | |
1445 | * | |
1446 | * If your interrupt is shared you must pass a non NULL dev_id | |
1447 | * as this is required when freeing the interrupt. | |
1448 | * | |
1449 | * Flags: | |
1450 | * | |
3cca53b0 | 1451 | * IRQF_SHARED Interrupt is shared |
0c5d1eb7 | 1452 | * IRQF_TRIGGER_* Specify active edge(s) or level |
1da177e4 LT |
1453 | * |
1454 | */ | |
3aa551c9 TG |
1455 | int request_threaded_irq(unsigned int irq, irq_handler_t handler, |
1456 | irq_handler_t thread_fn, unsigned long irqflags, | |
1457 | const char *devname, void *dev_id) | |
1da177e4 | 1458 | { |
06fcb0c6 | 1459 | struct irqaction *action; |
08678b08 | 1460 | struct irq_desc *desc; |
d3c60047 | 1461 | int retval; |
1da177e4 LT |
1462 | |
1463 | /* | |
1464 | * Sanity-check: shared interrupts must pass in a real dev-ID, | |
1465 | * otherwise we'll have trouble later trying to figure out | |
1466 | * which interrupt is which (messes up the interrupt freeing | |
1467 | * logic etc). | |
1468 | */ | |
3cca53b0 | 1469 | if ((irqflags & IRQF_SHARED) && !dev_id) |
1da177e4 | 1470 | return -EINVAL; |
7d94f7ca | 1471 | |
cb5bc832 | 1472 | desc = irq_to_desc(irq); |
7d94f7ca | 1473 | if (!desc) |
1da177e4 | 1474 | return -EINVAL; |
7d94f7ca | 1475 | |
31d9d9b6 MZ |
1476 | if (!irq_settings_can_request(desc) || |
1477 | WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
6550c775 | 1478 | return -EINVAL; |
b25c340c TG |
1479 | |
1480 | if (!handler) { | |
1481 | if (!thread_fn) | |
1482 | return -EINVAL; | |
1483 | handler = irq_default_primary_handler; | |
1484 | } | |
1da177e4 | 1485 | |
45535732 | 1486 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); |
1da177e4 LT |
1487 | if (!action) |
1488 | return -ENOMEM; | |
1489 | ||
1490 | action->handler = handler; | |
3aa551c9 | 1491 | action->thread_fn = thread_fn; |
1da177e4 | 1492 | action->flags = irqflags; |
1da177e4 | 1493 | action->name = devname; |
1da177e4 LT |
1494 | action->dev_id = dev_id; |
1495 | ||
3876ec9e | 1496 | chip_bus_lock(desc); |
d3c60047 | 1497 | retval = __setup_irq(irq, desc, action); |
3876ec9e | 1498 | chip_bus_sync_unlock(desc); |
70aedd24 | 1499 | |
377bf1e4 AV |
1500 | if (retval) |
1501 | kfree(action); | |
1502 | ||
6d83f94d | 1503 | #ifdef CONFIG_DEBUG_SHIRQ_FIXME |
6ce51c43 | 1504 | if (!retval && (irqflags & IRQF_SHARED)) { |
a304e1b8 DW |
1505 | /* |
1506 | * It's a shared IRQ -- the driver ought to be prepared for it | |
1507 | * to happen immediately, so let's make sure.... | |
377bf1e4 AV |
1508 | * We disable the irq to make sure that a 'real' IRQ doesn't |
1509 | * run in parallel with our fake. | |
a304e1b8 | 1510 | */ |
59845b1f | 1511 | unsigned long flags; |
a304e1b8 | 1512 | |
377bf1e4 | 1513 | disable_irq(irq); |
59845b1f | 1514 | local_irq_save(flags); |
377bf1e4 | 1515 | |
59845b1f | 1516 | handler(irq, dev_id); |
377bf1e4 | 1517 | |
59845b1f | 1518 | local_irq_restore(flags); |
377bf1e4 | 1519 | enable_irq(irq); |
a304e1b8 DW |
1520 | } |
1521 | #endif | |
1da177e4 LT |
1522 | return retval; |
1523 | } | |
3aa551c9 | 1524 | EXPORT_SYMBOL(request_threaded_irq); |
ae731f8d MZ |
1525 | |
1526 | /** | |
1527 | * request_any_context_irq - allocate an interrupt line | |
1528 | * @irq: Interrupt line to allocate | |
1529 | * @handler: Function to be called when the IRQ occurs. | |
1530 | * Threaded handler for threaded interrupts. | |
1531 | * @flags: Interrupt type flags | |
1532 | * @name: An ascii name for the claiming device | |
1533 | * @dev_id: A cookie passed back to the handler function | |
1534 | * | |
1535 | * This call allocates interrupt resources and enables the | |
1536 | * interrupt line and IRQ handling. It selects either a | |
1537 | * hardirq or threaded handling method depending on the | |
1538 | * context. | |
1539 | * | |
1540 | * On failure, it returns a negative value. On success, | |
1541 | * it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED. | |
1542 | */ | |
1543 | int request_any_context_irq(unsigned int irq, irq_handler_t handler, | |
1544 | unsigned long flags, const char *name, void *dev_id) | |
1545 | { | |
1546 | struct irq_desc *desc = irq_to_desc(irq); | |
1547 | int ret; | |
1548 | ||
1549 | if (!desc) | |
1550 | return -EINVAL; | |
1551 | ||
1ccb4e61 | 1552 | if (irq_settings_is_nested_thread(desc)) { |
ae731f8d MZ |
1553 | ret = request_threaded_irq(irq, NULL, handler, |
1554 | flags, name, dev_id); | |
1555 | return !ret ? IRQC_IS_NESTED : ret; | |
1556 | } | |
1557 | ||
1558 | ret = request_irq(irq, handler, flags, name, dev_id); | |
1559 | return !ret ? IRQC_IS_HARDIRQ : ret; | |
1560 | } | |
1561 | EXPORT_SYMBOL_GPL(request_any_context_irq); | |
31d9d9b6 | 1562 | |
1e7c5fd2 | 1563 | void enable_percpu_irq(unsigned int irq, unsigned int type) |
31d9d9b6 MZ |
1564 | { |
1565 | unsigned int cpu = smp_processor_id(); | |
1566 | unsigned long flags; | |
1567 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
1568 | ||
1569 | if (!desc) | |
1570 | return; | |
1571 | ||
1e7c5fd2 MZ |
1572 | type &= IRQ_TYPE_SENSE_MASK; |
1573 | if (type != IRQ_TYPE_NONE) { | |
1574 | int ret; | |
1575 | ||
1576 | ret = __irq_set_trigger(desc, irq, type); | |
1577 | ||
1578 | if (ret) { | |
32cffdde | 1579 | WARN(1, "failed to set type for IRQ%d\n", irq); |
1e7c5fd2 MZ |
1580 | goto out; |
1581 | } | |
1582 | } | |
1583 | ||
31d9d9b6 | 1584 | irq_percpu_enable(desc, cpu); |
1e7c5fd2 | 1585 | out: |
31d9d9b6 MZ |
1586 | irq_put_desc_unlock(desc, flags); |
1587 | } | |
36a5df85 | 1588 | EXPORT_SYMBOL_GPL(enable_percpu_irq); |
31d9d9b6 MZ |
1589 | |
1590 | void disable_percpu_irq(unsigned int irq) | |
1591 | { | |
1592 | unsigned int cpu = smp_processor_id(); | |
1593 | unsigned long flags; | |
1594 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
1595 | ||
1596 | if (!desc) | |
1597 | return; | |
1598 | ||
1599 | irq_percpu_disable(desc, cpu); | |
1600 | irq_put_desc_unlock(desc, flags); | |
1601 | } | |
36a5df85 | 1602 | EXPORT_SYMBOL_GPL(disable_percpu_irq); |
31d9d9b6 MZ |
1603 | |
1604 | /* | |
1605 | * Internal function to unregister a percpu irqaction. | |
1606 | */ | |
1607 | static struct irqaction *__free_percpu_irq(unsigned int irq, void __percpu *dev_id) | |
1608 | { | |
1609 | struct irq_desc *desc = irq_to_desc(irq); | |
1610 | struct irqaction *action; | |
1611 | unsigned long flags; | |
1612 | ||
1613 | WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq); | |
1614 | ||
1615 | if (!desc) | |
1616 | return NULL; | |
1617 | ||
1618 | raw_spin_lock_irqsave(&desc->lock, flags); | |
1619 | ||
1620 | action = desc->action; | |
1621 | if (!action || action->percpu_dev_id != dev_id) { | |
1622 | WARN(1, "Trying to free already-free IRQ %d\n", irq); | |
1623 | goto bad; | |
1624 | } | |
1625 | ||
1626 | if (!cpumask_empty(desc->percpu_enabled)) { | |
1627 | WARN(1, "percpu IRQ %d still enabled on CPU%d!\n", | |
1628 | irq, cpumask_first(desc->percpu_enabled)); | |
1629 | goto bad; | |
1630 | } | |
1631 | ||
1632 | /* Found it - now remove it from the list of entries: */ | |
1633 | desc->action = NULL; | |
1634 | ||
1635 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1636 | ||
1637 | unregister_handler_proc(irq, action); | |
1638 | ||
1639 | module_put(desc->owner); | |
1640 | return action; | |
1641 | ||
1642 | bad: | |
1643 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1644 | return NULL; | |
1645 | } | |
1646 | ||
1647 | /** | |
1648 | * remove_percpu_irq - free a per-cpu interrupt | |
1649 | * @irq: Interrupt line to free | |
1650 | * @act: irqaction for the interrupt | |
1651 | * | |
1652 | * Used to remove interrupts statically setup by the early boot process. | |
1653 | */ | |
1654 | void remove_percpu_irq(unsigned int irq, struct irqaction *act) | |
1655 | { | |
1656 | struct irq_desc *desc = irq_to_desc(irq); | |
1657 | ||
1658 | if (desc && irq_settings_is_per_cpu_devid(desc)) | |
1659 | __free_percpu_irq(irq, act->percpu_dev_id); | |
1660 | } | |
1661 | ||
1662 | /** | |
1663 | * free_percpu_irq - free an interrupt allocated with request_percpu_irq | |
1664 | * @irq: Interrupt line to free | |
1665 | * @dev_id: Device identity to free | |
1666 | * | |
1667 | * Remove a percpu interrupt handler. The handler is removed, but | |
1668 | * the interrupt line is not disabled. This must be done on each | |
1669 | * CPU before calling this function. The function does not return | |
1670 | * until any executing interrupts for this IRQ have completed. | |
1671 | * | |
1672 | * This function must not be called from interrupt context. | |
1673 | */ | |
1674 | void free_percpu_irq(unsigned int irq, void __percpu *dev_id) | |
1675 | { | |
1676 | struct irq_desc *desc = irq_to_desc(irq); | |
1677 | ||
1678 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
1679 | return; | |
1680 | ||
1681 | chip_bus_lock(desc); | |
1682 | kfree(__free_percpu_irq(irq, dev_id)); | |
1683 | chip_bus_sync_unlock(desc); | |
1684 | } | |
1685 | ||
1686 | /** | |
1687 | * setup_percpu_irq - setup a per-cpu interrupt | |
1688 | * @irq: Interrupt line to setup | |
1689 | * @act: irqaction for the interrupt | |
1690 | * | |
1691 | * Used to statically setup per-cpu interrupts in the early boot process. | |
1692 | */ | |
1693 | int setup_percpu_irq(unsigned int irq, struct irqaction *act) | |
1694 | { | |
1695 | struct irq_desc *desc = irq_to_desc(irq); | |
1696 | int retval; | |
1697 | ||
1698 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
1699 | return -EINVAL; | |
1700 | chip_bus_lock(desc); | |
1701 | retval = __setup_irq(irq, desc, act); | |
1702 | chip_bus_sync_unlock(desc); | |
1703 | ||
1704 | return retval; | |
1705 | } | |
1706 | ||
1707 | /** | |
1708 | * request_percpu_irq - allocate a percpu interrupt line | |
1709 | * @irq: Interrupt line to allocate | |
1710 | * @handler: Function to be called when the IRQ occurs. | |
1711 | * @devname: An ascii name for the claiming device | |
1712 | * @dev_id: A percpu cookie passed back to the handler function | |
1713 | * | |
1714 | * This call allocates interrupt resources, but doesn't | |
1715 | * automatically enable the interrupt. It has to be done on each | |
1716 | * CPU using enable_percpu_irq(). | |
1717 | * | |
1718 | * Dev_id must be globally unique. It is a per-cpu variable, and | |
1719 | * the handler gets called with the interrupted CPU's instance of | |
1720 | * that variable. | |
1721 | */ | |
1722 | int request_percpu_irq(unsigned int irq, irq_handler_t handler, | |
1723 | const char *devname, void __percpu *dev_id) | |
1724 | { | |
1725 | struct irqaction *action; | |
1726 | struct irq_desc *desc; | |
1727 | int retval; | |
1728 | ||
1729 | if (!dev_id) | |
1730 | return -EINVAL; | |
1731 | ||
1732 | desc = irq_to_desc(irq); | |
1733 | if (!desc || !irq_settings_can_request(desc) || | |
1734 | !irq_settings_is_per_cpu_devid(desc)) | |
1735 | return -EINVAL; | |
1736 | ||
1737 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); | |
1738 | if (!action) | |
1739 | return -ENOMEM; | |
1740 | ||
1741 | action->handler = handler; | |
2ed0e645 | 1742 | action->flags = IRQF_PERCPU | IRQF_NO_SUSPEND; |
31d9d9b6 MZ |
1743 | action->name = devname; |
1744 | action->percpu_dev_id = dev_id; | |
1745 | ||
1746 | chip_bus_lock(desc); | |
1747 | retval = __setup_irq(irq, desc, action); | |
1748 | chip_bus_sync_unlock(desc); | |
1749 | ||
1750 | if (retval) | |
1751 | kfree(action); | |
1752 | ||
1753 | return retval; | |
1754 | } |