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1da177e4 LT |
1 | /* |
2 | * linux/kernel/irq/manage.c | |
3 | * | |
a34db9b2 IM |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
5 | * Copyright (C) 2005-2006 Thomas Gleixner | |
1da177e4 LT |
6 | * |
7 | * This file contains driver APIs to the irq subsystem. | |
8 | */ | |
9 | ||
97fd75b7 AM |
10 | #define pr_fmt(fmt) "genirq: " fmt |
11 | ||
1da177e4 | 12 | #include <linux/irq.h> |
3aa551c9 | 13 | #include <linux/kthread.h> |
1da177e4 LT |
14 | #include <linux/module.h> |
15 | #include <linux/random.h> | |
16 | #include <linux/interrupt.h> | |
1aeb272c | 17 | #include <linux/slab.h> |
3aa551c9 | 18 | #include <linux/sched.h> |
8bd75c77 | 19 | #include <linux/sched/rt.h> |
0881e7bd | 20 | #include <linux/sched/task.h> |
ae7e81c0 | 21 | #include <uapi/linux/sched/types.h> |
4d1d61a6 | 22 | #include <linux/task_work.h> |
1da177e4 LT |
23 | |
24 | #include "internals.h" | |
25 | ||
8d32a307 TG |
26 | #ifdef CONFIG_IRQ_FORCED_THREADING |
27 | __read_mostly bool force_irqthreads; | |
28 | ||
29 | static int __init setup_forced_irqthreads(char *arg) | |
30 | { | |
31 | force_irqthreads = true; | |
32 | return 0; | |
33 | } | |
34 | early_param("threadirqs", setup_forced_irqthreads); | |
35 | #endif | |
36 | ||
18258f72 | 37 | static void __synchronize_hardirq(struct irq_desc *desc) |
1da177e4 | 38 | { |
32f4125e | 39 | bool inprogress; |
1da177e4 | 40 | |
a98ce5c6 HX |
41 | do { |
42 | unsigned long flags; | |
43 | ||
44 | /* | |
45 | * Wait until we're out of the critical section. This might | |
46 | * give the wrong answer due to the lack of memory barriers. | |
47 | */ | |
32f4125e | 48 | while (irqd_irq_inprogress(&desc->irq_data)) |
a98ce5c6 HX |
49 | cpu_relax(); |
50 | ||
51 | /* Ok, that indicated we're done: double-check carefully. */ | |
239007b8 | 52 | raw_spin_lock_irqsave(&desc->lock, flags); |
32f4125e | 53 | inprogress = irqd_irq_inprogress(&desc->irq_data); |
239007b8 | 54 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
a98ce5c6 HX |
55 | |
56 | /* Oops, that failed? */ | |
32f4125e | 57 | } while (inprogress); |
18258f72 TG |
58 | } |
59 | ||
60 | /** | |
61 | * synchronize_hardirq - wait for pending hard IRQ handlers (on other CPUs) | |
62 | * @irq: interrupt number to wait for | |
63 | * | |
64 | * This function waits for any pending hard IRQ handlers for this | |
65 | * interrupt to complete before returning. If you use this | |
66 | * function while holding a resource the IRQ handler may need you | |
67 | * will deadlock. It does not take associated threaded handlers | |
68 | * into account. | |
69 | * | |
70 | * Do not use this for shutdown scenarios where you must be sure | |
71 | * that all parts (hardirq and threaded handler) have completed. | |
72 | * | |
02cea395 PZ |
73 | * Returns: false if a threaded handler is active. |
74 | * | |
18258f72 TG |
75 | * This function may be called - with care - from IRQ context. |
76 | */ | |
02cea395 | 77 | bool synchronize_hardirq(unsigned int irq) |
18258f72 TG |
78 | { |
79 | struct irq_desc *desc = irq_to_desc(irq); | |
3aa551c9 | 80 | |
02cea395 | 81 | if (desc) { |
18258f72 | 82 | __synchronize_hardirq(desc); |
02cea395 PZ |
83 | return !atomic_read(&desc->threads_active); |
84 | } | |
85 | ||
86 | return true; | |
18258f72 TG |
87 | } |
88 | EXPORT_SYMBOL(synchronize_hardirq); | |
89 | ||
90 | /** | |
91 | * synchronize_irq - wait for pending IRQ handlers (on other CPUs) | |
92 | * @irq: interrupt number to wait for | |
93 | * | |
94 | * This function waits for any pending IRQ handlers for this interrupt | |
95 | * to complete before returning. If you use this function while | |
96 | * holding a resource the IRQ handler may need you will deadlock. | |
97 | * | |
98 | * This function may be called - with care - from IRQ context. | |
99 | */ | |
100 | void synchronize_irq(unsigned int irq) | |
101 | { | |
102 | struct irq_desc *desc = irq_to_desc(irq); | |
103 | ||
104 | if (desc) { | |
105 | __synchronize_hardirq(desc); | |
106 | /* | |
107 | * We made sure that no hardirq handler is | |
108 | * running. Now verify that no threaded handlers are | |
109 | * active. | |
110 | */ | |
111 | wait_event(desc->wait_for_threads, | |
112 | !atomic_read(&desc->threads_active)); | |
113 | } | |
1da177e4 | 114 | } |
1da177e4 LT |
115 | EXPORT_SYMBOL(synchronize_irq); |
116 | ||
3aa551c9 TG |
117 | #ifdef CONFIG_SMP |
118 | cpumask_var_t irq_default_affinity; | |
119 | ||
9c255583 | 120 | static bool __irq_can_set_affinity(struct irq_desc *desc) |
e019c249 JL |
121 | { |
122 | if (!desc || !irqd_can_balance(&desc->irq_data) || | |
123 | !desc->irq_data.chip || !desc->irq_data.chip->irq_set_affinity) | |
9c255583 TG |
124 | return false; |
125 | return true; | |
e019c249 JL |
126 | } |
127 | ||
771ee3b0 TG |
128 | /** |
129 | * irq_can_set_affinity - Check if the affinity of a given irq can be set | |
130 | * @irq: Interrupt to check | |
131 | * | |
132 | */ | |
133 | int irq_can_set_affinity(unsigned int irq) | |
134 | { | |
e019c249 | 135 | return __irq_can_set_affinity(irq_to_desc(irq)); |
771ee3b0 TG |
136 | } |
137 | ||
9c255583 TG |
138 | /** |
139 | * irq_can_set_affinity_usr - Check if affinity of a irq can be set from user space | |
140 | * @irq: Interrupt to check | |
141 | * | |
142 | * Like irq_can_set_affinity() above, but additionally checks for the | |
143 | * AFFINITY_MANAGED flag. | |
144 | */ | |
145 | bool irq_can_set_affinity_usr(unsigned int irq) | |
146 | { | |
147 | struct irq_desc *desc = irq_to_desc(irq); | |
148 | ||
149 | return __irq_can_set_affinity(desc) && | |
150 | !irqd_affinity_is_managed(&desc->irq_data); | |
151 | } | |
152 | ||
591d2fb0 TG |
153 | /** |
154 | * irq_set_thread_affinity - Notify irq threads to adjust affinity | |
155 | * @desc: irq descriptor which has affitnity changed | |
156 | * | |
157 | * We just set IRQTF_AFFINITY and delegate the affinity setting | |
158 | * to the interrupt thread itself. We can not call | |
159 | * set_cpus_allowed_ptr() here as we hold desc->lock and this | |
160 | * code can be called from hard interrupt context. | |
161 | */ | |
162 | void irq_set_thread_affinity(struct irq_desc *desc) | |
3aa551c9 | 163 | { |
f944b5a7 | 164 | struct irqaction *action; |
3aa551c9 | 165 | |
f944b5a7 | 166 | for_each_action_of_desc(desc, action) |
3aa551c9 | 167 | if (action->thread) |
591d2fb0 | 168 | set_bit(IRQTF_AFFINITY, &action->thread_flags); |
3aa551c9 TG |
169 | } |
170 | ||
1fa46f1f | 171 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
0ef5ca1e | 172 | static inline bool irq_can_move_pcntxt(struct irq_data *data) |
1fa46f1f | 173 | { |
0ef5ca1e | 174 | return irqd_can_move_in_process_context(data); |
1fa46f1f | 175 | } |
0ef5ca1e | 176 | static inline bool irq_move_pending(struct irq_data *data) |
1fa46f1f | 177 | { |
0ef5ca1e | 178 | return irqd_is_setaffinity_pending(data); |
1fa46f1f TG |
179 | } |
180 | static inline void | |
181 | irq_copy_pending(struct irq_desc *desc, const struct cpumask *mask) | |
182 | { | |
183 | cpumask_copy(desc->pending_mask, mask); | |
184 | } | |
185 | static inline void | |
186 | irq_get_pending(struct cpumask *mask, struct irq_desc *desc) | |
187 | { | |
188 | cpumask_copy(mask, desc->pending_mask); | |
189 | } | |
190 | #else | |
0ef5ca1e | 191 | static inline bool irq_can_move_pcntxt(struct irq_data *data) { return true; } |
cd22c0e4 | 192 | static inline bool irq_move_pending(struct irq_data *data) { return false; } |
1fa46f1f TG |
193 | static inline void |
194 | irq_copy_pending(struct irq_desc *desc, const struct cpumask *mask) { } | |
195 | static inline void | |
196 | irq_get_pending(struct cpumask *mask, struct irq_desc *desc) { } | |
197 | #endif | |
198 | ||
818b0f3b JL |
199 | int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask, |
200 | bool force) | |
201 | { | |
202 | struct irq_desc *desc = irq_data_to_desc(data); | |
203 | struct irq_chip *chip = irq_data_get_irq_chip(data); | |
204 | int ret; | |
205 | ||
01f8fa4f | 206 | ret = chip->irq_set_affinity(data, mask, force); |
818b0f3b JL |
207 | switch (ret) { |
208 | case IRQ_SET_MASK_OK: | |
2cb62547 | 209 | case IRQ_SET_MASK_OK_DONE: |
9df872fa | 210 | cpumask_copy(desc->irq_common_data.affinity, mask); |
818b0f3b JL |
211 | case IRQ_SET_MASK_OK_NOCOPY: |
212 | irq_set_thread_affinity(desc); | |
213 | ret = 0; | |
214 | } | |
215 | ||
216 | return ret; | |
217 | } | |
218 | ||
01f8fa4f TG |
219 | int irq_set_affinity_locked(struct irq_data *data, const struct cpumask *mask, |
220 | bool force) | |
771ee3b0 | 221 | { |
c2d0c555 DD |
222 | struct irq_chip *chip = irq_data_get_irq_chip(data); |
223 | struct irq_desc *desc = irq_data_to_desc(data); | |
1fa46f1f | 224 | int ret = 0; |
771ee3b0 | 225 | |
c2d0c555 | 226 | if (!chip || !chip->irq_set_affinity) |
771ee3b0 TG |
227 | return -EINVAL; |
228 | ||
0ef5ca1e | 229 | if (irq_can_move_pcntxt(data)) { |
01f8fa4f | 230 | ret = irq_do_set_affinity(data, mask, force); |
1fa46f1f | 231 | } else { |
c2d0c555 | 232 | irqd_set_move_pending(data); |
1fa46f1f | 233 | irq_copy_pending(desc, mask); |
57b150cc | 234 | } |
1fa46f1f | 235 | |
cd7eab44 BH |
236 | if (desc->affinity_notify) { |
237 | kref_get(&desc->affinity_notify->kref); | |
238 | schedule_work(&desc->affinity_notify->work); | |
239 | } | |
c2d0c555 DD |
240 | irqd_set(data, IRQD_AFFINITY_SET); |
241 | ||
242 | return ret; | |
243 | } | |
244 | ||
01f8fa4f | 245 | int __irq_set_affinity(unsigned int irq, const struct cpumask *mask, bool force) |
c2d0c555 DD |
246 | { |
247 | struct irq_desc *desc = irq_to_desc(irq); | |
248 | unsigned long flags; | |
249 | int ret; | |
250 | ||
251 | if (!desc) | |
252 | return -EINVAL; | |
253 | ||
254 | raw_spin_lock_irqsave(&desc->lock, flags); | |
01f8fa4f | 255 | ret = irq_set_affinity_locked(irq_desc_get_irq_data(desc), mask, force); |
239007b8 | 256 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1fa46f1f | 257 | return ret; |
771ee3b0 TG |
258 | } |
259 | ||
e7a297b0 PWJ |
260 | int irq_set_affinity_hint(unsigned int irq, const struct cpumask *m) |
261 | { | |
e7a297b0 | 262 | unsigned long flags; |
31d9d9b6 | 263 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
e7a297b0 PWJ |
264 | |
265 | if (!desc) | |
266 | return -EINVAL; | |
e7a297b0 | 267 | desc->affinity_hint = m; |
02725e74 | 268 | irq_put_desc_unlock(desc, flags); |
e2e64a93 | 269 | /* set the initial affinity to prevent every interrupt being on CPU0 */ |
4fe7ffb7 JB |
270 | if (m) |
271 | __irq_set_affinity(irq, m, false); | |
e7a297b0 PWJ |
272 | return 0; |
273 | } | |
274 | EXPORT_SYMBOL_GPL(irq_set_affinity_hint); | |
275 | ||
cd7eab44 BH |
276 | static void irq_affinity_notify(struct work_struct *work) |
277 | { | |
278 | struct irq_affinity_notify *notify = | |
279 | container_of(work, struct irq_affinity_notify, work); | |
280 | struct irq_desc *desc = irq_to_desc(notify->irq); | |
281 | cpumask_var_t cpumask; | |
282 | unsigned long flags; | |
283 | ||
1fa46f1f | 284 | if (!desc || !alloc_cpumask_var(&cpumask, GFP_KERNEL)) |
cd7eab44 BH |
285 | goto out; |
286 | ||
287 | raw_spin_lock_irqsave(&desc->lock, flags); | |
0ef5ca1e | 288 | if (irq_move_pending(&desc->irq_data)) |
1fa46f1f | 289 | irq_get_pending(cpumask, desc); |
cd7eab44 | 290 | else |
9df872fa | 291 | cpumask_copy(cpumask, desc->irq_common_data.affinity); |
cd7eab44 BH |
292 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
293 | ||
294 | notify->notify(notify, cpumask); | |
295 | ||
296 | free_cpumask_var(cpumask); | |
297 | out: | |
298 | kref_put(¬ify->kref, notify->release); | |
299 | } | |
300 | ||
301 | /** | |
302 | * irq_set_affinity_notifier - control notification of IRQ affinity changes | |
303 | * @irq: Interrupt for which to enable/disable notification | |
304 | * @notify: Context for notification, or %NULL to disable | |
305 | * notification. Function pointers must be initialised; | |
306 | * the other fields will be initialised by this function. | |
307 | * | |
308 | * Must be called in process context. Notification may only be enabled | |
309 | * after the IRQ is allocated and must be disabled before the IRQ is | |
310 | * freed using free_irq(). | |
311 | */ | |
312 | int | |
313 | irq_set_affinity_notifier(unsigned int irq, struct irq_affinity_notify *notify) | |
314 | { | |
315 | struct irq_desc *desc = irq_to_desc(irq); | |
316 | struct irq_affinity_notify *old_notify; | |
317 | unsigned long flags; | |
318 | ||
319 | /* The release function is promised process context */ | |
320 | might_sleep(); | |
321 | ||
322 | if (!desc) | |
323 | return -EINVAL; | |
324 | ||
325 | /* Complete initialisation of *notify */ | |
326 | if (notify) { | |
327 | notify->irq = irq; | |
328 | kref_init(¬ify->kref); | |
329 | INIT_WORK(¬ify->work, irq_affinity_notify); | |
330 | } | |
331 | ||
332 | raw_spin_lock_irqsave(&desc->lock, flags); | |
333 | old_notify = desc->affinity_notify; | |
334 | desc->affinity_notify = notify; | |
335 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
336 | ||
337 | if (old_notify) | |
338 | kref_put(&old_notify->kref, old_notify->release); | |
339 | ||
340 | return 0; | |
341 | } | |
342 | EXPORT_SYMBOL_GPL(irq_set_affinity_notifier); | |
343 | ||
18404756 MK |
344 | #ifndef CONFIG_AUTO_IRQ_AFFINITY |
345 | /* | |
346 | * Generic version of the affinity autoselector. | |
347 | */ | |
a8a98eac | 348 | static int setup_affinity(struct irq_desc *desc, struct cpumask *mask) |
18404756 | 349 | { |
569bda8d | 350 | struct cpumask *set = irq_default_affinity; |
6783011b | 351 | int node = irq_desc_get_node(desc); |
569bda8d | 352 | |
b008207c | 353 | /* Excludes PER_CPU and NO_BALANCE interrupts */ |
e019c249 | 354 | if (!__irq_can_set_affinity(desc)) |
18404756 MK |
355 | return 0; |
356 | ||
f6d87f4b | 357 | /* |
9332ef9d | 358 | * Preserve the managed affinity setting and a userspace affinity |
06ee6d57 | 359 | * setup, but make sure that one of the targets is online. |
f6d87f4b | 360 | */ |
06ee6d57 TG |
361 | if (irqd_affinity_is_managed(&desc->irq_data) || |
362 | irqd_has_set(&desc->irq_data, IRQD_AFFINITY_SET)) { | |
9df872fa | 363 | if (cpumask_intersects(desc->irq_common_data.affinity, |
569bda8d | 364 | cpu_online_mask)) |
9df872fa | 365 | set = desc->irq_common_data.affinity; |
0c6f8a8b | 366 | else |
2bdd1055 | 367 | irqd_clear(&desc->irq_data, IRQD_AFFINITY_SET); |
f6d87f4b | 368 | } |
18404756 | 369 | |
3b8249e7 | 370 | cpumask_and(mask, cpu_online_mask, set); |
241fc640 PB |
371 | if (node != NUMA_NO_NODE) { |
372 | const struct cpumask *nodemask = cpumask_of_node(node); | |
373 | ||
374 | /* make sure at least one of the cpus in nodemask is online */ | |
375 | if (cpumask_intersects(mask, nodemask)) | |
376 | cpumask_and(mask, mask, nodemask); | |
377 | } | |
818b0f3b | 378 | irq_do_set_affinity(&desc->irq_data, mask, false); |
18404756 MK |
379 | return 0; |
380 | } | |
f6d87f4b | 381 | #else |
a8a98eac JL |
382 | /* Wrapper for ALPHA specific affinity selector magic */ |
383 | static inline int setup_affinity(struct irq_desc *d, struct cpumask *mask) | |
f6d87f4b | 384 | { |
a8a98eac | 385 | return irq_select_affinity(irq_desc_get_irq(d)); |
f6d87f4b | 386 | } |
18404756 MK |
387 | #endif |
388 | ||
f6d87f4b TG |
389 | /* |
390 | * Called when affinity is set via /proc/irq | |
391 | */ | |
3b8249e7 | 392 | int irq_select_affinity_usr(unsigned int irq, struct cpumask *mask) |
f6d87f4b TG |
393 | { |
394 | struct irq_desc *desc = irq_to_desc(irq); | |
395 | unsigned long flags; | |
396 | int ret; | |
397 | ||
239007b8 | 398 | raw_spin_lock_irqsave(&desc->lock, flags); |
a8a98eac | 399 | ret = setup_affinity(desc, mask); |
239007b8 | 400 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
f6d87f4b TG |
401 | return ret; |
402 | } | |
403 | ||
404 | #else | |
3b8249e7 | 405 | static inline int |
a8a98eac | 406 | setup_affinity(struct irq_desc *desc, struct cpumask *mask) |
f6d87f4b TG |
407 | { |
408 | return 0; | |
409 | } | |
1da177e4 LT |
410 | #endif |
411 | ||
fcf1ae2f FW |
412 | /** |
413 | * irq_set_vcpu_affinity - Set vcpu affinity for the interrupt | |
414 | * @irq: interrupt number to set affinity | |
415 | * @vcpu_info: vCPU specific data | |
416 | * | |
417 | * This function uses the vCPU specific data to set the vCPU | |
418 | * affinity for an irq. The vCPU specific data is passed from | |
419 | * outside, such as KVM. One example code path is as below: | |
420 | * KVM -> IOMMU -> irq_set_vcpu_affinity(). | |
421 | */ | |
422 | int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info) | |
423 | { | |
424 | unsigned long flags; | |
425 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | |
426 | struct irq_data *data; | |
427 | struct irq_chip *chip; | |
428 | int ret = -ENOSYS; | |
429 | ||
430 | if (!desc) | |
431 | return -EINVAL; | |
432 | ||
433 | data = irq_desc_get_irq_data(desc); | |
434 | chip = irq_data_get_irq_chip(data); | |
435 | if (chip && chip->irq_set_vcpu_affinity) | |
436 | ret = chip->irq_set_vcpu_affinity(data, vcpu_info); | |
437 | irq_put_desc_unlock(desc, flags); | |
438 | ||
439 | return ret; | |
440 | } | |
441 | EXPORT_SYMBOL_GPL(irq_set_vcpu_affinity); | |
442 | ||
79ff1cda | 443 | void __disable_irq(struct irq_desc *desc) |
0a0c5168 | 444 | { |
3aae994f | 445 | if (!desc->depth++) |
87923470 | 446 | irq_disable(desc); |
0a0c5168 RW |
447 | } |
448 | ||
02725e74 TG |
449 | static int __disable_irq_nosync(unsigned int irq) |
450 | { | |
451 | unsigned long flags; | |
31d9d9b6 | 452 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
02725e74 TG |
453 | |
454 | if (!desc) | |
455 | return -EINVAL; | |
79ff1cda | 456 | __disable_irq(desc); |
02725e74 TG |
457 | irq_put_desc_busunlock(desc, flags); |
458 | return 0; | |
459 | } | |
460 | ||
1da177e4 LT |
461 | /** |
462 | * disable_irq_nosync - disable an irq without waiting | |
463 | * @irq: Interrupt to disable | |
464 | * | |
465 | * Disable the selected interrupt line. Disables and Enables are | |
466 | * nested. | |
467 | * Unlike disable_irq(), this function does not ensure existing | |
468 | * instances of the IRQ handler have completed before returning. | |
469 | * | |
470 | * This function may be called from IRQ context. | |
471 | */ | |
472 | void disable_irq_nosync(unsigned int irq) | |
473 | { | |
02725e74 | 474 | __disable_irq_nosync(irq); |
1da177e4 | 475 | } |
1da177e4 LT |
476 | EXPORT_SYMBOL(disable_irq_nosync); |
477 | ||
478 | /** | |
479 | * disable_irq - disable an irq and wait for completion | |
480 | * @irq: Interrupt to disable | |
481 | * | |
482 | * Disable the selected interrupt line. Enables and Disables are | |
483 | * nested. | |
484 | * This function waits for any pending IRQ handlers for this interrupt | |
485 | * to complete before returning. If you use this function while | |
486 | * holding a resource the IRQ handler may need you will deadlock. | |
487 | * | |
488 | * This function may be called - with care - from IRQ context. | |
489 | */ | |
490 | void disable_irq(unsigned int irq) | |
491 | { | |
02725e74 | 492 | if (!__disable_irq_nosync(irq)) |
1da177e4 LT |
493 | synchronize_irq(irq); |
494 | } | |
1da177e4 LT |
495 | EXPORT_SYMBOL(disable_irq); |
496 | ||
02cea395 PZ |
497 | /** |
498 | * disable_hardirq - disables an irq and waits for hardirq completion | |
499 | * @irq: Interrupt to disable | |
500 | * | |
501 | * Disable the selected interrupt line. Enables and Disables are | |
502 | * nested. | |
503 | * This function waits for any pending hard IRQ handlers for this | |
504 | * interrupt to complete before returning. If you use this function while | |
505 | * holding a resource the hard IRQ handler may need you will deadlock. | |
506 | * | |
507 | * When used to optimistically disable an interrupt from atomic context | |
508 | * the return value must be checked. | |
509 | * | |
510 | * Returns: false if a threaded handler is active. | |
511 | * | |
512 | * This function may be called - with care - from IRQ context. | |
513 | */ | |
514 | bool disable_hardirq(unsigned int irq) | |
515 | { | |
516 | if (!__disable_irq_nosync(irq)) | |
517 | return synchronize_hardirq(irq); | |
518 | ||
519 | return false; | |
520 | } | |
521 | EXPORT_SYMBOL_GPL(disable_hardirq); | |
522 | ||
79ff1cda | 523 | void __enable_irq(struct irq_desc *desc) |
1adb0850 TG |
524 | { |
525 | switch (desc->depth) { | |
526 | case 0: | |
0a0c5168 | 527 | err_out: |
79ff1cda JL |
528 | WARN(1, KERN_WARNING "Unbalanced enable for IRQ %d\n", |
529 | irq_desc_get_irq(desc)); | |
1adb0850 TG |
530 | break; |
531 | case 1: { | |
c531e836 | 532 | if (desc->istate & IRQS_SUSPENDED) |
0a0c5168 | 533 | goto err_out; |
1adb0850 | 534 | /* Prevent probing on this irq: */ |
1ccb4e61 | 535 | irq_settings_set_noprobe(desc); |
201d7f47 TG |
536 | /* |
537 | * Call irq_startup() not irq_enable() here because the | |
538 | * interrupt might be marked NOAUTOEN. So irq_startup() | |
539 | * needs to be invoked when it gets enabled the first | |
540 | * time. If it was already started up, then irq_startup() | |
541 | * will invoke irq_enable() under the hood. | |
542 | */ | |
543 | irq_startup(desc, true); | |
544 | break; | |
1adb0850 TG |
545 | } |
546 | default: | |
547 | desc->depth--; | |
548 | } | |
549 | } | |
550 | ||
1da177e4 LT |
551 | /** |
552 | * enable_irq - enable handling of an irq | |
553 | * @irq: Interrupt to enable | |
554 | * | |
555 | * Undoes the effect of one call to disable_irq(). If this | |
556 | * matches the last disable, processing of interrupts on this | |
557 | * IRQ line is re-enabled. | |
558 | * | |
70aedd24 | 559 | * This function may be called from IRQ context only when |
6b8ff312 | 560 | * desc->irq_data.chip->bus_lock and desc->chip->bus_sync_unlock are NULL ! |
1da177e4 LT |
561 | */ |
562 | void enable_irq(unsigned int irq) | |
563 | { | |
1da177e4 | 564 | unsigned long flags; |
31d9d9b6 | 565 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
1da177e4 | 566 | |
7d94f7ca | 567 | if (!desc) |
c2b5a251 | 568 | return; |
50f7c032 TG |
569 | if (WARN(!desc->irq_data.chip, |
570 | KERN_ERR "enable_irq before setup/request_irq: irq %u\n", irq)) | |
02725e74 | 571 | goto out; |
2656c366 | 572 | |
79ff1cda | 573 | __enable_irq(desc); |
02725e74 TG |
574 | out: |
575 | irq_put_desc_busunlock(desc, flags); | |
1da177e4 | 576 | } |
1da177e4 LT |
577 | EXPORT_SYMBOL(enable_irq); |
578 | ||
0c5d1eb7 | 579 | static int set_irq_wake_real(unsigned int irq, unsigned int on) |
2db87321 | 580 | { |
08678b08 | 581 | struct irq_desc *desc = irq_to_desc(irq); |
2db87321 UKK |
582 | int ret = -ENXIO; |
583 | ||
60f96b41 SS |
584 | if (irq_desc_get_chip(desc)->flags & IRQCHIP_SKIP_SET_WAKE) |
585 | return 0; | |
586 | ||
2f7e99bb TG |
587 | if (desc->irq_data.chip->irq_set_wake) |
588 | ret = desc->irq_data.chip->irq_set_wake(&desc->irq_data, on); | |
2db87321 UKK |
589 | |
590 | return ret; | |
591 | } | |
592 | ||
ba9a2331 | 593 | /** |
a0cd9ca2 | 594 | * irq_set_irq_wake - control irq power management wakeup |
ba9a2331 TG |
595 | * @irq: interrupt to control |
596 | * @on: enable/disable power management wakeup | |
597 | * | |
15a647eb DB |
598 | * Enable/disable power management wakeup mode, which is |
599 | * disabled by default. Enables and disables must match, | |
600 | * just as they match for non-wakeup mode support. | |
601 | * | |
602 | * Wakeup mode lets this IRQ wake the system from sleep | |
603 | * states like "suspend to RAM". | |
ba9a2331 | 604 | */ |
a0cd9ca2 | 605 | int irq_set_irq_wake(unsigned int irq, unsigned int on) |
ba9a2331 | 606 | { |
ba9a2331 | 607 | unsigned long flags; |
31d9d9b6 | 608 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
2db87321 | 609 | int ret = 0; |
ba9a2331 | 610 | |
13863a66 JJ |
611 | if (!desc) |
612 | return -EINVAL; | |
613 | ||
15a647eb DB |
614 | /* wakeup-capable irqs can be shared between drivers that |
615 | * don't need to have the same sleep mode behaviors. | |
616 | */ | |
15a647eb | 617 | if (on) { |
2db87321 UKK |
618 | if (desc->wake_depth++ == 0) { |
619 | ret = set_irq_wake_real(irq, on); | |
620 | if (ret) | |
621 | desc->wake_depth = 0; | |
622 | else | |
7f94226f | 623 | irqd_set(&desc->irq_data, IRQD_WAKEUP_STATE); |
2db87321 | 624 | } |
15a647eb DB |
625 | } else { |
626 | if (desc->wake_depth == 0) { | |
7a2c4770 | 627 | WARN(1, "Unbalanced IRQ %d wake disable\n", irq); |
2db87321 UKK |
628 | } else if (--desc->wake_depth == 0) { |
629 | ret = set_irq_wake_real(irq, on); | |
630 | if (ret) | |
631 | desc->wake_depth = 1; | |
632 | else | |
7f94226f | 633 | irqd_clear(&desc->irq_data, IRQD_WAKEUP_STATE); |
2db87321 | 634 | } |
15a647eb | 635 | } |
02725e74 | 636 | irq_put_desc_busunlock(desc, flags); |
ba9a2331 TG |
637 | return ret; |
638 | } | |
a0cd9ca2 | 639 | EXPORT_SYMBOL(irq_set_irq_wake); |
ba9a2331 | 640 | |
1da177e4 LT |
641 | /* |
642 | * Internal function that tells the architecture code whether a | |
643 | * particular irq has been exclusively allocated or is available | |
644 | * for driver use. | |
645 | */ | |
646 | int can_request_irq(unsigned int irq, unsigned long irqflags) | |
647 | { | |
cc8c3b78 | 648 | unsigned long flags; |
31d9d9b6 | 649 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
02725e74 | 650 | int canrequest = 0; |
1da177e4 | 651 | |
7d94f7ca YL |
652 | if (!desc) |
653 | return 0; | |
654 | ||
02725e74 | 655 | if (irq_settings_can_request(desc)) { |
2779db8d BH |
656 | if (!desc->action || |
657 | irqflags & desc->action->flags & IRQF_SHARED) | |
658 | canrequest = 1; | |
02725e74 TG |
659 | } |
660 | irq_put_desc_unlock(desc, flags); | |
661 | return canrequest; | |
1da177e4 LT |
662 | } |
663 | ||
a1ff541a | 664 | int __irq_set_trigger(struct irq_desc *desc, unsigned long flags) |
82736f4d | 665 | { |
6b8ff312 | 666 | struct irq_chip *chip = desc->irq_data.chip; |
d4d5e089 | 667 | int ret, unmask = 0; |
82736f4d | 668 | |
b2ba2c30 | 669 | if (!chip || !chip->irq_set_type) { |
82736f4d UKK |
670 | /* |
671 | * IRQF_TRIGGER_* but the PIC does not support multiple | |
672 | * flow-types? | |
673 | */ | |
a1ff541a JL |
674 | pr_debug("No set_type function for IRQ %d (%s)\n", |
675 | irq_desc_get_irq(desc), | |
f5d89470 | 676 | chip ? (chip->name ? : "unknown") : "unknown"); |
82736f4d UKK |
677 | return 0; |
678 | } | |
679 | ||
d4d5e089 | 680 | if (chip->flags & IRQCHIP_SET_TYPE_MASKED) { |
32f4125e | 681 | if (!irqd_irq_masked(&desc->irq_data)) |
d4d5e089 | 682 | mask_irq(desc); |
32f4125e | 683 | if (!irqd_irq_disabled(&desc->irq_data)) |
d4d5e089 TG |
684 | unmask = 1; |
685 | } | |
686 | ||
00b992de AK |
687 | /* Mask all flags except trigger mode */ |
688 | flags &= IRQ_TYPE_SENSE_MASK; | |
b2ba2c30 | 689 | ret = chip->irq_set_type(&desc->irq_data, flags); |
82736f4d | 690 | |
876dbd4c TG |
691 | switch (ret) { |
692 | case IRQ_SET_MASK_OK: | |
2cb62547 | 693 | case IRQ_SET_MASK_OK_DONE: |
876dbd4c TG |
694 | irqd_clear(&desc->irq_data, IRQD_TRIGGER_MASK); |
695 | irqd_set(&desc->irq_data, flags); | |
696 | ||
697 | case IRQ_SET_MASK_OK_NOCOPY: | |
698 | flags = irqd_get_trigger_type(&desc->irq_data); | |
699 | irq_settings_set_trigger_mask(desc, flags); | |
700 | irqd_clear(&desc->irq_data, IRQD_LEVEL); | |
701 | irq_settings_clr_level(desc); | |
702 | if (flags & IRQ_TYPE_LEVEL_MASK) { | |
703 | irq_settings_set_level(desc); | |
704 | irqd_set(&desc->irq_data, IRQD_LEVEL); | |
705 | } | |
46732475 | 706 | |
d4d5e089 | 707 | ret = 0; |
8fff39e0 | 708 | break; |
876dbd4c | 709 | default: |
97fd75b7 | 710 | pr_err("Setting trigger mode %lu for irq %u failed (%pF)\n", |
a1ff541a | 711 | flags, irq_desc_get_irq(desc), chip->irq_set_type); |
0c5d1eb7 | 712 | } |
d4d5e089 TG |
713 | if (unmask) |
714 | unmask_irq(desc); | |
82736f4d UKK |
715 | return ret; |
716 | } | |
717 | ||
293a7a0a TG |
718 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
719 | int irq_set_parent(int irq, int parent_irq) | |
720 | { | |
721 | unsigned long flags; | |
722 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | |
723 | ||
724 | if (!desc) | |
725 | return -EINVAL; | |
726 | ||
727 | desc->parent_irq = parent_irq; | |
728 | ||
729 | irq_put_desc_unlock(desc, flags); | |
730 | return 0; | |
731 | } | |
3118dac5 | 732 | EXPORT_SYMBOL_GPL(irq_set_parent); |
293a7a0a TG |
733 | #endif |
734 | ||
b25c340c TG |
735 | /* |
736 | * Default primary interrupt handler for threaded interrupts. Is | |
737 | * assigned as primary handler when request_threaded_irq is called | |
738 | * with handler == NULL. Useful for oneshot interrupts. | |
739 | */ | |
740 | static irqreturn_t irq_default_primary_handler(int irq, void *dev_id) | |
741 | { | |
742 | return IRQ_WAKE_THREAD; | |
743 | } | |
744 | ||
399b5da2 TG |
745 | /* |
746 | * Primary handler for nested threaded interrupts. Should never be | |
747 | * called. | |
748 | */ | |
749 | static irqreturn_t irq_nested_primary_handler(int irq, void *dev_id) | |
750 | { | |
751 | WARN(1, "Primary handler called for nested irq %d\n", irq); | |
752 | return IRQ_NONE; | |
753 | } | |
754 | ||
2a1d3ab8 TG |
755 | static irqreturn_t irq_forced_secondary_handler(int irq, void *dev_id) |
756 | { | |
757 | WARN(1, "Secondary action handler called for irq %d\n", irq); | |
758 | return IRQ_NONE; | |
759 | } | |
760 | ||
3aa551c9 TG |
761 | static int irq_wait_for_interrupt(struct irqaction *action) |
762 | { | |
550acb19 IY |
763 | set_current_state(TASK_INTERRUPTIBLE); |
764 | ||
3aa551c9 | 765 | while (!kthread_should_stop()) { |
f48fe81e TG |
766 | |
767 | if (test_and_clear_bit(IRQTF_RUNTHREAD, | |
768 | &action->thread_flags)) { | |
3aa551c9 TG |
769 | __set_current_state(TASK_RUNNING); |
770 | return 0; | |
f48fe81e TG |
771 | } |
772 | schedule(); | |
550acb19 | 773 | set_current_state(TASK_INTERRUPTIBLE); |
3aa551c9 | 774 | } |
550acb19 | 775 | __set_current_state(TASK_RUNNING); |
3aa551c9 TG |
776 | return -1; |
777 | } | |
778 | ||
b25c340c TG |
779 | /* |
780 | * Oneshot interrupts keep the irq line masked until the threaded | |
781 | * handler finished. unmask if the interrupt has not been disabled and | |
782 | * is marked MASKED. | |
783 | */ | |
b5faba21 | 784 | static void irq_finalize_oneshot(struct irq_desc *desc, |
f3f79e38 | 785 | struct irqaction *action) |
b25c340c | 786 | { |
2a1d3ab8 TG |
787 | if (!(desc->istate & IRQS_ONESHOT) || |
788 | action->handler == irq_forced_secondary_handler) | |
b5faba21 | 789 | return; |
0b1adaa0 | 790 | again: |
3876ec9e | 791 | chip_bus_lock(desc); |
239007b8 | 792 | raw_spin_lock_irq(&desc->lock); |
0b1adaa0 TG |
793 | |
794 | /* | |
795 | * Implausible though it may be we need to protect us against | |
796 | * the following scenario: | |
797 | * | |
798 | * The thread is faster done than the hard interrupt handler | |
799 | * on the other CPU. If we unmask the irq line then the | |
800 | * interrupt can come in again and masks the line, leaves due | |
009b4c3b | 801 | * to IRQS_INPROGRESS and the irq line is masked forever. |
b5faba21 TG |
802 | * |
803 | * This also serializes the state of shared oneshot handlers | |
804 | * versus "desc->threads_onehsot |= action->thread_mask;" in | |
805 | * irq_wake_thread(). See the comment there which explains the | |
806 | * serialization. | |
0b1adaa0 | 807 | */ |
32f4125e | 808 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) { |
0b1adaa0 | 809 | raw_spin_unlock_irq(&desc->lock); |
3876ec9e | 810 | chip_bus_sync_unlock(desc); |
0b1adaa0 TG |
811 | cpu_relax(); |
812 | goto again; | |
813 | } | |
814 | ||
b5faba21 TG |
815 | /* |
816 | * Now check again, whether the thread should run. Otherwise | |
817 | * we would clear the threads_oneshot bit of this thread which | |
818 | * was just set. | |
819 | */ | |
f3f79e38 | 820 | if (test_bit(IRQTF_RUNTHREAD, &action->thread_flags)) |
b5faba21 TG |
821 | goto out_unlock; |
822 | ||
823 | desc->threads_oneshot &= ~action->thread_mask; | |
824 | ||
32f4125e TG |
825 | if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && |
826 | irqd_irq_masked(&desc->irq_data)) | |
328a4978 | 827 | unmask_threaded_irq(desc); |
32f4125e | 828 | |
b5faba21 | 829 | out_unlock: |
239007b8 | 830 | raw_spin_unlock_irq(&desc->lock); |
3876ec9e | 831 | chip_bus_sync_unlock(desc); |
b25c340c TG |
832 | } |
833 | ||
61f38261 | 834 | #ifdef CONFIG_SMP |
591d2fb0 | 835 | /* |
b04c644e | 836 | * Check whether we need to change the affinity of the interrupt thread. |
591d2fb0 TG |
837 | */ |
838 | static void | |
839 | irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) | |
840 | { | |
841 | cpumask_var_t mask; | |
04aa530e | 842 | bool valid = true; |
591d2fb0 TG |
843 | |
844 | if (!test_and_clear_bit(IRQTF_AFFINITY, &action->thread_flags)) | |
845 | return; | |
846 | ||
847 | /* | |
848 | * In case we are out of memory we set IRQTF_AFFINITY again and | |
849 | * try again next time | |
850 | */ | |
851 | if (!alloc_cpumask_var(&mask, GFP_KERNEL)) { | |
852 | set_bit(IRQTF_AFFINITY, &action->thread_flags); | |
853 | return; | |
854 | } | |
855 | ||
239007b8 | 856 | raw_spin_lock_irq(&desc->lock); |
04aa530e TG |
857 | /* |
858 | * This code is triggered unconditionally. Check the affinity | |
859 | * mask pointer. For CPU_MASK_OFFSTACK=n this is optimized out. | |
860 | */ | |
d170fe7d | 861 | if (cpumask_available(desc->irq_common_data.affinity)) |
9df872fa | 862 | cpumask_copy(mask, desc->irq_common_data.affinity); |
04aa530e TG |
863 | else |
864 | valid = false; | |
239007b8 | 865 | raw_spin_unlock_irq(&desc->lock); |
591d2fb0 | 866 | |
04aa530e TG |
867 | if (valid) |
868 | set_cpus_allowed_ptr(current, mask); | |
591d2fb0 TG |
869 | free_cpumask_var(mask); |
870 | } | |
61f38261 BP |
871 | #else |
872 | static inline void | |
873 | irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) { } | |
874 | #endif | |
591d2fb0 | 875 | |
8d32a307 TG |
876 | /* |
877 | * Interrupts which are not explicitely requested as threaded | |
878 | * interrupts rely on the implicit bh/preempt disable of the hard irq | |
879 | * context. So we need to disable bh here to avoid deadlocks and other | |
880 | * side effects. | |
881 | */ | |
3a43e05f | 882 | static irqreturn_t |
8d32a307 TG |
883 | irq_forced_thread_fn(struct irq_desc *desc, struct irqaction *action) |
884 | { | |
3a43e05f SAS |
885 | irqreturn_t ret; |
886 | ||
8d32a307 | 887 | local_bh_disable(); |
3a43e05f | 888 | ret = action->thread_fn(action->irq, action->dev_id); |
f3f79e38 | 889 | irq_finalize_oneshot(desc, action); |
8d32a307 | 890 | local_bh_enable(); |
3a43e05f | 891 | return ret; |
8d32a307 TG |
892 | } |
893 | ||
894 | /* | |
f788e7bf | 895 | * Interrupts explicitly requested as threaded interrupts want to be |
8d32a307 TG |
896 | * preemtible - many of them need to sleep and wait for slow busses to |
897 | * complete. | |
898 | */ | |
3a43e05f SAS |
899 | static irqreturn_t irq_thread_fn(struct irq_desc *desc, |
900 | struct irqaction *action) | |
8d32a307 | 901 | { |
3a43e05f SAS |
902 | irqreturn_t ret; |
903 | ||
904 | ret = action->thread_fn(action->irq, action->dev_id); | |
f3f79e38 | 905 | irq_finalize_oneshot(desc, action); |
3a43e05f | 906 | return ret; |
8d32a307 TG |
907 | } |
908 | ||
7140ea19 IY |
909 | static void wake_threads_waitq(struct irq_desc *desc) |
910 | { | |
c685689f | 911 | if (atomic_dec_and_test(&desc->threads_active)) |
7140ea19 IY |
912 | wake_up(&desc->wait_for_threads); |
913 | } | |
914 | ||
67d12145 | 915 | static void irq_thread_dtor(struct callback_head *unused) |
4d1d61a6 ON |
916 | { |
917 | struct task_struct *tsk = current; | |
918 | struct irq_desc *desc; | |
919 | struct irqaction *action; | |
920 | ||
921 | if (WARN_ON_ONCE(!(current->flags & PF_EXITING))) | |
922 | return; | |
923 | ||
924 | action = kthread_data(tsk); | |
925 | ||
fb21affa | 926 | pr_err("exiting task \"%s\" (%d) is an active IRQ thread (irq %d)\n", |
19af395d | 927 | tsk->comm, tsk->pid, action->irq); |
4d1d61a6 ON |
928 | |
929 | ||
930 | desc = irq_to_desc(action->irq); | |
931 | /* | |
932 | * If IRQTF_RUNTHREAD is set, we need to decrement | |
933 | * desc->threads_active and wake possible waiters. | |
934 | */ | |
935 | if (test_and_clear_bit(IRQTF_RUNTHREAD, &action->thread_flags)) | |
936 | wake_threads_waitq(desc); | |
937 | ||
938 | /* Prevent a stale desc->threads_oneshot */ | |
939 | irq_finalize_oneshot(desc, action); | |
940 | } | |
941 | ||
2a1d3ab8 TG |
942 | static void irq_wake_secondary(struct irq_desc *desc, struct irqaction *action) |
943 | { | |
944 | struct irqaction *secondary = action->secondary; | |
945 | ||
946 | if (WARN_ON_ONCE(!secondary)) | |
947 | return; | |
948 | ||
949 | raw_spin_lock_irq(&desc->lock); | |
950 | __irq_wake_thread(desc, secondary); | |
951 | raw_spin_unlock_irq(&desc->lock); | |
952 | } | |
953 | ||
3aa551c9 TG |
954 | /* |
955 | * Interrupt handler thread | |
956 | */ | |
957 | static int irq_thread(void *data) | |
958 | { | |
67d12145 | 959 | struct callback_head on_exit_work; |
3aa551c9 TG |
960 | struct irqaction *action = data; |
961 | struct irq_desc *desc = irq_to_desc(action->irq); | |
3a43e05f SAS |
962 | irqreturn_t (*handler_fn)(struct irq_desc *desc, |
963 | struct irqaction *action); | |
3aa551c9 | 964 | |
540b60e2 | 965 | if (force_irqthreads && test_bit(IRQTF_FORCED_THREAD, |
8d32a307 TG |
966 | &action->thread_flags)) |
967 | handler_fn = irq_forced_thread_fn; | |
968 | else | |
969 | handler_fn = irq_thread_fn; | |
970 | ||
41f9d29f | 971 | init_task_work(&on_exit_work, irq_thread_dtor); |
4d1d61a6 | 972 | task_work_add(current, &on_exit_work, false); |
3aa551c9 | 973 | |
f3de44ed SM |
974 | irq_thread_check_affinity(desc, action); |
975 | ||
3aa551c9 | 976 | while (!irq_wait_for_interrupt(action)) { |
7140ea19 | 977 | irqreturn_t action_ret; |
3aa551c9 | 978 | |
591d2fb0 TG |
979 | irq_thread_check_affinity(desc, action); |
980 | ||
7140ea19 | 981 | action_ret = handler_fn(desc, action); |
1e77d0a1 TG |
982 | if (action_ret == IRQ_HANDLED) |
983 | atomic_inc(&desc->threads_handled); | |
2a1d3ab8 TG |
984 | if (action_ret == IRQ_WAKE_THREAD) |
985 | irq_wake_secondary(desc, action); | |
3aa551c9 | 986 | |
7140ea19 | 987 | wake_threads_waitq(desc); |
3aa551c9 TG |
988 | } |
989 | ||
7140ea19 IY |
990 | /* |
991 | * This is the regular exit path. __free_irq() is stopping the | |
992 | * thread via kthread_stop() after calling | |
993 | * synchronize_irq(). So neither IRQTF_RUNTHREAD nor the | |
e04268b0 TG |
994 | * oneshot mask bit can be set. We cannot verify that as we |
995 | * cannot touch the oneshot mask at this point anymore as | |
996 | * __setup_irq() might have given out currents thread_mask | |
997 | * again. | |
3aa551c9 | 998 | */ |
4d1d61a6 | 999 | task_work_cancel(current, irq_thread_dtor); |
3aa551c9 TG |
1000 | return 0; |
1001 | } | |
1002 | ||
a92444c6 TG |
1003 | /** |
1004 | * irq_wake_thread - wake the irq thread for the action identified by dev_id | |
1005 | * @irq: Interrupt line | |
1006 | * @dev_id: Device identity for which the thread should be woken | |
1007 | * | |
1008 | */ | |
1009 | void irq_wake_thread(unsigned int irq, void *dev_id) | |
1010 | { | |
1011 | struct irq_desc *desc = irq_to_desc(irq); | |
1012 | struct irqaction *action; | |
1013 | unsigned long flags; | |
1014 | ||
1015 | if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
1016 | return; | |
1017 | ||
1018 | raw_spin_lock_irqsave(&desc->lock, flags); | |
f944b5a7 | 1019 | for_each_action_of_desc(desc, action) { |
a92444c6 TG |
1020 | if (action->dev_id == dev_id) { |
1021 | if (action->thread) | |
1022 | __irq_wake_thread(desc, action); | |
1023 | break; | |
1024 | } | |
1025 | } | |
1026 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1027 | } | |
1028 | EXPORT_SYMBOL_GPL(irq_wake_thread); | |
1029 | ||
2a1d3ab8 | 1030 | static int irq_setup_forced_threading(struct irqaction *new) |
8d32a307 TG |
1031 | { |
1032 | if (!force_irqthreads) | |
2a1d3ab8 | 1033 | return 0; |
8d32a307 | 1034 | if (new->flags & (IRQF_NO_THREAD | IRQF_PERCPU | IRQF_ONESHOT)) |
2a1d3ab8 | 1035 | return 0; |
8d32a307 TG |
1036 | |
1037 | new->flags |= IRQF_ONESHOT; | |
1038 | ||
2a1d3ab8 TG |
1039 | /* |
1040 | * Handle the case where we have a real primary handler and a | |
1041 | * thread handler. We force thread them as well by creating a | |
1042 | * secondary action. | |
1043 | */ | |
1044 | if (new->handler != irq_default_primary_handler && new->thread_fn) { | |
1045 | /* Allocate the secondary action */ | |
1046 | new->secondary = kzalloc(sizeof(struct irqaction), GFP_KERNEL); | |
1047 | if (!new->secondary) | |
1048 | return -ENOMEM; | |
1049 | new->secondary->handler = irq_forced_secondary_handler; | |
1050 | new->secondary->thread_fn = new->thread_fn; | |
1051 | new->secondary->dev_id = new->dev_id; | |
1052 | new->secondary->irq = new->irq; | |
1053 | new->secondary->name = new->name; | |
8d32a307 | 1054 | } |
2a1d3ab8 TG |
1055 | /* Deal with the primary handler */ |
1056 | set_bit(IRQTF_FORCED_THREAD, &new->thread_flags); | |
1057 | new->thread_fn = new->handler; | |
1058 | new->handler = irq_default_primary_handler; | |
1059 | return 0; | |
8d32a307 TG |
1060 | } |
1061 | ||
c1bacbae TG |
1062 | static int irq_request_resources(struct irq_desc *desc) |
1063 | { | |
1064 | struct irq_data *d = &desc->irq_data; | |
1065 | struct irq_chip *c = d->chip; | |
1066 | ||
1067 | return c->irq_request_resources ? c->irq_request_resources(d) : 0; | |
1068 | } | |
1069 | ||
1070 | static void irq_release_resources(struct irq_desc *desc) | |
1071 | { | |
1072 | struct irq_data *d = &desc->irq_data; | |
1073 | struct irq_chip *c = d->chip; | |
1074 | ||
1075 | if (c->irq_release_resources) | |
1076 | c->irq_release_resources(d); | |
1077 | } | |
1078 | ||
2a1d3ab8 TG |
1079 | static int |
1080 | setup_irq_thread(struct irqaction *new, unsigned int irq, bool secondary) | |
1081 | { | |
1082 | struct task_struct *t; | |
1083 | struct sched_param param = { | |
1084 | .sched_priority = MAX_USER_RT_PRIO/2, | |
1085 | }; | |
1086 | ||
1087 | if (!secondary) { | |
1088 | t = kthread_create(irq_thread, new, "irq/%d-%s", irq, | |
1089 | new->name); | |
1090 | } else { | |
1091 | t = kthread_create(irq_thread, new, "irq/%d-s-%s", irq, | |
1092 | new->name); | |
1093 | param.sched_priority -= 1; | |
1094 | } | |
1095 | ||
1096 | if (IS_ERR(t)) | |
1097 | return PTR_ERR(t); | |
1098 | ||
1099 | sched_setscheduler_nocheck(t, SCHED_FIFO, ¶m); | |
1100 | ||
1101 | /* | |
1102 | * We keep the reference to the task struct even if | |
1103 | * the thread dies to avoid that the interrupt code | |
1104 | * references an already freed task_struct. | |
1105 | */ | |
1106 | get_task_struct(t); | |
1107 | new->thread = t; | |
1108 | /* | |
1109 | * Tell the thread to set its affinity. This is | |
1110 | * important for shared interrupt handlers as we do | |
1111 | * not invoke setup_affinity() for the secondary | |
1112 | * handlers as everything is already set up. Even for | |
1113 | * interrupts marked with IRQF_NO_BALANCE this is | |
1114 | * correct as we want the thread to move to the cpu(s) | |
1115 | * on which the requesting code placed the interrupt. | |
1116 | */ | |
1117 | set_bit(IRQTF_AFFINITY, &new->thread_flags); | |
1118 | return 0; | |
1119 | } | |
1120 | ||
1da177e4 LT |
1121 | /* |
1122 | * Internal function to register an irqaction - typically used to | |
1123 | * allocate special interrupts that are part of the architecture. | |
1124 | */ | |
d3c60047 | 1125 | static int |
327ec569 | 1126 | __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) |
1da177e4 | 1127 | { |
f17c7545 | 1128 | struct irqaction *old, **old_ptr; |
b5faba21 | 1129 | unsigned long flags, thread_mask = 0; |
3b8249e7 TG |
1130 | int ret, nested, shared = 0; |
1131 | cpumask_var_t mask; | |
1da177e4 | 1132 | |
7d94f7ca | 1133 | if (!desc) |
c2b5a251 MW |
1134 | return -EINVAL; |
1135 | ||
6b8ff312 | 1136 | if (desc->irq_data.chip == &no_irq_chip) |
1da177e4 | 1137 | return -ENOSYS; |
b6873807 SAS |
1138 | if (!try_module_get(desc->owner)) |
1139 | return -ENODEV; | |
1da177e4 | 1140 | |
2a1d3ab8 TG |
1141 | new->irq = irq; |
1142 | ||
4b357dae JH |
1143 | /* |
1144 | * If the trigger type is not specified by the caller, | |
1145 | * then use the default for this interrupt. | |
1146 | */ | |
1147 | if (!(new->flags & IRQF_TRIGGER_MASK)) | |
1148 | new->flags |= irqd_get_trigger_type(&desc->irq_data); | |
1149 | ||
3aa551c9 | 1150 | /* |
399b5da2 TG |
1151 | * Check whether the interrupt nests into another interrupt |
1152 | * thread. | |
1153 | */ | |
1ccb4e61 | 1154 | nested = irq_settings_is_nested_thread(desc); |
399b5da2 | 1155 | if (nested) { |
b6873807 SAS |
1156 | if (!new->thread_fn) { |
1157 | ret = -EINVAL; | |
1158 | goto out_mput; | |
1159 | } | |
399b5da2 TG |
1160 | /* |
1161 | * Replace the primary handler which was provided from | |
1162 | * the driver for non nested interrupt handling by the | |
1163 | * dummy function which warns when called. | |
1164 | */ | |
1165 | new->handler = irq_nested_primary_handler; | |
8d32a307 | 1166 | } else { |
2a1d3ab8 TG |
1167 | if (irq_settings_can_thread(desc)) { |
1168 | ret = irq_setup_forced_threading(new); | |
1169 | if (ret) | |
1170 | goto out_mput; | |
1171 | } | |
399b5da2 TG |
1172 | } |
1173 | ||
3aa551c9 | 1174 | /* |
399b5da2 TG |
1175 | * Create a handler thread when a thread function is supplied |
1176 | * and the interrupt does not nest into another interrupt | |
1177 | * thread. | |
3aa551c9 | 1178 | */ |
399b5da2 | 1179 | if (new->thread_fn && !nested) { |
2a1d3ab8 TG |
1180 | ret = setup_irq_thread(new, irq, false); |
1181 | if (ret) | |
b6873807 | 1182 | goto out_mput; |
2a1d3ab8 TG |
1183 | if (new->secondary) { |
1184 | ret = setup_irq_thread(new->secondary, irq, true); | |
1185 | if (ret) | |
1186 | goto out_thread; | |
b6873807 | 1187 | } |
3aa551c9 TG |
1188 | } |
1189 | ||
3b8249e7 TG |
1190 | if (!alloc_cpumask_var(&mask, GFP_KERNEL)) { |
1191 | ret = -ENOMEM; | |
1192 | goto out_thread; | |
1193 | } | |
1194 | ||
dc9b229a TG |
1195 | /* |
1196 | * Drivers are often written to work w/o knowledge about the | |
1197 | * underlying irq chip implementation, so a request for a | |
1198 | * threaded irq without a primary hard irq context handler | |
1199 | * requires the ONESHOT flag to be set. Some irq chips like | |
1200 | * MSI based interrupts are per se one shot safe. Check the | |
1201 | * chip flags, so we can avoid the unmask dance at the end of | |
1202 | * the threaded handler for those. | |
1203 | */ | |
1204 | if (desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE) | |
1205 | new->flags &= ~IRQF_ONESHOT; | |
1206 | ||
1da177e4 LT |
1207 | /* |
1208 | * The following block of code has to be executed atomically | |
1209 | */ | |
239007b8 | 1210 | raw_spin_lock_irqsave(&desc->lock, flags); |
f17c7545 IM |
1211 | old_ptr = &desc->action; |
1212 | old = *old_ptr; | |
06fcb0c6 | 1213 | if (old) { |
e76de9f8 TG |
1214 | /* |
1215 | * Can't share interrupts unless both agree to and are | |
1216 | * the same type (level, edge, polarity). So both flag | |
3cca53b0 | 1217 | * fields must have IRQF_SHARED set and the bits which |
9d591edd TG |
1218 | * set the trigger type must match. Also all must |
1219 | * agree on ONESHOT. | |
e76de9f8 | 1220 | */ |
382bd4de HG |
1221 | unsigned int oldtype = irqd_get_trigger_type(&desc->irq_data); |
1222 | ||
3cca53b0 | 1223 | if (!((old->flags & new->flags) & IRQF_SHARED) || |
382bd4de | 1224 | (oldtype != (new->flags & IRQF_TRIGGER_MASK)) || |
f5d89470 | 1225 | ((old->flags ^ new->flags) & IRQF_ONESHOT)) |
f5163427 DS |
1226 | goto mismatch; |
1227 | ||
f5163427 | 1228 | /* All handlers must agree on per-cpuness */ |
3cca53b0 TG |
1229 | if ((old->flags & IRQF_PERCPU) != |
1230 | (new->flags & IRQF_PERCPU)) | |
f5163427 | 1231 | goto mismatch; |
1da177e4 LT |
1232 | |
1233 | /* add new interrupt at end of irq queue */ | |
1234 | do { | |
52abb700 TG |
1235 | /* |
1236 | * Or all existing action->thread_mask bits, | |
1237 | * so we can find the next zero bit for this | |
1238 | * new action. | |
1239 | */ | |
b5faba21 | 1240 | thread_mask |= old->thread_mask; |
f17c7545 IM |
1241 | old_ptr = &old->next; |
1242 | old = *old_ptr; | |
1da177e4 LT |
1243 | } while (old); |
1244 | shared = 1; | |
1245 | } | |
1246 | ||
b5faba21 | 1247 | /* |
52abb700 TG |
1248 | * Setup the thread mask for this irqaction for ONESHOT. For |
1249 | * !ONESHOT irqs the thread mask is 0 so we can avoid a | |
1250 | * conditional in irq_wake_thread(). | |
b5faba21 | 1251 | */ |
52abb700 TG |
1252 | if (new->flags & IRQF_ONESHOT) { |
1253 | /* | |
1254 | * Unlikely to have 32 resp 64 irqs sharing one line, | |
1255 | * but who knows. | |
1256 | */ | |
1257 | if (thread_mask == ~0UL) { | |
1258 | ret = -EBUSY; | |
1259 | goto out_mask; | |
1260 | } | |
1261 | /* | |
1262 | * The thread_mask for the action is or'ed to | |
1263 | * desc->thread_active to indicate that the | |
1264 | * IRQF_ONESHOT thread handler has been woken, but not | |
1265 | * yet finished. The bit is cleared when a thread | |
1266 | * completes. When all threads of a shared interrupt | |
1267 | * line have completed desc->threads_active becomes | |
1268 | * zero and the interrupt line is unmasked. See | |
1269 | * handle.c:irq_wake_thread() for further information. | |
1270 | * | |
1271 | * If no thread is woken by primary (hard irq context) | |
1272 | * interrupt handlers, then desc->threads_active is | |
1273 | * also checked for zero to unmask the irq line in the | |
1274 | * affected hard irq flow handlers | |
1275 | * (handle_[fasteoi|level]_irq). | |
1276 | * | |
1277 | * The new action gets the first zero bit of | |
1278 | * thread_mask assigned. See the loop above which or's | |
1279 | * all existing action->thread_mask bits. | |
1280 | */ | |
1281 | new->thread_mask = 1 << ffz(thread_mask); | |
1c6c6952 | 1282 | |
dc9b229a TG |
1283 | } else if (new->handler == irq_default_primary_handler && |
1284 | !(desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE)) { | |
1c6c6952 TG |
1285 | /* |
1286 | * The interrupt was requested with handler = NULL, so | |
1287 | * we use the default primary handler for it. But it | |
1288 | * does not have the oneshot flag set. In combination | |
1289 | * with level interrupts this is deadly, because the | |
1290 | * default primary handler just wakes the thread, then | |
1291 | * the irq lines is reenabled, but the device still | |
1292 | * has the level irq asserted. Rinse and repeat.... | |
1293 | * | |
1294 | * While this works for edge type interrupts, we play | |
1295 | * it safe and reject unconditionally because we can't | |
1296 | * say for sure which type this interrupt really | |
1297 | * has. The type flags are unreliable as the | |
1298 | * underlying chip implementation can override them. | |
1299 | */ | |
97fd75b7 | 1300 | pr_err("Threaded irq requested with handler=NULL and !ONESHOT for irq %d\n", |
1c6c6952 TG |
1301 | irq); |
1302 | ret = -EINVAL; | |
1303 | goto out_mask; | |
b5faba21 | 1304 | } |
b5faba21 | 1305 | |
1da177e4 | 1306 | if (!shared) { |
c1bacbae TG |
1307 | ret = irq_request_resources(desc); |
1308 | if (ret) { | |
1309 | pr_err("Failed to request resources for %s (irq %d) on irqchip %s\n", | |
1310 | new->name, irq, desc->irq_data.chip->name); | |
1311 | goto out_mask; | |
1312 | } | |
1313 | ||
3aa551c9 TG |
1314 | init_waitqueue_head(&desc->wait_for_threads); |
1315 | ||
e76de9f8 | 1316 | /* Setup the type (level, edge polarity) if configured: */ |
3cca53b0 | 1317 | if (new->flags & IRQF_TRIGGER_MASK) { |
a1ff541a JL |
1318 | ret = __irq_set_trigger(desc, |
1319 | new->flags & IRQF_TRIGGER_MASK); | |
82736f4d | 1320 | |
fa07ab72 HK |
1321 | if (ret) { |
1322 | irq_release_resources(desc); | |
3b8249e7 | 1323 | goto out_mask; |
fa07ab72 | 1324 | } |
091738a2 | 1325 | } |
6a6de9ef | 1326 | |
009b4c3b | 1327 | desc->istate &= ~(IRQS_AUTODETECT | IRQS_SPURIOUS_DISABLED | \ |
32f4125e TG |
1328 | IRQS_ONESHOT | IRQS_WAITING); |
1329 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); | |
94d39e1f | 1330 | |
a005677b TG |
1331 | if (new->flags & IRQF_PERCPU) { |
1332 | irqd_set(&desc->irq_data, IRQD_PER_CPU); | |
1333 | irq_settings_set_per_cpu(desc); | |
1334 | } | |
6a58fb3b | 1335 | |
b25c340c | 1336 | if (new->flags & IRQF_ONESHOT) |
3d67baec | 1337 | desc->istate |= IRQS_ONESHOT; |
b25c340c | 1338 | |
04c848d3 | 1339 | if (irq_settings_can_autoenable(desc)) { |
b4bc724e | 1340 | irq_startup(desc, true); |
04c848d3 TG |
1341 | } else { |
1342 | /* | |
1343 | * Shared interrupts do not go well with disabling | |
1344 | * auto enable. The sharing interrupt might request | |
1345 | * it while it's still disabled and then wait for | |
1346 | * interrupts forever. | |
1347 | */ | |
1348 | WARN_ON_ONCE(new->flags & IRQF_SHARED); | |
e76de9f8 TG |
1349 | /* Undo nested disables: */ |
1350 | desc->depth = 1; | |
04c848d3 | 1351 | } |
18404756 | 1352 | |
612e3684 | 1353 | /* Exclude IRQ from balancing if requested */ |
a005677b TG |
1354 | if (new->flags & IRQF_NOBALANCING) { |
1355 | irq_settings_set_no_balancing(desc); | |
1356 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | |
1357 | } | |
612e3684 | 1358 | |
18404756 | 1359 | /* Set default affinity mask once everything is setup */ |
a8a98eac | 1360 | setup_affinity(desc, mask); |
0c5d1eb7 | 1361 | |
876dbd4c TG |
1362 | } else if (new->flags & IRQF_TRIGGER_MASK) { |
1363 | unsigned int nmsk = new->flags & IRQF_TRIGGER_MASK; | |
7ee7e87d | 1364 | unsigned int omsk = irqd_get_trigger_type(&desc->irq_data); |
876dbd4c TG |
1365 | |
1366 | if (nmsk != omsk) | |
1367 | /* hope the handler works with current trigger mode */ | |
a395d6a7 | 1368 | pr_warn("irq %d uses trigger mode %u; requested %u\n", |
7ee7e87d | 1369 | irq, omsk, nmsk); |
1da177e4 | 1370 | } |
82736f4d | 1371 | |
f17c7545 | 1372 | *old_ptr = new; |
82736f4d | 1373 | |
cab303be TG |
1374 | irq_pm_install_action(desc, new); |
1375 | ||
8528b0f1 LT |
1376 | /* Reset broken irq detection when installing new handler */ |
1377 | desc->irq_count = 0; | |
1378 | desc->irqs_unhandled = 0; | |
1adb0850 TG |
1379 | |
1380 | /* | |
1381 | * Check whether we disabled the irq via the spurious handler | |
1382 | * before. Reenable it and give it another chance. | |
1383 | */ | |
7acdd53e TG |
1384 | if (shared && (desc->istate & IRQS_SPURIOUS_DISABLED)) { |
1385 | desc->istate &= ~IRQS_SPURIOUS_DISABLED; | |
79ff1cda | 1386 | __enable_irq(desc); |
1adb0850 TG |
1387 | } |
1388 | ||
239007b8 | 1389 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 | 1390 | |
69ab8494 TG |
1391 | /* |
1392 | * Strictly no need to wake it up, but hung_task complains | |
1393 | * when no hard interrupt wakes the thread up. | |
1394 | */ | |
1395 | if (new->thread) | |
1396 | wake_up_process(new->thread); | |
2a1d3ab8 TG |
1397 | if (new->secondary) |
1398 | wake_up_process(new->secondary->thread); | |
69ab8494 | 1399 | |
2c6927a3 | 1400 | register_irq_proc(irq, desc); |
087cdfb6 | 1401 | irq_add_debugfs_entry(irq, desc); |
1da177e4 LT |
1402 | new->dir = NULL; |
1403 | register_handler_proc(irq, new); | |
4f5058c3 | 1404 | free_cpumask_var(mask); |
1da177e4 LT |
1405 | |
1406 | return 0; | |
f5163427 DS |
1407 | |
1408 | mismatch: | |
3cca53b0 | 1409 | if (!(new->flags & IRQF_PROBE_SHARED)) { |
97fd75b7 | 1410 | pr_err("Flags mismatch irq %d. %08x (%s) vs. %08x (%s)\n", |
f5d89470 TG |
1411 | irq, new->flags, new->name, old->flags, old->name); |
1412 | #ifdef CONFIG_DEBUG_SHIRQ | |
13e87ec6 | 1413 | dump_stack(); |
3f050447 | 1414 | #endif |
f5d89470 | 1415 | } |
3aa551c9 TG |
1416 | ret = -EBUSY; |
1417 | ||
3b8249e7 | 1418 | out_mask: |
1c389795 | 1419 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3b8249e7 TG |
1420 | free_cpumask_var(mask); |
1421 | ||
3aa551c9 | 1422 | out_thread: |
3aa551c9 TG |
1423 | if (new->thread) { |
1424 | struct task_struct *t = new->thread; | |
1425 | ||
1426 | new->thread = NULL; | |
05d74efa | 1427 | kthread_stop(t); |
3aa551c9 TG |
1428 | put_task_struct(t); |
1429 | } | |
2a1d3ab8 TG |
1430 | if (new->secondary && new->secondary->thread) { |
1431 | struct task_struct *t = new->secondary->thread; | |
1432 | ||
1433 | new->secondary->thread = NULL; | |
1434 | kthread_stop(t); | |
1435 | put_task_struct(t); | |
1436 | } | |
b6873807 SAS |
1437 | out_mput: |
1438 | module_put(desc->owner); | |
3aa551c9 | 1439 | return ret; |
1da177e4 LT |
1440 | } |
1441 | ||
d3c60047 TG |
1442 | /** |
1443 | * setup_irq - setup an interrupt | |
1444 | * @irq: Interrupt line to setup | |
1445 | * @act: irqaction for the interrupt | |
1446 | * | |
1447 | * Used to statically setup interrupts in the early boot process. | |
1448 | */ | |
1449 | int setup_irq(unsigned int irq, struct irqaction *act) | |
1450 | { | |
986c011d | 1451 | int retval; |
d3c60047 TG |
1452 | struct irq_desc *desc = irq_to_desc(irq); |
1453 | ||
9b5d585d | 1454 | if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) |
31d9d9b6 | 1455 | return -EINVAL; |
be45beb2 JH |
1456 | |
1457 | retval = irq_chip_pm_get(&desc->irq_data); | |
1458 | if (retval < 0) | |
1459 | return retval; | |
1460 | ||
986c011d DD |
1461 | chip_bus_lock(desc); |
1462 | retval = __setup_irq(irq, desc, act); | |
1463 | chip_bus_sync_unlock(desc); | |
1464 | ||
be45beb2 JH |
1465 | if (retval) |
1466 | irq_chip_pm_put(&desc->irq_data); | |
1467 | ||
986c011d | 1468 | return retval; |
d3c60047 | 1469 | } |
eb53b4e8 | 1470 | EXPORT_SYMBOL_GPL(setup_irq); |
d3c60047 | 1471 | |
31d9d9b6 | 1472 | /* |
cbf94f06 MD |
1473 | * Internal function to unregister an irqaction - used to free |
1474 | * regular and special interrupts that are part of the architecture. | |
1da177e4 | 1475 | */ |
cbf94f06 | 1476 | static struct irqaction *__free_irq(unsigned int irq, void *dev_id) |
1da177e4 | 1477 | { |
d3c60047 | 1478 | struct irq_desc *desc = irq_to_desc(irq); |
f17c7545 | 1479 | struct irqaction *action, **action_ptr; |
1da177e4 LT |
1480 | unsigned long flags; |
1481 | ||
ae88a23b | 1482 | WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq); |
7d94f7ca | 1483 | |
7d94f7ca | 1484 | if (!desc) |
f21cfb25 | 1485 | return NULL; |
1da177e4 | 1486 | |
abc7e40c | 1487 | chip_bus_lock(desc); |
239007b8 | 1488 | raw_spin_lock_irqsave(&desc->lock, flags); |
ae88a23b IM |
1489 | |
1490 | /* | |
1491 | * There can be multiple actions per IRQ descriptor, find the right | |
1492 | * one based on the dev_id: | |
1493 | */ | |
f17c7545 | 1494 | action_ptr = &desc->action; |
1da177e4 | 1495 | for (;;) { |
f17c7545 | 1496 | action = *action_ptr; |
1da177e4 | 1497 | |
ae88a23b IM |
1498 | if (!action) { |
1499 | WARN(1, "Trying to free already-free IRQ %d\n", irq); | |
239007b8 | 1500 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
abc7e40c | 1501 | chip_bus_sync_unlock(desc); |
f21cfb25 | 1502 | return NULL; |
ae88a23b | 1503 | } |
1da177e4 | 1504 | |
8316e381 IM |
1505 | if (action->dev_id == dev_id) |
1506 | break; | |
f17c7545 | 1507 | action_ptr = &action->next; |
ae88a23b | 1508 | } |
dbce706e | 1509 | |
ae88a23b | 1510 | /* Found it - now remove it from the list of entries: */ |
f17c7545 | 1511 | *action_ptr = action->next; |
ae88a23b | 1512 | |
cab303be TG |
1513 | irq_pm_remove_action(desc, action); |
1514 | ||
ae88a23b | 1515 | /* If this was the last handler, shut down the IRQ line: */ |
c1bacbae | 1516 | if (!desc->action) { |
e9849777 | 1517 | irq_settings_clr_disable_unlazy(desc); |
46999238 | 1518 | irq_shutdown(desc); |
c1bacbae TG |
1519 | irq_release_resources(desc); |
1520 | } | |
3aa551c9 | 1521 | |
e7a297b0 PWJ |
1522 | #ifdef CONFIG_SMP |
1523 | /* make sure affinity_hint is cleaned up */ | |
1524 | if (WARN_ON_ONCE(desc->affinity_hint)) | |
1525 | desc->affinity_hint = NULL; | |
1526 | #endif | |
1527 | ||
239007b8 | 1528 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
abc7e40c | 1529 | chip_bus_sync_unlock(desc); |
ae88a23b IM |
1530 | |
1531 | unregister_handler_proc(irq, action); | |
1532 | ||
1533 | /* Make sure it's not being used on another CPU: */ | |
1534 | synchronize_irq(irq); | |
1da177e4 | 1535 | |
70edcd77 | 1536 | #ifdef CONFIG_DEBUG_SHIRQ |
ae88a23b IM |
1537 | /* |
1538 | * It's a shared IRQ -- the driver ought to be prepared for an IRQ | |
1539 | * event to happen even now it's being freed, so let's make sure that | |
1540 | * is so by doing an extra call to the handler .... | |
1541 | * | |
1542 | * ( We do this after actually deregistering it, to make sure that a | |
1543 | * 'real' IRQ doesn't run in * parallel with our fake. ) | |
1544 | */ | |
1545 | if (action->flags & IRQF_SHARED) { | |
1546 | local_irq_save(flags); | |
1547 | action->handler(irq, dev_id); | |
1548 | local_irq_restore(flags); | |
1da177e4 | 1549 | } |
ae88a23b | 1550 | #endif |
2d860ad7 LT |
1551 | |
1552 | if (action->thread) { | |
05d74efa | 1553 | kthread_stop(action->thread); |
2d860ad7 | 1554 | put_task_struct(action->thread); |
2a1d3ab8 TG |
1555 | if (action->secondary && action->secondary->thread) { |
1556 | kthread_stop(action->secondary->thread); | |
1557 | put_task_struct(action->secondary->thread); | |
1558 | } | |
2d860ad7 LT |
1559 | } |
1560 | ||
be45beb2 | 1561 | irq_chip_pm_put(&desc->irq_data); |
b6873807 | 1562 | module_put(desc->owner); |
2a1d3ab8 | 1563 | kfree(action->secondary); |
f21cfb25 MD |
1564 | return action; |
1565 | } | |
1566 | ||
cbf94f06 MD |
1567 | /** |
1568 | * remove_irq - free an interrupt | |
1569 | * @irq: Interrupt line to free | |
1570 | * @act: irqaction for the interrupt | |
1571 | * | |
1572 | * Used to remove interrupts statically setup by the early boot process. | |
1573 | */ | |
1574 | void remove_irq(unsigned int irq, struct irqaction *act) | |
1575 | { | |
31d9d9b6 MZ |
1576 | struct irq_desc *desc = irq_to_desc(irq); |
1577 | ||
1578 | if (desc && !WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
a7e60e55 | 1579 | __free_irq(irq, act->dev_id); |
cbf94f06 | 1580 | } |
eb53b4e8 | 1581 | EXPORT_SYMBOL_GPL(remove_irq); |
cbf94f06 | 1582 | |
f21cfb25 MD |
1583 | /** |
1584 | * free_irq - free an interrupt allocated with request_irq | |
1585 | * @irq: Interrupt line to free | |
1586 | * @dev_id: Device identity to free | |
1587 | * | |
1588 | * Remove an interrupt handler. The handler is removed and if the | |
1589 | * interrupt line is no longer in use by any driver it is disabled. | |
1590 | * On a shared IRQ the caller must ensure the interrupt is disabled | |
1591 | * on the card it drives before calling this function. The function | |
1592 | * does not return until any executing interrupts for this IRQ | |
1593 | * have completed. | |
1594 | * | |
1595 | * This function must not be called from interrupt context. | |
25ce4be7 CH |
1596 | * |
1597 | * Returns the devname argument passed to request_irq. | |
f21cfb25 | 1598 | */ |
25ce4be7 | 1599 | const void *free_irq(unsigned int irq, void *dev_id) |
f21cfb25 | 1600 | { |
70aedd24 | 1601 | struct irq_desc *desc = irq_to_desc(irq); |
25ce4be7 CH |
1602 | struct irqaction *action; |
1603 | const char *devname; | |
70aedd24 | 1604 | |
31d9d9b6 | 1605 | if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) |
25ce4be7 | 1606 | return NULL; |
70aedd24 | 1607 | |
cd7eab44 BH |
1608 | #ifdef CONFIG_SMP |
1609 | if (WARN_ON(desc->affinity_notify)) | |
1610 | desc->affinity_notify = NULL; | |
1611 | #endif | |
1612 | ||
25ce4be7 CH |
1613 | action = __free_irq(irq, dev_id); |
1614 | devname = action->name; | |
1615 | kfree(action); | |
1616 | return devname; | |
1da177e4 | 1617 | } |
1da177e4 LT |
1618 | EXPORT_SYMBOL(free_irq); |
1619 | ||
1620 | /** | |
3aa551c9 | 1621 | * request_threaded_irq - allocate an interrupt line |
1da177e4 | 1622 | * @irq: Interrupt line to allocate |
3aa551c9 TG |
1623 | * @handler: Function to be called when the IRQ occurs. |
1624 | * Primary handler for threaded interrupts | |
b25c340c TG |
1625 | * If NULL and thread_fn != NULL the default |
1626 | * primary handler is installed | |
f48fe81e TG |
1627 | * @thread_fn: Function called from the irq handler thread |
1628 | * If NULL, no irq thread is created | |
1da177e4 LT |
1629 | * @irqflags: Interrupt type flags |
1630 | * @devname: An ascii name for the claiming device | |
1631 | * @dev_id: A cookie passed back to the handler function | |
1632 | * | |
1633 | * This call allocates interrupt resources and enables the | |
1634 | * interrupt line and IRQ handling. From the point this | |
1635 | * call is made your handler function may be invoked. Since | |
1636 | * your handler function must clear any interrupt the board | |
1637 | * raises, you must take care both to initialise your hardware | |
1638 | * and to set up the interrupt handler in the right order. | |
1639 | * | |
3aa551c9 | 1640 | * If you want to set up a threaded irq handler for your device |
6d21af4f | 1641 | * then you need to supply @handler and @thread_fn. @handler is |
3aa551c9 TG |
1642 | * still called in hard interrupt context and has to check |
1643 | * whether the interrupt originates from the device. If yes it | |
1644 | * needs to disable the interrupt on the device and return | |
39a2eddb | 1645 | * IRQ_WAKE_THREAD which will wake up the handler thread and run |
3aa551c9 TG |
1646 | * @thread_fn. This split handler design is necessary to support |
1647 | * shared interrupts. | |
1648 | * | |
1da177e4 LT |
1649 | * Dev_id must be globally unique. Normally the address of the |
1650 | * device data structure is used as the cookie. Since the handler | |
1651 | * receives this value it makes sense to use it. | |
1652 | * | |
1653 | * If your interrupt is shared you must pass a non NULL dev_id | |
1654 | * as this is required when freeing the interrupt. | |
1655 | * | |
1656 | * Flags: | |
1657 | * | |
3cca53b0 | 1658 | * IRQF_SHARED Interrupt is shared |
0c5d1eb7 | 1659 | * IRQF_TRIGGER_* Specify active edge(s) or level |
1da177e4 LT |
1660 | * |
1661 | */ | |
3aa551c9 TG |
1662 | int request_threaded_irq(unsigned int irq, irq_handler_t handler, |
1663 | irq_handler_t thread_fn, unsigned long irqflags, | |
1664 | const char *devname, void *dev_id) | |
1da177e4 | 1665 | { |
06fcb0c6 | 1666 | struct irqaction *action; |
08678b08 | 1667 | struct irq_desc *desc; |
d3c60047 | 1668 | int retval; |
1da177e4 | 1669 | |
e237a551 CF |
1670 | if (irq == IRQ_NOTCONNECTED) |
1671 | return -ENOTCONN; | |
1672 | ||
1da177e4 LT |
1673 | /* |
1674 | * Sanity-check: shared interrupts must pass in a real dev-ID, | |
1675 | * otherwise we'll have trouble later trying to figure out | |
1676 | * which interrupt is which (messes up the interrupt freeing | |
1677 | * logic etc). | |
17f48034 RW |
1678 | * |
1679 | * Also IRQF_COND_SUSPEND only makes sense for shared interrupts and | |
1680 | * it cannot be set along with IRQF_NO_SUSPEND. | |
1da177e4 | 1681 | */ |
17f48034 RW |
1682 | if (((irqflags & IRQF_SHARED) && !dev_id) || |
1683 | (!(irqflags & IRQF_SHARED) && (irqflags & IRQF_COND_SUSPEND)) || | |
1684 | ((irqflags & IRQF_NO_SUSPEND) && (irqflags & IRQF_COND_SUSPEND))) | |
1da177e4 | 1685 | return -EINVAL; |
7d94f7ca | 1686 | |
cb5bc832 | 1687 | desc = irq_to_desc(irq); |
7d94f7ca | 1688 | if (!desc) |
1da177e4 | 1689 | return -EINVAL; |
7d94f7ca | 1690 | |
31d9d9b6 MZ |
1691 | if (!irq_settings_can_request(desc) || |
1692 | WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
6550c775 | 1693 | return -EINVAL; |
b25c340c TG |
1694 | |
1695 | if (!handler) { | |
1696 | if (!thread_fn) | |
1697 | return -EINVAL; | |
1698 | handler = irq_default_primary_handler; | |
1699 | } | |
1da177e4 | 1700 | |
45535732 | 1701 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); |
1da177e4 LT |
1702 | if (!action) |
1703 | return -ENOMEM; | |
1704 | ||
1705 | action->handler = handler; | |
3aa551c9 | 1706 | action->thread_fn = thread_fn; |
1da177e4 | 1707 | action->flags = irqflags; |
1da177e4 | 1708 | action->name = devname; |
1da177e4 LT |
1709 | action->dev_id = dev_id; |
1710 | ||
be45beb2 | 1711 | retval = irq_chip_pm_get(&desc->irq_data); |
4396f46c SL |
1712 | if (retval < 0) { |
1713 | kfree(action); | |
be45beb2 | 1714 | return retval; |
4396f46c | 1715 | } |
be45beb2 | 1716 | |
3876ec9e | 1717 | chip_bus_lock(desc); |
d3c60047 | 1718 | retval = __setup_irq(irq, desc, action); |
3876ec9e | 1719 | chip_bus_sync_unlock(desc); |
70aedd24 | 1720 | |
2a1d3ab8 | 1721 | if (retval) { |
be45beb2 | 1722 | irq_chip_pm_put(&desc->irq_data); |
2a1d3ab8 | 1723 | kfree(action->secondary); |
377bf1e4 | 1724 | kfree(action); |
2a1d3ab8 | 1725 | } |
377bf1e4 | 1726 | |
6d83f94d | 1727 | #ifdef CONFIG_DEBUG_SHIRQ_FIXME |
6ce51c43 | 1728 | if (!retval && (irqflags & IRQF_SHARED)) { |
a304e1b8 DW |
1729 | /* |
1730 | * It's a shared IRQ -- the driver ought to be prepared for it | |
1731 | * to happen immediately, so let's make sure.... | |
377bf1e4 AV |
1732 | * We disable the irq to make sure that a 'real' IRQ doesn't |
1733 | * run in parallel with our fake. | |
a304e1b8 | 1734 | */ |
59845b1f | 1735 | unsigned long flags; |
a304e1b8 | 1736 | |
377bf1e4 | 1737 | disable_irq(irq); |
59845b1f | 1738 | local_irq_save(flags); |
377bf1e4 | 1739 | |
59845b1f | 1740 | handler(irq, dev_id); |
377bf1e4 | 1741 | |
59845b1f | 1742 | local_irq_restore(flags); |
377bf1e4 | 1743 | enable_irq(irq); |
a304e1b8 DW |
1744 | } |
1745 | #endif | |
1da177e4 LT |
1746 | return retval; |
1747 | } | |
3aa551c9 | 1748 | EXPORT_SYMBOL(request_threaded_irq); |
ae731f8d MZ |
1749 | |
1750 | /** | |
1751 | * request_any_context_irq - allocate an interrupt line | |
1752 | * @irq: Interrupt line to allocate | |
1753 | * @handler: Function to be called when the IRQ occurs. | |
1754 | * Threaded handler for threaded interrupts. | |
1755 | * @flags: Interrupt type flags | |
1756 | * @name: An ascii name for the claiming device | |
1757 | * @dev_id: A cookie passed back to the handler function | |
1758 | * | |
1759 | * This call allocates interrupt resources and enables the | |
1760 | * interrupt line and IRQ handling. It selects either a | |
1761 | * hardirq or threaded handling method depending on the | |
1762 | * context. | |
1763 | * | |
1764 | * On failure, it returns a negative value. On success, | |
1765 | * it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED. | |
1766 | */ | |
1767 | int request_any_context_irq(unsigned int irq, irq_handler_t handler, | |
1768 | unsigned long flags, const char *name, void *dev_id) | |
1769 | { | |
e237a551 | 1770 | struct irq_desc *desc; |
ae731f8d MZ |
1771 | int ret; |
1772 | ||
e237a551 CF |
1773 | if (irq == IRQ_NOTCONNECTED) |
1774 | return -ENOTCONN; | |
1775 | ||
1776 | desc = irq_to_desc(irq); | |
ae731f8d MZ |
1777 | if (!desc) |
1778 | return -EINVAL; | |
1779 | ||
1ccb4e61 | 1780 | if (irq_settings_is_nested_thread(desc)) { |
ae731f8d MZ |
1781 | ret = request_threaded_irq(irq, NULL, handler, |
1782 | flags, name, dev_id); | |
1783 | return !ret ? IRQC_IS_NESTED : ret; | |
1784 | } | |
1785 | ||
1786 | ret = request_irq(irq, handler, flags, name, dev_id); | |
1787 | return !ret ? IRQC_IS_HARDIRQ : ret; | |
1788 | } | |
1789 | EXPORT_SYMBOL_GPL(request_any_context_irq); | |
31d9d9b6 | 1790 | |
1e7c5fd2 | 1791 | void enable_percpu_irq(unsigned int irq, unsigned int type) |
31d9d9b6 MZ |
1792 | { |
1793 | unsigned int cpu = smp_processor_id(); | |
1794 | unsigned long flags; | |
1795 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
1796 | ||
1797 | if (!desc) | |
1798 | return; | |
1799 | ||
f35ad083 MZ |
1800 | /* |
1801 | * If the trigger type is not specified by the caller, then | |
1802 | * use the default for this interrupt. | |
1803 | */ | |
1e7c5fd2 | 1804 | type &= IRQ_TYPE_SENSE_MASK; |
f35ad083 MZ |
1805 | if (type == IRQ_TYPE_NONE) |
1806 | type = irqd_get_trigger_type(&desc->irq_data); | |
1807 | ||
1e7c5fd2 MZ |
1808 | if (type != IRQ_TYPE_NONE) { |
1809 | int ret; | |
1810 | ||
a1ff541a | 1811 | ret = __irq_set_trigger(desc, type); |
1e7c5fd2 MZ |
1812 | |
1813 | if (ret) { | |
32cffdde | 1814 | WARN(1, "failed to set type for IRQ%d\n", irq); |
1e7c5fd2 MZ |
1815 | goto out; |
1816 | } | |
1817 | } | |
1818 | ||
31d9d9b6 | 1819 | irq_percpu_enable(desc, cpu); |
1e7c5fd2 | 1820 | out: |
31d9d9b6 MZ |
1821 | irq_put_desc_unlock(desc, flags); |
1822 | } | |
36a5df85 | 1823 | EXPORT_SYMBOL_GPL(enable_percpu_irq); |
31d9d9b6 | 1824 | |
f0cb3220 TP |
1825 | /** |
1826 | * irq_percpu_is_enabled - Check whether the per cpu irq is enabled | |
1827 | * @irq: Linux irq number to check for | |
1828 | * | |
1829 | * Must be called from a non migratable context. Returns the enable | |
1830 | * state of a per cpu interrupt on the current cpu. | |
1831 | */ | |
1832 | bool irq_percpu_is_enabled(unsigned int irq) | |
1833 | { | |
1834 | unsigned int cpu = smp_processor_id(); | |
1835 | struct irq_desc *desc; | |
1836 | unsigned long flags; | |
1837 | bool is_enabled; | |
1838 | ||
1839 | desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
1840 | if (!desc) | |
1841 | return false; | |
1842 | ||
1843 | is_enabled = cpumask_test_cpu(cpu, desc->percpu_enabled); | |
1844 | irq_put_desc_unlock(desc, flags); | |
1845 | ||
1846 | return is_enabled; | |
1847 | } | |
1848 | EXPORT_SYMBOL_GPL(irq_percpu_is_enabled); | |
1849 | ||
31d9d9b6 MZ |
1850 | void disable_percpu_irq(unsigned int irq) |
1851 | { | |
1852 | unsigned int cpu = smp_processor_id(); | |
1853 | unsigned long flags; | |
1854 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
1855 | ||
1856 | if (!desc) | |
1857 | return; | |
1858 | ||
1859 | irq_percpu_disable(desc, cpu); | |
1860 | irq_put_desc_unlock(desc, flags); | |
1861 | } | |
36a5df85 | 1862 | EXPORT_SYMBOL_GPL(disable_percpu_irq); |
31d9d9b6 MZ |
1863 | |
1864 | /* | |
1865 | * Internal function to unregister a percpu irqaction. | |
1866 | */ | |
1867 | static struct irqaction *__free_percpu_irq(unsigned int irq, void __percpu *dev_id) | |
1868 | { | |
1869 | struct irq_desc *desc = irq_to_desc(irq); | |
1870 | struct irqaction *action; | |
1871 | unsigned long flags; | |
1872 | ||
1873 | WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq); | |
1874 | ||
1875 | if (!desc) | |
1876 | return NULL; | |
1877 | ||
1878 | raw_spin_lock_irqsave(&desc->lock, flags); | |
1879 | ||
1880 | action = desc->action; | |
1881 | if (!action || action->percpu_dev_id != dev_id) { | |
1882 | WARN(1, "Trying to free already-free IRQ %d\n", irq); | |
1883 | goto bad; | |
1884 | } | |
1885 | ||
1886 | if (!cpumask_empty(desc->percpu_enabled)) { | |
1887 | WARN(1, "percpu IRQ %d still enabled on CPU%d!\n", | |
1888 | irq, cpumask_first(desc->percpu_enabled)); | |
1889 | goto bad; | |
1890 | } | |
1891 | ||
1892 | /* Found it - now remove it from the list of entries: */ | |
1893 | desc->action = NULL; | |
1894 | ||
1895 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1896 | ||
1897 | unregister_handler_proc(irq, action); | |
1898 | ||
be45beb2 | 1899 | irq_chip_pm_put(&desc->irq_data); |
31d9d9b6 MZ |
1900 | module_put(desc->owner); |
1901 | return action; | |
1902 | ||
1903 | bad: | |
1904 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1905 | return NULL; | |
1906 | } | |
1907 | ||
1908 | /** | |
1909 | * remove_percpu_irq - free a per-cpu interrupt | |
1910 | * @irq: Interrupt line to free | |
1911 | * @act: irqaction for the interrupt | |
1912 | * | |
1913 | * Used to remove interrupts statically setup by the early boot process. | |
1914 | */ | |
1915 | void remove_percpu_irq(unsigned int irq, struct irqaction *act) | |
1916 | { | |
1917 | struct irq_desc *desc = irq_to_desc(irq); | |
1918 | ||
1919 | if (desc && irq_settings_is_per_cpu_devid(desc)) | |
1920 | __free_percpu_irq(irq, act->percpu_dev_id); | |
1921 | } | |
1922 | ||
1923 | /** | |
1924 | * free_percpu_irq - free an interrupt allocated with request_percpu_irq | |
1925 | * @irq: Interrupt line to free | |
1926 | * @dev_id: Device identity to free | |
1927 | * | |
1928 | * Remove a percpu interrupt handler. The handler is removed, but | |
1929 | * the interrupt line is not disabled. This must be done on each | |
1930 | * CPU before calling this function. The function does not return | |
1931 | * until any executing interrupts for this IRQ have completed. | |
1932 | * | |
1933 | * This function must not be called from interrupt context. | |
1934 | */ | |
1935 | void free_percpu_irq(unsigned int irq, void __percpu *dev_id) | |
1936 | { | |
1937 | struct irq_desc *desc = irq_to_desc(irq); | |
1938 | ||
1939 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
1940 | return; | |
1941 | ||
1942 | chip_bus_lock(desc); | |
1943 | kfree(__free_percpu_irq(irq, dev_id)); | |
1944 | chip_bus_sync_unlock(desc); | |
1945 | } | |
aec2e2ad | 1946 | EXPORT_SYMBOL_GPL(free_percpu_irq); |
31d9d9b6 MZ |
1947 | |
1948 | /** | |
1949 | * setup_percpu_irq - setup a per-cpu interrupt | |
1950 | * @irq: Interrupt line to setup | |
1951 | * @act: irqaction for the interrupt | |
1952 | * | |
1953 | * Used to statically setup per-cpu interrupts in the early boot process. | |
1954 | */ | |
1955 | int setup_percpu_irq(unsigned int irq, struct irqaction *act) | |
1956 | { | |
1957 | struct irq_desc *desc = irq_to_desc(irq); | |
1958 | int retval; | |
1959 | ||
1960 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
1961 | return -EINVAL; | |
be45beb2 JH |
1962 | |
1963 | retval = irq_chip_pm_get(&desc->irq_data); | |
1964 | if (retval < 0) | |
1965 | return retval; | |
1966 | ||
31d9d9b6 MZ |
1967 | chip_bus_lock(desc); |
1968 | retval = __setup_irq(irq, desc, act); | |
1969 | chip_bus_sync_unlock(desc); | |
1970 | ||
be45beb2 JH |
1971 | if (retval) |
1972 | irq_chip_pm_put(&desc->irq_data); | |
1973 | ||
31d9d9b6 MZ |
1974 | return retval; |
1975 | } | |
1976 | ||
1977 | /** | |
1978 | * request_percpu_irq - allocate a percpu interrupt line | |
1979 | * @irq: Interrupt line to allocate | |
1980 | * @handler: Function to be called when the IRQ occurs. | |
1981 | * @devname: An ascii name for the claiming device | |
1982 | * @dev_id: A percpu cookie passed back to the handler function | |
1983 | * | |
a1b7febd MR |
1984 | * This call allocates interrupt resources and enables the |
1985 | * interrupt on the local CPU. If the interrupt is supposed to be | |
1986 | * enabled on other CPUs, it has to be done on each CPU using | |
1987 | * enable_percpu_irq(). | |
31d9d9b6 MZ |
1988 | * |
1989 | * Dev_id must be globally unique. It is a per-cpu variable, and | |
1990 | * the handler gets called with the interrupted CPU's instance of | |
1991 | * that variable. | |
1992 | */ | |
1993 | int request_percpu_irq(unsigned int irq, irq_handler_t handler, | |
1994 | const char *devname, void __percpu *dev_id) | |
1995 | { | |
1996 | struct irqaction *action; | |
1997 | struct irq_desc *desc; | |
1998 | int retval; | |
1999 | ||
2000 | if (!dev_id) | |
2001 | return -EINVAL; | |
2002 | ||
2003 | desc = irq_to_desc(irq); | |
2004 | if (!desc || !irq_settings_can_request(desc) || | |
2005 | !irq_settings_is_per_cpu_devid(desc)) | |
2006 | return -EINVAL; | |
2007 | ||
2008 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); | |
2009 | if (!action) | |
2010 | return -ENOMEM; | |
2011 | ||
2012 | action->handler = handler; | |
2ed0e645 | 2013 | action->flags = IRQF_PERCPU | IRQF_NO_SUSPEND; |
31d9d9b6 MZ |
2014 | action->name = devname; |
2015 | action->percpu_dev_id = dev_id; | |
2016 | ||
be45beb2 | 2017 | retval = irq_chip_pm_get(&desc->irq_data); |
4396f46c SL |
2018 | if (retval < 0) { |
2019 | kfree(action); | |
be45beb2 | 2020 | return retval; |
4396f46c | 2021 | } |
be45beb2 | 2022 | |
31d9d9b6 MZ |
2023 | chip_bus_lock(desc); |
2024 | retval = __setup_irq(irq, desc, action); | |
2025 | chip_bus_sync_unlock(desc); | |
2026 | ||
be45beb2 JH |
2027 | if (retval) { |
2028 | irq_chip_pm_put(&desc->irq_data); | |
31d9d9b6 | 2029 | kfree(action); |
be45beb2 | 2030 | } |
31d9d9b6 MZ |
2031 | |
2032 | return retval; | |
2033 | } | |
aec2e2ad | 2034 | EXPORT_SYMBOL_GPL(request_percpu_irq); |
1b7047ed MZ |
2035 | |
2036 | /** | |
2037 | * irq_get_irqchip_state - returns the irqchip state of a interrupt. | |
2038 | * @irq: Interrupt line that is forwarded to a VM | |
2039 | * @which: One of IRQCHIP_STATE_* the caller wants to know about | |
2040 | * @state: a pointer to a boolean where the state is to be storeed | |
2041 | * | |
2042 | * This call snapshots the internal irqchip state of an | |
2043 | * interrupt, returning into @state the bit corresponding to | |
2044 | * stage @which | |
2045 | * | |
2046 | * This function should be called with preemption disabled if the | |
2047 | * interrupt controller has per-cpu registers. | |
2048 | */ | |
2049 | int irq_get_irqchip_state(unsigned int irq, enum irqchip_irq_state which, | |
2050 | bool *state) | |
2051 | { | |
2052 | struct irq_desc *desc; | |
2053 | struct irq_data *data; | |
2054 | struct irq_chip *chip; | |
2055 | unsigned long flags; | |
2056 | int err = -EINVAL; | |
2057 | ||
2058 | desc = irq_get_desc_buslock(irq, &flags, 0); | |
2059 | if (!desc) | |
2060 | return err; | |
2061 | ||
2062 | data = irq_desc_get_irq_data(desc); | |
2063 | ||
2064 | do { | |
2065 | chip = irq_data_get_irq_chip(data); | |
2066 | if (chip->irq_get_irqchip_state) | |
2067 | break; | |
2068 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
2069 | data = data->parent_data; | |
2070 | #else | |
2071 | data = NULL; | |
2072 | #endif | |
2073 | } while (data); | |
2074 | ||
2075 | if (data) | |
2076 | err = chip->irq_get_irqchip_state(data, which, state); | |
2077 | ||
2078 | irq_put_desc_busunlock(desc, flags); | |
2079 | return err; | |
2080 | } | |
1ee4fb3e | 2081 | EXPORT_SYMBOL_GPL(irq_get_irqchip_state); |
1b7047ed MZ |
2082 | |
2083 | /** | |
2084 | * irq_set_irqchip_state - set the state of a forwarded interrupt. | |
2085 | * @irq: Interrupt line that is forwarded to a VM | |
2086 | * @which: State to be restored (one of IRQCHIP_STATE_*) | |
2087 | * @val: Value corresponding to @which | |
2088 | * | |
2089 | * This call sets the internal irqchip state of an interrupt, | |
2090 | * depending on the value of @which. | |
2091 | * | |
2092 | * This function should be called with preemption disabled if the | |
2093 | * interrupt controller has per-cpu registers. | |
2094 | */ | |
2095 | int irq_set_irqchip_state(unsigned int irq, enum irqchip_irq_state which, | |
2096 | bool val) | |
2097 | { | |
2098 | struct irq_desc *desc; | |
2099 | struct irq_data *data; | |
2100 | struct irq_chip *chip; | |
2101 | unsigned long flags; | |
2102 | int err = -EINVAL; | |
2103 | ||
2104 | desc = irq_get_desc_buslock(irq, &flags, 0); | |
2105 | if (!desc) | |
2106 | return err; | |
2107 | ||
2108 | data = irq_desc_get_irq_data(desc); | |
2109 | ||
2110 | do { | |
2111 | chip = irq_data_get_irq_chip(data); | |
2112 | if (chip->irq_set_irqchip_state) | |
2113 | break; | |
2114 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
2115 | data = data->parent_data; | |
2116 | #else | |
2117 | data = NULL; | |
2118 | #endif | |
2119 | } while (data); | |
2120 | ||
2121 | if (data) | |
2122 | err = chip->irq_set_irqchip_state(data, which, val); | |
2123 | ||
2124 | irq_put_desc_busunlock(desc, flags); | |
2125 | return err; | |
2126 | } | |
1ee4fb3e | 2127 | EXPORT_SYMBOL_GPL(irq_set_irqchip_state); |