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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
c777ac55 | 2 | |
d824e66a | 3 | #include <linux/irq.h> |
57b150cc YL |
4 | #include <linux/interrupt.h> |
5 | ||
6 | #include "internals.h" | |
c777ac55 | 7 | |
cdd16365 TG |
8 | /** |
9 | * irq_fixup_move_pending - Cleanup irq move pending from a dying CPU | |
10 | * @desc: Interrupt descpriptor to clean up | |
11 | * @force_clear: If set clear the move pending bit unconditionally. | |
12 | * If not set, clear it only when the dying CPU is the | |
13 | * last one in the pending mask. | |
14 | * | |
15 | * Returns true if the pending bit was set and the pending mask contains an | |
16 | * online CPU other than the dying CPU. | |
17 | */ | |
18 | bool irq_fixup_move_pending(struct irq_desc *desc, bool force_clear) | |
19 | { | |
20 | struct irq_data *data = irq_desc_get_irq_data(desc); | |
21 | ||
22 | if (!irqd_is_setaffinity_pending(data)) | |
23 | return false; | |
24 | ||
25 | /* | |
26 | * The outgoing CPU might be the last online target in a pending | |
27 | * interrupt move. If that's the case clear the pending move bit. | |
28 | */ | |
29 | if (cpumask_any_and(desc->pending_mask, cpu_online_mask) >= nr_cpu_ids) { | |
30 | irqd_clr_move_pending(data); | |
31 | return false; | |
32 | } | |
33 | if (force_clear) | |
34 | irqd_clr_move_pending(data); | |
35 | return true; | |
36 | } | |
37 | ||
a439520f | 38 | void irq_move_masked_irq(struct irq_data *idata) |
c777ac55 | 39 | { |
a439520f | 40 | struct irq_desc *desc = irq_data_to_desc(idata); |
5301810f TG |
41 | struct irq_data *data = &desc->irq_data; |
42 | struct irq_chip *chip = data->chip; | |
c777ac55 | 43 | |
5301810f | 44 | if (likely(!irqd_is_setaffinity_pending(data))) |
c777ac55 AM |
45 | return; |
46 | ||
5301810f | 47 | irqd_clr_move_pending(data); |
a614a610 | 48 | |
501f2499 BH |
49 | /* |
50 | * Paranoia: cpu-local interrupts shouldn't be calling in here anyway. | |
51 | */ | |
5301810f | 52 | if (irqd_is_per_cpu(data)) { |
501f2499 BH |
53 | WARN_ON(1); |
54 | return; | |
55 | } | |
56 | ||
7f7ace0c | 57 | if (unlikely(cpumask_empty(desc->pending_mask))) |
c777ac55 AM |
58 | return; |
59 | ||
c96b3b3c | 60 | if (!chip->irq_set_affinity) |
c777ac55 AM |
61 | return; |
62 | ||
239007b8 | 63 | assert_raw_spin_locked(&desc->lock); |
501f2499 | 64 | |
c777ac55 AM |
65 | /* |
66 | * If there was a valid mask to work with, please | |
67 | * do the disable, re-program, enable sequence. | |
68 | * This is *not* particularly important for level triggered | |
69 | * but in a edge trigger case, we might be setting rte | |
25985edc | 70 | * when an active trigger is coming in. This could |
c777ac55 AM |
71 | * cause some ioapics to mal-function. |
72 | * Being paranoid i guess! | |
e7b946e9 EB |
73 | * |
74 | * For correct operation this depends on the caller | |
75 | * masking the irqs. | |
c777ac55 | 76 | */ |
5301810f TG |
77 | if (cpumask_any_and(desc->pending_mask, cpu_online_mask) < nr_cpu_ids) { |
78 | int ret; | |
79 | ||
80 | ret = irq_do_set_affinity(data, desc->pending_mask, false); | |
81 | /* | |
82 | * If the there is a cleanup pending in the underlying | |
83 | * vector management, reschedule the move for the next | |
84 | * interrupt. Leave desc->pending_mask intact. | |
85 | */ | |
86 | if (ret == -EBUSY) { | |
87 | irqd_set_move_pending(data); | |
88 | return; | |
89 | } | |
90 | } | |
7f7ace0c | 91 | cpumask_clear(desc->pending_mask); |
c777ac55 | 92 | } |
e7b946e9 | 93 | |
7d2e1b76 | 94 | void __irq_move_irq(struct irq_data *idata) |
e7b946e9 | 95 | { |
f1a06390 | 96 | bool masked; |
e7b946e9 | 97 | |
77ed42f1 JL |
98 | /* |
99 | * Get top level irq_data when CONFIG_IRQ_DOMAIN_HIERARCHY is enabled, | |
100 | * and it should be optimized away when CONFIG_IRQ_DOMAIN_HIERARCHY is | |
101 | * disabled. So we avoid an "#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY" here. | |
102 | */ | |
103 | idata = irq_desc_get_irq_data(irq_data_to_desc(idata)); | |
104 | ||
32f4125e | 105 | if (unlikely(irqd_irq_disabled(idata))) |
2a786b45 | 106 | return; |
e7b946e9 | 107 | |
f1a06390 TG |
108 | /* |
109 | * Be careful vs. already masked interrupts. If this is a | |
110 | * threaded interrupt with ONESHOT set, we can end up with an | |
111 | * interrupt storm. | |
112 | */ | |
32f4125e | 113 | masked = irqd_irq_masked(idata); |
f1a06390 | 114 | if (!masked) |
a439520f TG |
115 | idata->chip->irq_mask(idata); |
116 | irq_move_masked_irq(idata); | |
f1a06390 | 117 | if (!masked) |
a439520f TG |
118 | idata->chip->irq_unmask(idata); |
119 | } |